1 /* 2 * Kernel-based Virtual Machine driver for Linux 3 * 4 * derived from drivers/kvm/kvm_main.c 5 * 6 * Copyright (C) 2006 Qumranet, Inc. 7 * Copyright (C) 2008 Qumranet, Inc. 8 * Copyright IBM Corporation, 2008 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 * Amit Shah <amit.shah@qumranet.com> 15 * Ben-Ami Yassour <benami@il.ibm.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 */ 21 22 #include <linux/kvm_host.h> 23 #include "irq.h" 24 #include "mmu.h" 25 #include "i8254.h" 26 #include "tss.h" 27 #include "kvm_cache_regs.h" 28 #include "x86.h" 29 #include "cpuid.h" 30 31 #include <linux/clocksource.h> 32 #include <linux/interrupt.h> 33 #include <linux/kvm.h> 34 #include <linux/fs.h> 35 #include <linux/vmalloc.h> 36 #include <linux/module.h> 37 #include <linux/mman.h> 38 #include <linux/highmem.h> 39 #include <linux/iommu.h> 40 #include <linux/intel-iommu.h> 41 #include <linux/cpufreq.h> 42 #include <linux/user-return-notifier.h> 43 #include <linux/srcu.h> 44 #include <linux/slab.h> 45 #include <linux/perf_event.h> 46 #include <linux/uaccess.h> 47 #include <linux/hash.h> 48 #include <linux/pci.h> 49 #include <linux/timekeeper_internal.h> 50 #include <linux/pvclock_gtod.h> 51 #include <trace/events/kvm.h> 52 53 #define CREATE_TRACE_POINTS 54 #include "trace.h" 55 56 #include <asm/debugreg.h> 57 #include <asm/msr.h> 58 #include <asm/desc.h> 59 #include <asm/mtrr.h> 60 #include <asm/mce.h> 61 #include <asm/i387.h> 62 #include <asm/fpu-internal.h> /* Ugh! */ 63 #include <asm/xcr.h> 64 #include <asm/pvclock.h> 65 #include <asm/div64.h> 66 67 #define MAX_IO_MSRS 256 68 #define KVM_MAX_MCE_BANKS 32 69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P) 70 71 #define emul_to_vcpu(ctxt) \ 72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt) 73 74 /* EFER defaults: 75 * - enable syscall per default because its emulated by KVM 76 * - enable LME and LMA per default on 64 bit KVM 77 */ 78 #ifdef CONFIG_X86_64 79 static 80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 81 #else 82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); 83 #endif 84 85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM 86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU 87 88 static void update_cr8_intercept(struct kvm_vcpu *vcpu); 89 static void process_nmi(struct kvm_vcpu *vcpu); 90 91 struct kvm_x86_ops *kvm_x86_ops; 92 EXPORT_SYMBOL_GPL(kvm_x86_ops); 93 94 static bool ignore_msrs = 0; 95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); 96 97 unsigned int min_timer_period_us = 500; 98 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); 99 100 bool kvm_has_tsc_control; 101 EXPORT_SYMBOL_GPL(kvm_has_tsc_control); 102 u32 kvm_max_guest_tsc_khz; 103 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz); 104 105 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ 106 static u32 tsc_tolerance_ppm = 250; 107 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); 108 109 #define KVM_NR_SHARED_MSRS 16 110 111 struct kvm_shared_msrs_global { 112 int nr; 113 u32 msrs[KVM_NR_SHARED_MSRS]; 114 }; 115 116 struct kvm_shared_msrs { 117 struct user_return_notifier urn; 118 bool registered; 119 struct kvm_shared_msr_values { 120 u64 host; 121 u64 curr; 122 } values[KVM_NR_SHARED_MSRS]; 123 }; 124 125 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; 126 static struct kvm_shared_msrs __percpu *shared_msrs; 127 128 struct kvm_stats_debugfs_item debugfs_entries[] = { 129 { "pf_fixed", VCPU_STAT(pf_fixed) }, 130 { "pf_guest", VCPU_STAT(pf_guest) }, 131 { "tlb_flush", VCPU_STAT(tlb_flush) }, 132 { "invlpg", VCPU_STAT(invlpg) }, 133 { "exits", VCPU_STAT(exits) }, 134 { "io_exits", VCPU_STAT(io_exits) }, 135 { "mmio_exits", VCPU_STAT(mmio_exits) }, 136 { "signal_exits", VCPU_STAT(signal_exits) }, 137 { "irq_window", VCPU_STAT(irq_window_exits) }, 138 { "nmi_window", VCPU_STAT(nmi_window_exits) }, 139 { "halt_exits", VCPU_STAT(halt_exits) }, 140 { "halt_wakeup", VCPU_STAT(halt_wakeup) }, 141 { "hypercalls", VCPU_STAT(hypercalls) }, 142 { "request_irq", VCPU_STAT(request_irq_exits) }, 143 { "irq_exits", VCPU_STAT(irq_exits) }, 144 { "host_state_reload", VCPU_STAT(host_state_reload) }, 145 { "efer_reload", VCPU_STAT(efer_reload) }, 146 { "fpu_reload", VCPU_STAT(fpu_reload) }, 147 { "insn_emulation", VCPU_STAT(insn_emulation) }, 148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, 149 { "irq_injections", VCPU_STAT(irq_injections) }, 150 { "nmi_injections", VCPU_STAT(nmi_injections) }, 151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, 152 { "mmu_pte_write", VM_STAT(mmu_pte_write) }, 153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, 154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, 155 { "mmu_flooded", VM_STAT(mmu_flooded) }, 156 { "mmu_recycled", VM_STAT(mmu_recycled) }, 157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, 158 { "mmu_unsync", VM_STAT(mmu_unsync) }, 159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, 160 { "largepages", VM_STAT(lpages) }, 161 { NULL } 162 }; 163 164 u64 __read_mostly host_xcr0; 165 166 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); 167 168 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 169 { 170 int i; 171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++) 172 vcpu->arch.apf.gfns[i] = ~0; 173 } 174 175 static void kvm_on_user_return(struct user_return_notifier *urn) 176 { 177 unsigned slot; 178 struct kvm_shared_msrs *locals 179 = container_of(urn, struct kvm_shared_msrs, urn); 180 struct kvm_shared_msr_values *values; 181 182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) { 183 values = &locals->values[slot]; 184 if (values->host != values->curr) { 185 wrmsrl(shared_msrs_global.msrs[slot], values->host); 186 values->curr = values->host; 187 } 188 } 189 locals->registered = false; 190 user_return_notifier_unregister(urn); 191 } 192 193 static void shared_msr_update(unsigned slot, u32 msr) 194 { 195 u64 value; 196 unsigned int cpu = smp_processor_id(); 197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 198 199 /* only read, and nobody should modify it at this time, 200 * so don't need lock */ 201 if (slot >= shared_msrs_global.nr) { 202 printk(KERN_ERR "kvm: invalid MSR slot!"); 203 return; 204 } 205 rdmsrl_safe(msr, &value); 206 smsr->values[slot].host = value; 207 smsr->values[slot].curr = value; 208 } 209 210 void kvm_define_shared_msr(unsigned slot, u32 msr) 211 { 212 if (slot >= shared_msrs_global.nr) 213 shared_msrs_global.nr = slot + 1; 214 shared_msrs_global.msrs[slot] = msr; 215 /* we need ensured the shared_msr_global have been updated */ 216 smp_wmb(); 217 } 218 EXPORT_SYMBOL_GPL(kvm_define_shared_msr); 219 220 static void kvm_shared_msr_cpu_online(void) 221 { 222 unsigned i; 223 224 for (i = 0; i < shared_msrs_global.nr; ++i) 225 shared_msr_update(i, shared_msrs_global.msrs[i]); 226 } 227 228 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 229 { 230 unsigned int cpu = smp_processor_id(); 231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 232 233 if (((value ^ smsr->values[slot].curr) & mask) == 0) 234 return; 235 smsr->values[slot].curr = value; 236 wrmsrl(shared_msrs_global.msrs[slot], value); 237 if (!smsr->registered) { 238 smsr->urn.on_user_return = kvm_on_user_return; 239 user_return_notifier_register(&smsr->urn); 240 smsr->registered = true; 241 } 242 } 243 EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 244 245 static void drop_user_return_notifiers(void *ignore) 246 { 247 unsigned int cpu = smp_processor_id(); 248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 249 250 if (smsr->registered) 251 kvm_on_user_return(&smsr->urn); 252 } 253 254 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) 255 { 256 return vcpu->arch.apic_base; 257 } 258 EXPORT_SYMBOL_GPL(kvm_get_apic_base); 259 260 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 261 { 262 u64 old_state = vcpu->arch.apic_base & 263 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 264 u64 new_state = msr_info->data & 265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 266 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 267 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE); 268 269 if (!msr_info->host_initiated && 270 ((msr_info->data & reserved_bits) != 0 || 271 new_state == X2APIC_ENABLE || 272 (new_state == MSR_IA32_APICBASE_ENABLE && 273 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) || 274 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) && 275 old_state == 0))) 276 return 1; 277 278 kvm_lapic_set_base(vcpu, msr_info->data); 279 return 0; 280 } 281 EXPORT_SYMBOL_GPL(kvm_set_apic_base); 282 283 asmlinkage void kvm_spurious_fault(void) 284 { 285 /* Fault while not rebooting. We want the trace. */ 286 BUG(); 287 } 288 EXPORT_SYMBOL_GPL(kvm_spurious_fault); 289 290 #define EXCPT_BENIGN 0 291 #define EXCPT_CONTRIBUTORY 1 292 #define EXCPT_PF 2 293 294 static int exception_class(int vector) 295 { 296 switch (vector) { 297 case PF_VECTOR: 298 return EXCPT_PF; 299 case DE_VECTOR: 300 case TS_VECTOR: 301 case NP_VECTOR: 302 case SS_VECTOR: 303 case GP_VECTOR: 304 return EXCPT_CONTRIBUTORY; 305 default: 306 break; 307 } 308 return EXCPT_BENIGN; 309 } 310 311 static void kvm_multiple_exception(struct kvm_vcpu *vcpu, 312 unsigned nr, bool has_error, u32 error_code, 313 bool reinject) 314 { 315 u32 prev_nr; 316 int class1, class2; 317 318 kvm_make_request(KVM_REQ_EVENT, vcpu); 319 320 if (!vcpu->arch.exception.pending) { 321 queue: 322 vcpu->arch.exception.pending = true; 323 vcpu->arch.exception.has_error_code = has_error; 324 vcpu->arch.exception.nr = nr; 325 vcpu->arch.exception.error_code = error_code; 326 vcpu->arch.exception.reinject = reinject; 327 return; 328 } 329 330 /* to check exception */ 331 prev_nr = vcpu->arch.exception.nr; 332 if (prev_nr == DF_VECTOR) { 333 /* triple fault -> shutdown */ 334 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 335 return; 336 } 337 class1 = exception_class(prev_nr); 338 class2 = exception_class(nr); 339 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) 340 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { 341 /* generate double fault per SDM Table 5-5 */ 342 vcpu->arch.exception.pending = true; 343 vcpu->arch.exception.has_error_code = true; 344 vcpu->arch.exception.nr = DF_VECTOR; 345 vcpu->arch.exception.error_code = 0; 346 } else 347 /* replace previous exception with a new one in a hope 348 that instruction re-execution will regenerate lost 349 exception */ 350 goto queue; 351 } 352 353 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) 354 { 355 kvm_multiple_exception(vcpu, nr, false, 0, false); 356 } 357 EXPORT_SYMBOL_GPL(kvm_queue_exception); 358 359 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) 360 { 361 kvm_multiple_exception(vcpu, nr, false, 0, true); 362 } 363 EXPORT_SYMBOL_GPL(kvm_requeue_exception); 364 365 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) 366 { 367 if (err) 368 kvm_inject_gp(vcpu, 0); 369 else 370 kvm_x86_ops->skip_emulated_instruction(vcpu); 371 } 372 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); 373 374 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 375 { 376 ++vcpu->stat.pf_guest; 377 vcpu->arch.cr2 = fault->address; 378 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); 379 } 380 EXPORT_SYMBOL_GPL(kvm_inject_page_fault); 381 382 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) 383 { 384 if (mmu_is_nested(vcpu) && !fault->nested_page_fault) 385 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault); 386 else 387 vcpu->arch.mmu.inject_page_fault(vcpu, fault); 388 } 389 390 void kvm_inject_nmi(struct kvm_vcpu *vcpu) 391 { 392 atomic_inc(&vcpu->arch.nmi_queued); 393 kvm_make_request(KVM_REQ_NMI, vcpu); 394 } 395 EXPORT_SYMBOL_GPL(kvm_inject_nmi); 396 397 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 398 { 399 kvm_multiple_exception(vcpu, nr, true, error_code, false); 400 } 401 EXPORT_SYMBOL_GPL(kvm_queue_exception_e); 402 403 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) 404 { 405 kvm_multiple_exception(vcpu, nr, true, error_code, true); 406 } 407 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); 408 409 /* 410 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue 411 * a #GP and return false. 412 */ 413 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) 414 { 415 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) 416 return true; 417 kvm_queue_exception_e(vcpu, GP_VECTOR, 0); 418 return false; 419 } 420 EXPORT_SYMBOL_GPL(kvm_require_cpl); 421 422 /* 423 * This function will be used to read from the physical memory of the currently 424 * running guest. The difference to kvm_read_guest_page is that this function 425 * can read from guest physical or from the guest's guest physical memory. 426 */ 427 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 428 gfn_t ngfn, void *data, int offset, int len, 429 u32 access) 430 { 431 gfn_t real_gfn; 432 gpa_t ngpa; 433 434 ngpa = gfn_to_gpa(ngfn); 435 real_gfn = mmu->translate_gpa(vcpu, ngpa, access); 436 if (real_gfn == UNMAPPED_GVA) 437 return -EFAULT; 438 439 real_gfn = gpa_to_gfn(real_gfn); 440 441 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len); 442 } 443 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu); 444 445 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn, 446 void *data, int offset, int len, u32 access) 447 { 448 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn, 449 data, offset, len, access); 450 } 451 452 /* 453 * Load the pae pdptrs. Return true is they are all valid. 454 */ 455 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3) 456 { 457 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; 458 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; 459 int i; 460 int ret; 461 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; 462 463 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte, 464 offset * sizeof(u64), sizeof(pdpte), 465 PFERR_USER_MASK|PFERR_WRITE_MASK); 466 if (ret < 0) { 467 ret = 0; 468 goto out; 469 } 470 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { 471 if (is_present_gpte(pdpte[i]) && 472 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { 473 ret = 0; 474 goto out; 475 } 476 } 477 ret = 1; 478 479 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); 480 __set_bit(VCPU_EXREG_PDPTR, 481 (unsigned long *)&vcpu->arch.regs_avail); 482 __set_bit(VCPU_EXREG_PDPTR, 483 (unsigned long *)&vcpu->arch.regs_dirty); 484 out: 485 486 return ret; 487 } 488 EXPORT_SYMBOL_GPL(load_pdptrs); 489 490 static bool pdptrs_changed(struct kvm_vcpu *vcpu) 491 { 492 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)]; 493 bool changed = true; 494 int offset; 495 gfn_t gfn; 496 int r; 497 498 if (is_long_mode(vcpu) || !is_pae(vcpu)) 499 return false; 500 501 if (!test_bit(VCPU_EXREG_PDPTR, 502 (unsigned long *)&vcpu->arch.regs_avail)) 503 return true; 504 505 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT; 506 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1); 507 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte), 508 PFERR_USER_MASK | PFERR_WRITE_MASK); 509 if (r < 0) 510 goto out; 511 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0; 512 out: 513 514 return changed; 515 } 516 517 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 518 { 519 unsigned long old_cr0 = kvm_read_cr0(vcpu); 520 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP | 521 X86_CR0_CD | X86_CR0_NW; 522 523 cr0 |= X86_CR0_ET; 524 525 #ifdef CONFIG_X86_64 526 if (cr0 & 0xffffffff00000000UL) 527 return 1; 528 #endif 529 530 cr0 &= ~CR0_RESERVED_BITS; 531 532 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) 533 return 1; 534 535 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) 536 return 1; 537 538 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { 539 #ifdef CONFIG_X86_64 540 if ((vcpu->arch.efer & EFER_LME)) { 541 int cs_db, cs_l; 542 543 if (!is_pae(vcpu)) 544 return 1; 545 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 546 if (cs_l) 547 return 1; 548 } else 549 #endif 550 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 551 kvm_read_cr3(vcpu))) 552 return 1; 553 } 554 555 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) 556 return 1; 557 558 kvm_x86_ops->set_cr0(vcpu, cr0); 559 560 if ((cr0 ^ old_cr0) & X86_CR0_PG) { 561 kvm_clear_async_pf_completion_queue(vcpu); 562 kvm_async_pf_hash_reset(vcpu); 563 } 564 565 if ((cr0 ^ old_cr0) & update_bits) 566 kvm_mmu_reset_context(vcpu); 567 return 0; 568 } 569 EXPORT_SYMBOL_GPL(kvm_set_cr0); 570 571 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) 572 { 573 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); 574 } 575 EXPORT_SYMBOL_GPL(kvm_lmsw); 576 577 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu) 578 { 579 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) && 580 !vcpu->guest_xcr0_loaded) { 581 /* kvm_set_xcr() also depends on this */ 582 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); 583 vcpu->guest_xcr0_loaded = 1; 584 } 585 } 586 587 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu) 588 { 589 if (vcpu->guest_xcr0_loaded) { 590 if (vcpu->arch.xcr0 != host_xcr0) 591 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); 592 vcpu->guest_xcr0_loaded = 0; 593 } 594 } 595 596 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 597 { 598 u64 xcr0 = xcr; 599 u64 old_xcr0 = vcpu->arch.xcr0; 600 u64 valid_bits; 601 602 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ 603 if (index != XCR_XFEATURE_ENABLED_MASK) 604 return 1; 605 if (!(xcr0 & XSTATE_FP)) 606 return 1; 607 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE)) 608 return 1; 609 610 /* 611 * Do not allow the guest to set bits that we do not support 612 * saving. However, xcr0 bit 0 is always set, even if the 613 * emulated CPU does not support XSAVE (see fx_init). 614 */ 615 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP; 616 if (xcr0 & ~valid_bits) 617 return 1; 618 619 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR))) 620 return 1; 621 622 kvm_put_guest_xcr0(vcpu); 623 vcpu->arch.xcr0 = xcr0; 624 625 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK) 626 kvm_update_cpuid(vcpu); 627 return 0; 628 } 629 630 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) 631 { 632 if (kvm_x86_ops->get_cpl(vcpu) != 0 || 633 __kvm_set_xcr(vcpu, index, xcr)) { 634 kvm_inject_gp(vcpu, 0); 635 return 1; 636 } 637 return 0; 638 } 639 EXPORT_SYMBOL_GPL(kvm_set_xcr); 640 641 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 642 { 643 unsigned long old_cr4 = kvm_read_cr4(vcpu); 644 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | 645 X86_CR4_PAE | X86_CR4_SMEP; 646 if (cr4 & CR4_RESERVED_BITS) 647 return 1; 648 649 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE)) 650 return 1; 651 652 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP)) 653 return 1; 654 655 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP)) 656 return 1; 657 658 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE)) 659 return 1; 660 661 if (is_long_mode(vcpu)) { 662 if (!(cr4 & X86_CR4_PAE)) 663 return 1; 664 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) 665 && ((cr4 ^ old_cr4) & pdptr_bits) 666 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, 667 kvm_read_cr3(vcpu))) 668 return 1; 669 670 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { 671 if (!guest_cpuid_has_pcid(vcpu)) 672 return 1; 673 674 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ 675 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) 676 return 1; 677 } 678 679 if (kvm_x86_ops->set_cr4(vcpu, cr4)) 680 return 1; 681 682 if (((cr4 ^ old_cr4) & pdptr_bits) || 683 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) 684 kvm_mmu_reset_context(vcpu); 685 686 if ((cr4 ^ old_cr4) & X86_CR4_SMAP) 687 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false); 688 689 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE) 690 kvm_update_cpuid(vcpu); 691 692 return 0; 693 } 694 EXPORT_SYMBOL_GPL(kvm_set_cr4); 695 696 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 697 { 698 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) { 699 kvm_mmu_sync_roots(vcpu); 700 kvm_mmu_flush_tlb(vcpu); 701 return 0; 702 } 703 704 if (is_long_mode(vcpu) && (cr3 & CR3_L_MODE_RESERVED_BITS)) 705 return 1; 706 if (is_pae(vcpu) && is_paging(vcpu) && 707 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) 708 return 1; 709 710 vcpu->arch.cr3 = cr3; 711 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 712 kvm_mmu_new_cr3(vcpu); 713 return 0; 714 } 715 EXPORT_SYMBOL_GPL(kvm_set_cr3); 716 717 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) 718 { 719 if (cr8 & CR8_RESERVED_BITS) 720 return 1; 721 if (irqchip_in_kernel(vcpu->kvm)) 722 kvm_lapic_set_tpr(vcpu, cr8); 723 else 724 vcpu->arch.cr8 = cr8; 725 return 0; 726 } 727 EXPORT_SYMBOL_GPL(kvm_set_cr8); 728 729 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) 730 { 731 if (irqchip_in_kernel(vcpu->kvm)) 732 return kvm_lapic_get_cr8(vcpu); 733 else 734 return vcpu->arch.cr8; 735 } 736 EXPORT_SYMBOL_GPL(kvm_get_cr8); 737 738 static void kvm_update_dr6(struct kvm_vcpu *vcpu) 739 { 740 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 741 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6); 742 } 743 744 static void kvm_update_dr7(struct kvm_vcpu *vcpu) 745 { 746 unsigned long dr7; 747 748 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 749 dr7 = vcpu->arch.guest_debug_dr7; 750 else 751 dr7 = vcpu->arch.dr7; 752 kvm_x86_ops->set_dr7(vcpu, dr7); 753 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; 754 if (dr7 & DR7_BP_EN_MASK) 755 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; 756 } 757 758 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 759 { 760 switch (dr) { 761 case 0 ... 3: 762 vcpu->arch.db[dr] = val; 763 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) 764 vcpu->arch.eff_db[dr] = val; 765 break; 766 case 4: 767 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 768 return 1; /* #UD */ 769 /* fall through */ 770 case 6: 771 if (val & 0xffffffff00000000ULL) 772 return -1; /* #GP */ 773 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1; 774 kvm_update_dr6(vcpu); 775 break; 776 case 5: 777 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 778 return 1; /* #UD */ 779 /* fall through */ 780 default: /* 7 */ 781 if (val & 0xffffffff00000000ULL) 782 return -1; /* #GP */ 783 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; 784 kvm_update_dr7(vcpu); 785 break; 786 } 787 788 return 0; 789 } 790 791 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) 792 { 793 int res; 794 795 res = __kvm_set_dr(vcpu, dr, val); 796 if (res > 0) 797 kvm_queue_exception(vcpu, UD_VECTOR); 798 else if (res < 0) 799 kvm_inject_gp(vcpu, 0); 800 801 return res; 802 } 803 EXPORT_SYMBOL_GPL(kvm_set_dr); 804 805 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 806 { 807 switch (dr) { 808 case 0 ... 3: 809 *val = vcpu->arch.db[dr]; 810 break; 811 case 4: 812 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 813 return 1; 814 /* fall through */ 815 case 6: 816 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) 817 *val = vcpu->arch.dr6; 818 else 819 *val = kvm_x86_ops->get_dr6(vcpu); 820 break; 821 case 5: 822 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) 823 return 1; 824 /* fall through */ 825 default: /* 7 */ 826 *val = vcpu->arch.dr7; 827 break; 828 } 829 830 return 0; 831 } 832 833 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) 834 { 835 if (_kvm_get_dr(vcpu, dr, val)) { 836 kvm_queue_exception(vcpu, UD_VECTOR); 837 return 1; 838 } 839 return 0; 840 } 841 EXPORT_SYMBOL_GPL(kvm_get_dr); 842 843 bool kvm_rdpmc(struct kvm_vcpu *vcpu) 844 { 845 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); 846 u64 data; 847 int err; 848 849 err = kvm_pmu_read_pmc(vcpu, ecx, &data); 850 if (err) 851 return err; 852 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data); 853 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32); 854 return err; 855 } 856 EXPORT_SYMBOL_GPL(kvm_rdpmc); 857 858 /* 859 * List of msr numbers which we expose to userspace through KVM_GET_MSRS 860 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. 861 * 862 * This list is modified at module load time to reflect the 863 * capabilities of the host cpu. This capabilities test skips MSRs that are 864 * kvm-specific. Those are put in the beginning of the list. 865 */ 866 867 #define KVM_SAVE_MSRS_BEGIN 12 868 static u32 msrs_to_save[] = { 869 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, 870 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, 871 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, 872 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, 873 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, 874 MSR_KVM_PV_EOI_EN, 875 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 876 MSR_STAR, 877 #ifdef CONFIG_X86_64 878 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, 879 #endif 880 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, 881 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS 882 }; 883 884 static unsigned num_msrs_to_save; 885 886 static const u32 emulated_msrs[] = { 887 MSR_IA32_TSC_ADJUST, 888 MSR_IA32_TSCDEADLINE, 889 MSR_IA32_MISC_ENABLE, 890 MSR_IA32_MCG_STATUS, 891 MSR_IA32_MCG_CTL, 892 }; 893 894 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) 895 { 896 if (efer & efer_reserved_bits) 897 return false; 898 899 if (efer & EFER_FFXSR) { 900 struct kvm_cpuid_entry2 *feat; 901 902 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 903 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) 904 return false; 905 } 906 907 if (efer & EFER_SVME) { 908 struct kvm_cpuid_entry2 *feat; 909 910 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); 911 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) 912 return false; 913 } 914 915 return true; 916 } 917 EXPORT_SYMBOL_GPL(kvm_valid_efer); 918 919 static int set_efer(struct kvm_vcpu *vcpu, u64 efer) 920 { 921 u64 old_efer = vcpu->arch.efer; 922 923 if (!kvm_valid_efer(vcpu, efer)) 924 return 1; 925 926 if (is_paging(vcpu) 927 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) 928 return 1; 929 930 efer &= ~EFER_LMA; 931 efer |= vcpu->arch.efer & EFER_LMA; 932 933 kvm_x86_ops->set_efer(vcpu, efer); 934 935 /* Update reserved bits */ 936 if ((efer ^ old_efer) & EFER_NX) 937 kvm_mmu_reset_context(vcpu); 938 939 return 0; 940 } 941 942 void kvm_enable_efer_bits(u64 mask) 943 { 944 efer_reserved_bits &= ~mask; 945 } 946 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 947 948 949 /* 950 * Writes msr value into into the appropriate "register". 951 * Returns 0 on success, non-0 otherwise. 952 * Assumes vcpu_load() was already called. 953 */ 954 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 955 { 956 return kvm_x86_ops->set_msr(vcpu, msr); 957 } 958 959 /* 960 * Adapt set_msr() to msr_io()'s calling convention 961 */ 962 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) 963 { 964 struct msr_data msr; 965 966 msr.data = *data; 967 msr.index = index; 968 msr.host_initiated = true; 969 return kvm_set_msr(vcpu, &msr); 970 } 971 972 #ifdef CONFIG_X86_64 973 struct pvclock_gtod_data { 974 seqcount_t seq; 975 976 struct { /* extract of a clocksource struct */ 977 int vclock_mode; 978 cycle_t cycle_last; 979 cycle_t mask; 980 u32 mult; 981 u32 shift; 982 } clock; 983 984 /* open coded 'struct timespec' */ 985 u64 monotonic_time_snsec; 986 time_t monotonic_time_sec; 987 }; 988 989 static struct pvclock_gtod_data pvclock_gtod_data; 990 991 static void update_pvclock_gtod(struct timekeeper *tk) 992 { 993 struct pvclock_gtod_data *vdata = &pvclock_gtod_data; 994 995 write_seqcount_begin(&vdata->seq); 996 997 /* copy pvclock gtod data */ 998 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode; 999 vdata->clock.cycle_last = tk->clock->cycle_last; 1000 vdata->clock.mask = tk->clock->mask; 1001 vdata->clock.mult = tk->mult; 1002 vdata->clock.shift = tk->shift; 1003 1004 vdata->monotonic_time_sec = tk->xtime_sec 1005 + tk->wall_to_monotonic.tv_sec; 1006 vdata->monotonic_time_snsec = tk->xtime_nsec 1007 + (tk->wall_to_monotonic.tv_nsec 1008 << tk->shift); 1009 while (vdata->monotonic_time_snsec >= 1010 (((u64)NSEC_PER_SEC) << tk->shift)) { 1011 vdata->monotonic_time_snsec -= 1012 ((u64)NSEC_PER_SEC) << tk->shift; 1013 vdata->monotonic_time_sec++; 1014 } 1015 1016 write_seqcount_end(&vdata->seq); 1017 } 1018 #endif 1019 1020 1021 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) 1022 { 1023 int version; 1024 int r; 1025 struct pvclock_wall_clock wc; 1026 struct timespec boot; 1027 1028 if (!wall_clock) 1029 return; 1030 1031 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); 1032 if (r) 1033 return; 1034 1035 if (version & 1) 1036 ++version; /* first time write, random junk */ 1037 1038 ++version; 1039 1040 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1041 1042 /* 1043 * The guest calculates current wall clock time by adding 1044 * system time (updated by kvm_guest_time_update below) to the 1045 * wall clock specified here. guest system time equals host 1046 * system time for us, thus we must fill in host boot time here. 1047 */ 1048 getboottime(&boot); 1049 1050 if (kvm->arch.kvmclock_offset) { 1051 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset); 1052 boot = timespec_sub(boot, ts); 1053 } 1054 wc.sec = boot.tv_sec; 1055 wc.nsec = boot.tv_nsec; 1056 wc.version = version; 1057 1058 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); 1059 1060 version++; 1061 kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); 1062 } 1063 1064 static uint32_t div_frac(uint32_t dividend, uint32_t divisor) 1065 { 1066 uint32_t quotient, remainder; 1067 1068 /* Don't try to replace with do_div(), this one calculates 1069 * "(dividend << 32) / divisor" */ 1070 __asm__ ( "divl %4" 1071 : "=a" (quotient), "=d" (remainder) 1072 : "0" (0), "1" (dividend), "r" (divisor) ); 1073 return quotient; 1074 } 1075 1076 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz, 1077 s8 *pshift, u32 *pmultiplier) 1078 { 1079 uint64_t scaled64; 1080 int32_t shift = 0; 1081 uint64_t tps64; 1082 uint32_t tps32; 1083 1084 tps64 = base_khz * 1000LL; 1085 scaled64 = scaled_khz * 1000LL; 1086 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { 1087 tps64 >>= 1; 1088 shift--; 1089 } 1090 1091 tps32 = (uint32_t)tps64; 1092 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { 1093 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) 1094 scaled64 >>= 1; 1095 else 1096 tps32 <<= 1; 1097 shift++; 1098 } 1099 1100 *pshift = shift; 1101 *pmultiplier = div_frac(scaled64, tps32); 1102 1103 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n", 1104 __func__, base_khz, scaled_khz, shift, *pmultiplier); 1105 } 1106 1107 static inline u64 get_kernel_ns(void) 1108 { 1109 struct timespec ts; 1110 1111 ktime_get_ts(&ts); 1112 monotonic_to_bootbased(&ts); 1113 return timespec_to_ns(&ts); 1114 } 1115 1116 #ifdef CONFIG_X86_64 1117 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); 1118 #endif 1119 1120 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); 1121 unsigned long max_tsc_khz; 1122 1123 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 1124 { 1125 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 1126 vcpu->arch.virtual_tsc_shift); 1127 } 1128 1129 static u32 adjust_tsc_khz(u32 khz, s32 ppm) 1130 { 1131 u64 v = (u64)khz * (1000000 + ppm); 1132 do_div(v, 1000000); 1133 return v; 1134 } 1135 1136 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz) 1137 { 1138 u32 thresh_lo, thresh_hi; 1139 int use_scaling = 0; 1140 1141 /* tsc_khz can be zero if TSC calibration fails */ 1142 if (this_tsc_khz == 0) 1143 return; 1144 1145 /* Compute a scale to convert nanoseconds in TSC cycles */ 1146 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000, 1147 &vcpu->arch.virtual_tsc_shift, 1148 &vcpu->arch.virtual_tsc_mult); 1149 vcpu->arch.virtual_tsc_khz = this_tsc_khz; 1150 1151 /* 1152 * Compute the variation in TSC rate which is acceptable 1153 * within the range of tolerance and decide if the 1154 * rate being applied is within that bounds of the hardware 1155 * rate. If so, no scaling or compensation need be done. 1156 */ 1157 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); 1158 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); 1159 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) { 1160 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi); 1161 use_scaling = 1; 1162 } 1163 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling); 1164 } 1165 1166 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) 1167 { 1168 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, 1169 vcpu->arch.virtual_tsc_mult, 1170 vcpu->arch.virtual_tsc_shift); 1171 tsc += vcpu->arch.this_tsc_write; 1172 return tsc; 1173 } 1174 1175 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) 1176 { 1177 #ifdef CONFIG_X86_64 1178 bool vcpus_matched; 1179 bool do_request = false; 1180 struct kvm_arch *ka = &vcpu->kvm->arch; 1181 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1182 1183 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1184 atomic_read(&vcpu->kvm->online_vcpus)); 1185 1186 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC) 1187 if (!ka->use_master_clock) 1188 do_request = 1; 1189 1190 if (!vcpus_matched && ka->use_master_clock) 1191 do_request = 1; 1192 1193 if (do_request) 1194 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); 1195 1196 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, 1197 atomic_read(&vcpu->kvm->online_vcpus), 1198 ka->use_master_clock, gtod->clock.vclock_mode); 1199 #endif 1200 } 1201 1202 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset) 1203 { 1204 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu); 1205 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset; 1206 } 1207 1208 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr) 1209 { 1210 struct kvm *kvm = vcpu->kvm; 1211 u64 offset, ns, elapsed; 1212 unsigned long flags; 1213 s64 usdiff; 1214 bool matched; 1215 u64 data = msr->data; 1216 1217 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); 1218 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); 1219 ns = get_kernel_ns(); 1220 elapsed = ns - kvm->arch.last_tsc_nsec; 1221 1222 if (vcpu->arch.virtual_tsc_khz) { 1223 int faulted = 0; 1224 1225 /* n.b - signed multiplication and division required */ 1226 usdiff = data - kvm->arch.last_tsc_write; 1227 #ifdef CONFIG_X86_64 1228 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz; 1229 #else 1230 /* do_div() only does unsigned */ 1231 asm("1: idivl %[divisor]\n" 1232 "2: xor %%edx, %%edx\n" 1233 " movl $0, %[faulted]\n" 1234 "3:\n" 1235 ".section .fixup,\"ax\"\n" 1236 "4: movl $1, %[faulted]\n" 1237 " jmp 3b\n" 1238 ".previous\n" 1239 1240 _ASM_EXTABLE(1b, 4b) 1241 1242 : "=A"(usdiff), [faulted] "=r" (faulted) 1243 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz)); 1244 1245 #endif 1246 do_div(elapsed, 1000); 1247 usdiff -= elapsed; 1248 if (usdiff < 0) 1249 usdiff = -usdiff; 1250 1251 /* idivl overflow => difference is larger than USEC_PER_SEC */ 1252 if (faulted) 1253 usdiff = USEC_PER_SEC; 1254 } else 1255 usdiff = USEC_PER_SEC; /* disable TSC match window below */ 1256 1257 /* 1258 * Special case: TSC write with a small delta (1 second) of virtual 1259 * cycle time against real time is interpreted as an attempt to 1260 * synchronize the CPU. 1261 * 1262 * For a reliable TSC, we can match TSC offsets, and for an unstable 1263 * TSC, we add elapsed time in this computation. We could let the 1264 * compensation code attempt to catch up if we fall behind, but 1265 * it's better to try to match offsets from the beginning. 1266 */ 1267 if (usdiff < USEC_PER_SEC && 1268 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { 1269 if (!check_tsc_unstable()) { 1270 offset = kvm->arch.cur_tsc_offset; 1271 pr_debug("kvm: matched tsc offset for %llu\n", data); 1272 } else { 1273 u64 delta = nsec_to_cycles(vcpu, elapsed); 1274 data += delta; 1275 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data); 1276 pr_debug("kvm: adjusted tsc offset by %llu\n", delta); 1277 } 1278 matched = true; 1279 } else { 1280 /* 1281 * We split periods of matched TSC writes into generations. 1282 * For each generation, we track the original measured 1283 * nanosecond time, offset, and write, so if TSCs are in 1284 * sync, we can match exact offset, and if not, we can match 1285 * exact software computation in compute_guest_tsc() 1286 * 1287 * These values are tracked in kvm->arch.cur_xxx variables. 1288 */ 1289 kvm->arch.cur_tsc_generation++; 1290 kvm->arch.cur_tsc_nsec = ns; 1291 kvm->arch.cur_tsc_write = data; 1292 kvm->arch.cur_tsc_offset = offset; 1293 matched = false; 1294 pr_debug("kvm: new tsc generation %u, clock %llu\n", 1295 kvm->arch.cur_tsc_generation, data); 1296 } 1297 1298 /* 1299 * We also track th most recent recorded KHZ, write and time to 1300 * allow the matching interval to be extended at each write. 1301 */ 1302 kvm->arch.last_tsc_nsec = ns; 1303 kvm->arch.last_tsc_write = data; 1304 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; 1305 1306 vcpu->arch.last_guest_tsc = data; 1307 1308 /* Keep track of which generation this VCPU has synchronized to */ 1309 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; 1310 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; 1311 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; 1312 1313 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated) 1314 update_ia32_tsc_adjust_msr(vcpu, offset); 1315 kvm_x86_ops->write_tsc_offset(vcpu, offset); 1316 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); 1317 1318 spin_lock(&kvm->arch.pvclock_gtod_sync_lock); 1319 if (matched) 1320 kvm->arch.nr_vcpus_matched_tsc++; 1321 else 1322 kvm->arch.nr_vcpus_matched_tsc = 0; 1323 1324 kvm_track_tsc_matching(vcpu); 1325 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock); 1326 } 1327 1328 EXPORT_SYMBOL_GPL(kvm_write_tsc); 1329 1330 #ifdef CONFIG_X86_64 1331 1332 static cycle_t read_tsc(void) 1333 { 1334 cycle_t ret; 1335 u64 last; 1336 1337 /* 1338 * Empirically, a fence (of type that depends on the CPU) 1339 * before rdtsc is enough to ensure that rdtsc is ordered 1340 * with respect to loads. The various CPU manuals are unclear 1341 * as to whether rdtsc can be reordered with later loads, 1342 * but no one has ever seen it happen. 1343 */ 1344 rdtsc_barrier(); 1345 ret = (cycle_t)vget_cycles(); 1346 1347 last = pvclock_gtod_data.clock.cycle_last; 1348 1349 if (likely(ret >= last)) 1350 return ret; 1351 1352 /* 1353 * GCC likes to generate cmov here, but this branch is extremely 1354 * predictable (it's just a funciton of time and the likely is 1355 * very likely) and there's a data dependence, so force GCC 1356 * to generate a branch instead. I don't barrier() because 1357 * we don't actually need a barrier, and if this function 1358 * ever gets inlined it will generate worse code. 1359 */ 1360 asm volatile (""); 1361 return last; 1362 } 1363 1364 static inline u64 vgettsc(cycle_t *cycle_now) 1365 { 1366 long v; 1367 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1368 1369 *cycle_now = read_tsc(); 1370 1371 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask; 1372 return v * gtod->clock.mult; 1373 } 1374 1375 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now) 1376 { 1377 unsigned long seq; 1378 u64 ns; 1379 int mode; 1380 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 1381 1382 ts->tv_nsec = 0; 1383 do { 1384 seq = read_seqcount_begin(>od->seq); 1385 mode = gtod->clock.vclock_mode; 1386 ts->tv_sec = gtod->monotonic_time_sec; 1387 ns = gtod->monotonic_time_snsec; 1388 ns += vgettsc(cycle_now); 1389 ns >>= gtod->clock.shift; 1390 } while (unlikely(read_seqcount_retry(>od->seq, seq))); 1391 timespec_add_ns(ts, ns); 1392 1393 return mode; 1394 } 1395 1396 /* returns true if host is using tsc clocksource */ 1397 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now) 1398 { 1399 struct timespec ts; 1400 1401 /* checked again under seqlock below */ 1402 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC) 1403 return false; 1404 1405 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC) 1406 return false; 1407 1408 monotonic_to_bootbased(&ts); 1409 *kernel_ns = timespec_to_ns(&ts); 1410 1411 return true; 1412 } 1413 #endif 1414 1415 /* 1416 * 1417 * Assuming a stable TSC across physical CPUS, and a stable TSC 1418 * across virtual CPUs, the following condition is possible. 1419 * Each numbered line represents an event visible to both 1420 * CPUs at the next numbered event. 1421 * 1422 * "timespecX" represents host monotonic time. "tscX" represents 1423 * RDTSC value. 1424 * 1425 * VCPU0 on CPU0 | VCPU1 on CPU1 1426 * 1427 * 1. read timespec0,tsc0 1428 * 2. | timespec1 = timespec0 + N 1429 * | tsc1 = tsc0 + M 1430 * 3. transition to guest | transition to guest 1431 * 4. ret0 = timespec0 + (rdtsc - tsc0) | 1432 * 5. | ret1 = timespec1 + (rdtsc - tsc1) 1433 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) 1434 * 1435 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: 1436 * 1437 * - ret0 < ret1 1438 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) 1439 * ... 1440 * - 0 < N - M => M < N 1441 * 1442 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not 1443 * always the case (the difference between two distinct xtime instances 1444 * might be smaller then the difference between corresponding TSC reads, 1445 * when updating guest vcpus pvclock areas). 1446 * 1447 * To avoid that problem, do not allow visibility of distinct 1448 * system_timestamp/tsc_timestamp values simultaneously: use a master 1449 * copy of host monotonic time values. Update that master copy 1450 * in lockstep. 1451 * 1452 * Rely on synchronization of host TSCs and guest TSCs for monotonicity. 1453 * 1454 */ 1455 1456 static void pvclock_update_vm_gtod_copy(struct kvm *kvm) 1457 { 1458 #ifdef CONFIG_X86_64 1459 struct kvm_arch *ka = &kvm->arch; 1460 int vclock_mode; 1461 bool host_tsc_clocksource, vcpus_matched; 1462 1463 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == 1464 atomic_read(&kvm->online_vcpus)); 1465 1466 /* 1467 * If the host uses TSC clock, then passthrough TSC as stable 1468 * to the guest. 1469 */ 1470 host_tsc_clocksource = kvm_get_time_and_clockread( 1471 &ka->master_kernel_ns, 1472 &ka->master_cycle_now); 1473 1474 ka->use_master_clock = host_tsc_clocksource & vcpus_matched; 1475 1476 if (ka->use_master_clock) 1477 atomic_set(&kvm_guest_has_master_clock, 1); 1478 1479 vclock_mode = pvclock_gtod_data.clock.vclock_mode; 1480 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, 1481 vcpus_matched); 1482 #endif 1483 } 1484 1485 static void kvm_gen_update_masterclock(struct kvm *kvm) 1486 { 1487 #ifdef CONFIG_X86_64 1488 int i; 1489 struct kvm_vcpu *vcpu; 1490 struct kvm_arch *ka = &kvm->arch; 1491 1492 spin_lock(&ka->pvclock_gtod_sync_lock); 1493 kvm_make_mclock_inprogress_request(kvm); 1494 /* no guest entries from this point */ 1495 pvclock_update_vm_gtod_copy(kvm); 1496 1497 kvm_for_each_vcpu(i, vcpu, kvm) 1498 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); 1499 1500 /* guest entries allowed */ 1501 kvm_for_each_vcpu(i, vcpu, kvm) 1502 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests); 1503 1504 spin_unlock(&ka->pvclock_gtod_sync_lock); 1505 #endif 1506 } 1507 1508 static int kvm_guest_time_update(struct kvm_vcpu *v) 1509 { 1510 unsigned long flags, this_tsc_khz; 1511 struct kvm_vcpu_arch *vcpu = &v->arch; 1512 struct kvm_arch *ka = &v->kvm->arch; 1513 s64 kernel_ns; 1514 u64 tsc_timestamp, host_tsc; 1515 struct pvclock_vcpu_time_info guest_hv_clock; 1516 u8 pvclock_flags; 1517 bool use_master_clock; 1518 1519 kernel_ns = 0; 1520 host_tsc = 0; 1521 1522 /* 1523 * If the host uses TSC clock, then passthrough TSC as stable 1524 * to the guest. 1525 */ 1526 spin_lock(&ka->pvclock_gtod_sync_lock); 1527 use_master_clock = ka->use_master_clock; 1528 if (use_master_clock) { 1529 host_tsc = ka->master_cycle_now; 1530 kernel_ns = ka->master_kernel_ns; 1531 } 1532 spin_unlock(&ka->pvclock_gtod_sync_lock); 1533 1534 /* Keep irq disabled to prevent changes to the clock */ 1535 local_irq_save(flags); 1536 this_tsc_khz = __get_cpu_var(cpu_tsc_khz); 1537 if (unlikely(this_tsc_khz == 0)) { 1538 local_irq_restore(flags); 1539 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); 1540 return 1; 1541 } 1542 if (!use_master_clock) { 1543 host_tsc = native_read_tsc(); 1544 kernel_ns = get_kernel_ns(); 1545 } 1546 1547 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc); 1548 1549 /* 1550 * We may have to catch up the TSC to match elapsed wall clock 1551 * time for two reasons, even if kvmclock is used. 1552 * 1) CPU could have been running below the maximum TSC rate 1553 * 2) Broken TSC compensation resets the base at each VCPU 1554 * entry to avoid unknown leaps of TSC even when running 1555 * again on the same CPU. This may cause apparent elapsed 1556 * time to disappear, and the guest to stand still or run 1557 * very slowly. 1558 */ 1559 if (vcpu->tsc_catchup) { 1560 u64 tsc = compute_guest_tsc(v, kernel_ns); 1561 if (tsc > tsc_timestamp) { 1562 adjust_tsc_offset_guest(v, tsc - tsc_timestamp); 1563 tsc_timestamp = tsc; 1564 } 1565 } 1566 1567 local_irq_restore(flags); 1568 1569 if (!vcpu->pv_time_enabled) 1570 return 0; 1571 1572 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) { 1573 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz, 1574 &vcpu->hv_clock.tsc_shift, 1575 &vcpu->hv_clock.tsc_to_system_mul); 1576 vcpu->hw_tsc_khz = this_tsc_khz; 1577 } 1578 1579 /* With all the info we got, fill in the values */ 1580 vcpu->hv_clock.tsc_timestamp = tsc_timestamp; 1581 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; 1582 vcpu->last_guest_tsc = tsc_timestamp; 1583 1584 /* 1585 * The interface expects us to write an even number signaling that the 1586 * update is finished. Since the guest won't see the intermediate 1587 * state, we just increase by 2 at the end. 1588 */ 1589 vcpu->hv_clock.version += 2; 1590 1591 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time, 1592 &guest_hv_clock, sizeof(guest_hv_clock)))) 1593 return 0; 1594 1595 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ 1596 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED); 1597 1598 if (vcpu->pvclock_set_guest_stopped_request) { 1599 pvclock_flags |= PVCLOCK_GUEST_STOPPED; 1600 vcpu->pvclock_set_guest_stopped_request = false; 1601 } 1602 1603 /* If the host uses TSC clocksource, then it is stable */ 1604 if (use_master_clock) 1605 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; 1606 1607 vcpu->hv_clock.flags = pvclock_flags; 1608 1609 kvm_write_guest_cached(v->kvm, &vcpu->pv_time, 1610 &vcpu->hv_clock, 1611 sizeof(vcpu->hv_clock)); 1612 return 0; 1613 } 1614 1615 /* 1616 * kvmclock updates which are isolated to a given vcpu, such as 1617 * vcpu->cpu migration, should not allow system_timestamp from 1618 * the rest of the vcpus to remain static. Otherwise ntp frequency 1619 * correction applies to one vcpu's system_timestamp but not 1620 * the others. 1621 * 1622 * So in those cases, request a kvmclock update for all vcpus. 1623 * We need to rate-limit these requests though, as they can 1624 * considerably slow guests that have a large number of vcpus. 1625 * The time for a remote vcpu to update its kvmclock is bound 1626 * by the delay we use to rate-limit the updates. 1627 */ 1628 1629 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) 1630 1631 static void kvmclock_update_fn(struct work_struct *work) 1632 { 1633 int i; 1634 struct delayed_work *dwork = to_delayed_work(work); 1635 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1636 kvmclock_update_work); 1637 struct kvm *kvm = container_of(ka, struct kvm, arch); 1638 struct kvm_vcpu *vcpu; 1639 1640 kvm_for_each_vcpu(i, vcpu, kvm) { 1641 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); 1642 kvm_vcpu_kick(vcpu); 1643 } 1644 } 1645 1646 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) 1647 { 1648 struct kvm *kvm = v->kvm; 1649 1650 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests); 1651 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 1652 KVMCLOCK_UPDATE_DELAY); 1653 } 1654 1655 #define KVMCLOCK_SYNC_PERIOD (300 * HZ) 1656 1657 static void kvmclock_sync_fn(struct work_struct *work) 1658 { 1659 struct delayed_work *dwork = to_delayed_work(work); 1660 struct kvm_arch *ka = container_of(dwork, struct kvm_arch, 1661 kvmclock_sync_work); 1662 struct kvm *kvm = container_of(ka, struct kvm, arch); 1663 1664 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); 1665 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 1666 KVMCLOCK_SYNC_PERIOD); 1667 } 1668 1669 static bool msr_mtrr_valid(unsigned msr) 1670 { 1671 switch (msr) { 1672 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: 1673 case MSR_MTRRfix64K_00000: 1674 case MSR_MTRRfix16K_80000: 1675 case MSR_MTRRfix16K_A0000: 1676 case MSR_MTRRfix4K_C0000: 1677 case MSR_MTRRfix4K_C8000: 1678 case MSR_MTRRfix4K_D0000: 1679 case MSR_MTRRfix4K_D8000: 1680 case MSR_MTRRfix4K_E0000: 1681 case MSR_MTRRfix4K_E8000: 1682 case MSR_MTRRfix4K_F0000: 1683 case MSR_MTRRfix4K_F8000: 1684 case MSR_MTRRdefType: 1685 case MSR_IA32_CR_PAT: 1686 return true; 1687 case 0x2f8: 1688 return true; 1689 } 1690 return false; 1691 } 1692 1693 static bool valid_pat_type(unsigned t) 1694 { 1695 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ 1696 } 1697 1698 static bool valid_mtrr_type(unsigned t) 1699 { 1700 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ 1701 } 1702 1703 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1704 { 1705 int i; 1706 1707 if (!msr_mtrr_valid(msr)) 1708 return false; 1709 1710 if (msr == MSR_IA32_CR_PAT) { 1711 for (i = 0; i < 8; i++) 1712 if (!valid_pat_type((data >> (i * 8)) & 0xff)) 1713 return false; 1714 return true; 1715 } else if (msr == MSR_MTRRdefType) { 1716 if (data & ~0xcff) 1717 return false; 1718 return valid_mtrr_type(data & 0xff); 1719 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { 1720 for (i = 0; i < 8 ; i++) 1721 if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) 1722 return false; 1723 return true; 1724 } 1725 1726 /* variable MTRRs */ 1727 return valid_mtrr_type(data & 0xff); 1728 } 1729 1730 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1731 { 1732 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; 1733 1734 if (!mtrr_valid(vcpu, msr, data)) 1735 return 1; 1736 1737 if (msr == MSR_MTRRdefType) { 1738 vcpu->arch.mtrr_state.def_type = data; 1739 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; 1740 } else if (msr == MSR_MTRRfix64K_00000) 1741 p[0] = data; 1742 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) 1743 p[1 + msr - MSR_MTRRfix16K_80000] = data; 1744 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) 1745 p[3 + msr - MSR_MTRRfix4K_C0000] = data; 1746 else if (msr == MSR_IA32_CR_PAT) 1747 vcpu->arch.pat = data; 1748 else { /* Variable MTRRs */ 1749 int idx, is_mtrr_mask; 1750 u64 *pt; 1751 1752 idx = (msr - 0x200) / 2; 1753 is_mtrr_mask = msr - 0x200 - 2 * idx; 1754 if (!is_mtrr_mask) 1755 pt = 1756 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; 1757 else 1758 pt = 1759 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; 1760 *pt = data; 1761 } 1762 1763 kvm_mmu_reset_context(vcpu); 1764 return 0; 1765 } 1766 1767 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1768 { 1769 u64 mcg_cap = vcpu->arch.mcg_cap; 1770 unsigned bank_num = mcg_cap & 0xff; 1771 1772 switch (msr) { 1773 case MSR_IA32_MCG_STATUS: 1774 vcpu->arch.mcg_status = data; 1775 break; 1776 case MSR_IA32_MCG_CTL: 1777 if (!(mcg_cap & MCG_CTL_P)) 1778 return 1; 1779 if (data != 0 && data != ~(u64)0) 1780 return -1; 1781 vcpu->arch.mcg_ctl = data; 1782 break; 1783 default: 1784 if (msr >= MSR_IA32_MC0_CTL && 1785 msr < MSR_IA32_MC0_CTL + 4 * bank_num) { 1786 u32 offset = msr - MSR_IA32_MC0_CTL; 1787 /* only 0 or all 1s can be written to IA32_MCi_CTL 1788 * some Linux kernels though clear bit 10 in bank 4 to 1789 * workaround a BIOS/GART TBL issue on AMD K8s, ignore 1790 * this to avoid an uncatched #GP in the guest 1791 */ 1792 if ((offset & 0x3) == 0 && 1793 data != 0 && (data | (1 << 10)) != ~(u64)0) 1794 return -1; 1795 vcpu->arch.mce_banks[offset] = data; 1796 break; 1797 } 1798 return 1; 1799 } 1800 return 0; 1801 } 1802 1803 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) 1804 { 1805 struct kvm *kvm = vcpu->kvm; 1806 int lm = is_long_mode(vcpu); 1807 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 1808 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; 1809 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 1810 : kvm->arch.xen_hvm_config.blob_size_32; 1811 u32 page_num = data & ~PAGE_MASK; 1812 u64 page_addr = data & PAGE_MASK; 1813 u8 *page; 1814 int r; 1815 1816 r = -E2BIG; 1817 if (page_num >= blob_size) 1818 goto out; 1819 r = -ENOMEM; 1820 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE); 1821 if (IS_ERR(page)) { 1822 r = PTR_ERR(page); 1823 goto out; 1824 } 1825 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) 1826 goto out_free; 1827 r = 0; 1828 out_free: 1829 kfree(page); 1830 out: 1831 return r; 1832 } 1833 1834 static bool kvm_hv_hypercall_enabled(struct kvm *kvm) 1835 { 1836 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE; 1837 } 1838 1839 static bool kvm_hv_msr_partition_wide(u32 msr) 1840 { 1841 bool r = false; 1842 switch (msr) { 1843 case HV_X64_MSR_GUEST_OS_ID: 1844 case HV_X64_MSR_HYPERCALL: 1845 case HV_X64_MSR_REFERENCE_TSC: 1846 case HV_X64_MSR_TIME_REF_COUNT: 1847 r = true; 1848 break; 1849 } 1850 1851 return r; 1852 } 1853 1854 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1855 { 1856 struct kvm *kvm = vcpu->kvm; 1857 1858 switch (msr) { 1859 case HV_X64_MSR_GUEST_OS_ID: 1860 kvm->arch.hv_guest_os_id = data; 1861 /* setting guest os id to zero disables hypercall page */ 1862 if (!kvm->arch.hv_guest_os_id) 1863 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE; 1864 break; 1865 case HV_X64_MSR_HYPERCALL: { 1866 u64 gfn; 1867 unsigned long addr; 1868 u8 instructions[4]; 1869 1870 /* if guest os id is not set hypercall should remain disabled */ 1871 if (!kvm->arch.hv_guest_os_id) 1872 break; 1873 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) { 1874 kvm->arch.hv_hypercall = data; 1875 break; 1876 } 1877 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT; 1878 addr = gfn_to_hva(kvm, gfn); 1879 if (kvm_is_error_hva(addr)) 1880 return 1; 1881 kvm_x86_ops->patch_hypercall(vcpu, instructions); 1882 ((unsigned char *)instructions)[3] = 0xc3; /* ret */ 1883 if (__copy_to_user((void __user *)addr, instructions, 4)) 1884 return 1; 1885 kvm->arch.hv_hypercall = data; 1886 mark_page_dirty(kvm, gfn); 1887 break; 1888 } 1889 case HV_X64_MSR_REFERENCE_TSC: { 1890 u64 gfn; 1891 HV_REFERENCE_TSC_PAGE tsc_ref; 1892 memset(&tsc_ref, 0, sizeof(tsc_ref)); 1893 kvm->arch.hv_tsc_page = data; 1894 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE)) 1895 break; 1896 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT; 1897 if (kvm_write_guest(kvm, data, 1898 &tsc_ref, sizeof(tsc_ref))) 1899 return 1; 1900 mark_page_dirty(kvm, gfn); 1901 break; 1902 } 1903 default: 1904 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " 1905 "data 0x%llx\n", msr, data); 1906 return 1; 1907 } 1908 return 0; 1909 } 1910 1911 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1912 { 1913 switch (msr) { 1914 case HV_X64_MSR_APIC_ASSIST_PAGE: { 1915 u64 gfn; 1916 unsigned long addr; 1917 1918 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { 1919 vcpu->arch.hv_vapic = data; 1920 break; 1921 } 1922 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT; 1923 addr = gfn_to_hva(vcpu->kvm, gfn); 1924 if (kvm_is_error_hva(addr)) 1925 return 1; 1926 if (__clear_user((void __user *)addr, PAGE_SIZE)) 1927 return 1; 1928 vcpu->arch.hv_vapic = data; 1929 mark_page_dirty(vcpu->kvm, gfn); 1930 break; 1931 } 1932 case HV_X64_MSR_EOI: 1933 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data); 1934 case HV_X64_MSR_ICR: 1935 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data); 1936 case HV_X64_MSR_TPR: 1937 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data); 1938 default: 1939 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x " 1940 "data 0x%llx\n", msr, data); 1941 return 1; 1942 } 1943 1944 return 0; 1945 } 1946 1947 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) 1948 { 1949 gpa_t gpa = data & ~0x3f; 1950 1951 /* Bits 2:5 are reserved, Should be zero */ 1952 if (data & 0x3c) 1953 return 1; 1954 1955 vcpu->arch.apf.msr_val = data; 1956 1957 if (!(data & KVM_ASYNC_PF_ENABLED)) { 1958 kvm_clear_async_pf_completion_queue(vcpu); 1959 kvm_async_pf_hash_reset(vcpu); 1960 return 0; 1961 } 1962 1963 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, 1964 sizeof(u32))) 1965 return 1; 1966 1967 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); 1968 kvm_async_pf_wakeup_all(vcpu); 1969 return 0; 1970 } 1971 1972 static void kvmclock_reset(struct kvm_vcpu *vcpu) 1973 { 1974 vcpu->arch.pv_time_enabled = false; 1975 } 1976 1977 static void accumulate_steal_time(struct kvm_vcpu *vcpu) 1978 { 1979 u64 delta; 1980 1981 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 1982 return; 1983 1984 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal; 1985 vcpu->arch.st.last_steal = current->sched_info.run_delay; 1986 vcpu->arch.st.accum_steal = delta; 1987 } 1988 1989 static void record_steal_time(struct kvm_vcpu *vcpu) 1990 { 1991 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) 1992 return; 1993 1994 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 1995 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)))) 1996 return; 1997 1998 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal; 1999 vcpu->arch.st.steal.version += 2; 2000 vcpu->arch.st.accum_steal = 0; 2001 2002 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime, 2003 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time)); 2004 } 2005 2006 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 2007 { 2008 bool pr = false; 2009 u32 msr = msr_info->index; 2010 u64 data = msr_info->data; 2011 2012 switch (msr) { 2013 case MSR_AMD64_NB_CFG: 2014 case MSR_IA32_UCODE_REV: 2015 case MSR_IA32_UCODE_WRITE: 2016 case MSR_VM_HSAVE_PA: 2017 case MSR_AMD64_PATCH_LOADER: 2018 case MSR_AMD64_BU_CFG2: 2019 break; 2020 2021 case MSR_EFER: 2022 return set_efer(vcpu, data); 2023 case MSR_K7_HWCR: 2024 data &= ~(u64)0x40; /* ignore flush filter disable */ 2025 data &= ~(u64)0x100; /* ignore ignne emulation enable */ 2026 data &= ~(u64)0x8; /* ignore TLB cache disable */ 2027 if (data != 0) { 2028 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", 2029 data); 2030 return 1; 2031 } 2032 break; 2033 case MSR_FAM10H_MMIO_CONF_BASE: 2034 if (data != 0) { 2035 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " 2036 "0x%llx\n", data); 2037 return 1; 2038 } 2039 break; 2040 case MSR_IA32_DEBUGCTLMSR: 2041 if (!data) { 2042 /* We support the non-activated case already */ 2043 break; 2044 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { 2045 /* Values other than LBR and BTF are vendor-specific, 2046 thus reserved and should throw a #GP */ 2047 return 1; 2048 } 2049 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", 2050 __func__, data); 2051 break; 2052 case 0x200 ... 0x2ff: 2053 return set_msr_mtrr(vcpu, msr, data); 2054 case MSR_IA32_APICBASE: 2055 return kvm_set_apic_base(vcpu, msr_info); 2056 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2057 return kvm_x2apic_msr_write(vcpu, msr, data); 2058 case MSR_IA32_TSCDEADLINE: 2059 kvm_set_lapic_tscdeadline_msr(vcpu, data); 2060 break; 2061 case MSR_IA32_TSC_ADJUST: 2062 if (guest_cpuid_has_tsc_adjust(vcpu)) { 2063 if (!msr_info->host_initiated) { 2064 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; 2065 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true); 2066 } 2067 vcpu->arch.ia32_tsc_adjust_msr = data; 2068 } 2069 break; 2070 case MSR_IA32_MISC_ENABLE: 2071 vcpu->arch.ia32_misc_enable_msr = data; 2072 break; 2073 case MSR_KVM_WALL_CLOCK_NEW: 2074 case MSR_KVM_WALL_CLOCK: 2075 vcpu->kvm->arch.wall_clock = data; 2076 kvm_write_wall_clock(vcpu->kvm, data); 2077 break; 2078 case MSR_KVM_SYSTEM_TIME_NEW: 2079 case MSR_KVM_SYSTEM_TIME: { 2080 u64 gpa_offset; 2081 kvmclock_reset(vcpu); 2082 2083 vcpu->arch.time = data; 2084 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2085 2086 /* we verify if the enable bit is set... */ 2087 if (!(data & 1)) 2088 break; 2089 2090 gpa_offset = data & ~(PAGE_MASK | 1); 2091 2092 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 2093 &vcpu->arch.pv_time, data & ~1ULL, 2094 sizeof(struct pvclock_vcpu_time_info))) 2095 vcpu->arch.pv_time_enabled = false; 2096 else 2097 vcpu->arch.pv_time_enabled = true; 2098 2099 break; 2100 } 2101 case MSR_KVM_ASYNC_PF_EN: 2102 if (kvm_pv_enable_async_pf(vcpu, data)) 2103 return 1; 2104 break; 2105 case MSR_KVM_STEAL_TIME: 2106 2107 if (unlikely(!sched_info_on())) 2108 return 1; 2109 2110 if (data & KVM_STEAL_RESERVED_MASK) 2111 return 1; 2112 2113 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime, 2114 data & KVM_STEAL_VALID_BITS, 2115 sizeof(struct kvm_steal_time))) 2116 return 1; 2117 2118 vcpu->arch.st.msr_val = data; 2119 2120 if (!(data & KVM_MSR_ENABLED)) 2121 break; 2122 2123 vcpu->arch.st.last_steal = current->sched_info.run_delay; 2124 2125 preempt_disable(); 2126 accumulate_steal_time(vcpu); 2127 preempt_enable(); 2128 2129 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2130 2131 break; 2132 case MSR_KVM_PV_EOI_EN: 2133 if (kvm_lapic_enable_pv_eoi(vcpu, data)) 2134 return 1; 2135 break; 2136 2137 case MSR_IA32_MCG_CTL: 2138 case MSR_IA32_MCG_STATUS: 2139 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: 2140 return set_msr_mce(vcpu, msr, data); 2141 2142 /* Performance counters are not protected by a CPUID bit, 2143 * so we should check all of them in the generic path for the sake of 2144 * cross vendor migration. 2145 * Writing a zero into the event select MSRs disables them, 2146 * which we perfectly emulate ;-). Any other value should be at least 2147 * reported, some guests depend on them. 2148 */ 2149 case MSR_K7_EVNTSEL0: 2150 case MSR_K7_EVNTSEL1: 2151 case MSR_K7_EVNTSEL2: 2152 case MSR_K7_EVNTSEL3: 2153 if (data != 0) 2154 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " 2155 "0x%x data 0x%llx\n", msr, data); 2156 break; 2157 /* at least RHEL 4 unconditionally writes to the perfctr registers, 2158 * so we ignore writes to make it happy. 2159 */ 2160 case MSR_K7_PERFCTR0: 2161 case MSR_K7_PERFCTR1: 2162 case MSR_K7_PERFCTR2: 2163 case MSR_K7_PERFCTR3: 2164 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: " 2165 "0x%x data 0x%llx\n", msr, data); 2166 break; 2167 case MSR_P6_PERFCTR0: 2168 case MSR_P6_PERFCTR1: 2169 pr = true; 2170 case MSR_P6_EVNTSEL0: 2171 case MSR_P6_EVNTSEL1: 2172 if (kvm_pmu_msr(vcpu, msr)) 2173 return kvm_pmu_set_msr(vcpu, msr_info); 2174 2175 if (pr || data != 0) 2176 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " 2177 "0x%x data 0x%llx\n", msr, data); 2178 break; 2179 case MSR_K7_CLK_CTL: 2180 /* 2181 * Ignore all writes to this no longer documented MSR. 2182 * Writes are only relevant for old K7 processors, 2183 * all pre-dating SVM, but a recommended workaround from 2184 * AMD for these chips. It is possible to specify the 2185 * affected processor models on the command line, hence 2186 * the need to ignore the workaround. 2187 */ 2188 break; 2189 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2190 if (kvm_hv_msr_partition_wide(msr)) { 2191 int r; 2192 mutex_lock(&vcpu->kvm->lock); 2193 r = set_msr_hyperv_pw(vcpu, msr, data); 2194 mutex_unlock(&vcpu->kvm->lock); 2195 return r; 2196 } else 2197 return set_msr_hyperv(vcpu, msr, data); 2198 break; 2199 case MSR_IA32_BBL_CR_CTL3: 2200 /* Drop writes to this legacy MSR -- see rdmsr 2201 * counterpart for further detail. 2202 */ 2203 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data); 2204 break; 2205 case MSR_AMD64_OSVW_ID_LENGTH: 2206 if (!guest_cpuid_has_osvw(vcpu)) 2207 return 1; 2208 vcpu->arch.osvw.length = data; 2209 break; 2210 case MSR_AMD64_OSVW_STATUS: 2211 if (!guest_cpuid_has_osvw(vcpu)) 2212 return 1; 2213 vcpu->arch.osvw.status = data; 2214 break; 2215 default: 2216 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) 2217 return xen_hvm_config(vcpu, data); 2218 if (kvm_pmu_msr(vcpu, msr)) 2219 return kvm_pmu_set_msr(vcpu, msr_info); 2220 if (!ignore_msrs) { 2221 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", 2222 msr, data); 2223 return 1; 2224 } else { 2225 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", 2226 msr, data); 2227 break; 2228 } 2229 } 2230 return 0; 2231 } 2232 EXPORT_SYMBOL_GPL(kvm_set_msr_common); 2233 2234 2235 /* 2236 * Reads an msr value (of 'msr_index') into 'pdata'. 2237 * Returns 0 on success, non-0 otherwise. 2238 * Assumes vcpu_load() was already called. 2239 */ 2240 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) 2241 { 2242 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); 2243 } 2244 2245 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2246 { 2247 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; 2248 2249 if (!msr_mtrr_valid(msr)) 2250 return 1; 2251 2252 if (msr == MSR_MTRRdefType) 2253 *pdata = vcpu->arch.mtrr_state.def_type + 2254 (vcpu->arch.mtrr_state.enabled << 10); 2255 else if (msr == MSR_MTRRfix64K_00000) 2256 *pdata = p[0]; 2257 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) 2258 *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; 2259 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) 2260 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; 2261 else if (msr == MSR_IA32_CR_PAT) 2262 *pdata = vcpu->arch.pat; 2263 else { /* Variable MTRRs */ 2264 int idx, is_mtrr_mask; 2265 u64 *pt; 2266 2267 idx = (msr - 0x200) / 2; 2268 is_mtrr_mask = msr - 0x200 - 2 * idx; 2269 if (!is_mtrr_mask) 2270 pt = 2271 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; 2272 else 2273 pt = 2274 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; 2275 *pdata = *pt; 2276 } 2277 2278 return 0; 2279 } 2280 2281 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2282 { 2283 u64 data; 2284 u64 mcg_cap = vcpu->arch.mcg_cap; 2285 unsigned bank_num = mcg_cap & 0xff; 2286 2287 switch (msr) { 2288 case MSR_IA32_P5_MC_ADDR: 2289 case MSR_IA32_P5_MC_TYPE: 2290 data = 0; 2291 break; 2292 case MSR_IA32_MCG_CAP: 2293 data = vcpu->arch.mcg_cap; 2294 break; 2295 case MSR_IA32_MCG_CTL: 2296 if (!(mcg_cap & MCG_CTL_P)) 2297 return 1; 2298 data = vcpu->arch.mcg_ctl; 2299 break; 2300 case MSR_IA32_MCG_STATUS: 2301 data = vcpu->arch.mcg_status; 2302 break; 2303 default: 2304 if (msr >= MSR_IA32_MC0_CTL && 2305 msr < MSR_IA32_MC0_CTL + 4 * bank_num) { 2306 u32 offset = msr - MSR_IA32_MC0_CTL; 2307 data = vcpu->arch.mce_banks[offset]; 2308 break; 2309 } 2310 return 1; 2311 } 2312 *pdata = data; 2313 return 0; 2314 } 2315 2316 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2317 { 2318 u64 data = 0; 2319 struct kvm *kvm = vcpu->kvm; 2320 2321 switch (msr) { 2322 case HV_X64_MSR_GUEST_OS_ID: 2323 data = kvm->arch.hv_guest_os_id; 2324 break; 2325 case HV_X64_MSR_HYPERCALL: 2326 data = kvm->arch.hv_hypercall; 2327 break; 2328 case HV_X64_MSR_TIME_REF_COUNT: { 2329 data = 2330 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100); 2331 break; 2332 } 2333 case HV_X64_MSR_REFERENCE_TSC: 2334 data = kvm->arch.hv_tsc_page; 2335 break; 2336 default: 2337 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); 2338 return 1; 2339 } 2340 2341 *pdata = data; 2342 return 0; 2343 } 2344 2345 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2346 { 2347 u64 data = 0; 2348 2349 switch (msr) { 2350 case HV_X64_MSR_VP_INDEX: { 2351 int r; 2352 struct kvm_vcpu *v; 2353 kvm_for_each_vcpu(r, v, vcpu->kvm) { 2354 if (v == vcpu) { 2355 data = r; 2356 break; 2357 } 2358 } 2359 break; 2360 } 2361 case HV_X64_MSR_EOI: 2362 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata); 2363 case HV_X64_MSR_ICR: 2364 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata); 2365 case HV_X64_MSR_TPR: 2366 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata); 2367 case HV_X64_MSR_APIC_ASSIST_PAGE: 2368 data = vcpu->arch.hv_vapic; 2369 break; 2370 default: 2371 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr); 2372 return 1; 2373 } 2374 *pdata = data; 2375 return 0; 2376 } 2377 2378 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) 2379 { 2380 u64 data; 2381 2382 switch (msr) { 2383 case MSR_IA32_PLATFORM_ID: 2384 case MSR_IA32_EBL_CR_POWERON: 2385 case MSR_IA32_DEBUGCTLMSR: 2386 case MSR_IA32_LASTBRANCHFROMIP: 2387 case MSR_IA32_LASTBRANCHTOIP: 2388 case MSR_IA32_LASTINTFROMIP: 2389 case MSR_IA32_LASTINTTOIP: 2390 case MSR_K8_SYSCFG: 2391 case MSR_K7_HWCR: 2392 case MSR_VM_HSAVE_PA: 2393 case MSR_K7_EVNTSEL0: 2394 case MSR_K7_PERFCTR0: 2395 case MSR_K8_INT_PENDING_MSG: 2396 case MSR_AMD64_NB_CFG: 2397 case MSR_FAM10H_MMIO_CONF_BASE: 2398 case MSR_AMD64_BU_CFG2: 2399 data = 0; 2400 break; 2401 case MSR_P6_PERFCTR0: 2402 case MSR_P6_PERFCTR1: 2403 case MSR_P6_EVNTSEL0: 2404 case MSR_P6_EVNTSEL1: 2405 if (kvm_pmu_msr(vcpu, msr)) 2406 return kvm_pmu_get_msr(vcpu, msr, pdata); 2407 data = 0; 2408 break; 2409 case MSR_IA32_UCODE_REV: 2410 data = 0x100000000ULL; 2411 break; 2412 case MSR_MTRRcap: 2413 data = 0x500 | KVM_NR_VAR_MTRR; 2414 break; 2415 case 0x200 ... 0x2ff: 2416 return get_msr_mtrr(vcpu, msr, pdata); 2417 case 0xcd: /* fsb frequency */ 2418 data = 3; 2419 break; 2420 /* 2421 * MSR_EBC_FREQUENCY_ID 2422 * Conservative value valid for even the basic CPU models. 2423 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 2424 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 2425 * and 266MHz for model 3, or 4. Set Core Clock 2426 * Frequency to System Bus Frequency Ratio to 1 (bits 2427 * 31:24) even though these are only valid for CPU 2428 * models > 2, however guests may end up dividing or 2429 * multiplying by zero otherwise. 2430 */ 2431 case MSR_EBC_FREQUENCY_ID: 2432 data = 1 << 24; 2433 break; 2434 case MSR_IA32_APICBASE: 2435 data = kvm_get_apic_base(vcpu); 2436 break; 2437 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: 2438 return kvm_x2apic_msr_read(vcpu, msr, pdata); 2439 break; 2440 case MSR_IA32_TSCDEADLINE: 2441 data = kvm_get_lapic_tscdeadline_msr(vcpu); 2442 break; 2443 case MSR_IA32_TSC_ADJUST: 2444 data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 2445 break; 2446 case MSR_IA32_MISC_ENABLE: 2447 data = vcpu->arch.ia32_misc_enable_msr; 2448 break; 2449 case MSR_IA32_PERF_STATUS: 2450 /* TSC increment by tick */ 2451 data = 1000ULL; 2452 /* CPU multiplier */ 2453 data |= (((uint64_t)4ULL) << 40); 2454 break; 2455 case MSR_EFER: 2456 data = vcpu->arch.efer; 2457 break; 2458 case MSR_KVM_WALL_CLOCK: 2459 case MSR_KVM_WALL_CLOCK_NEW: 2460 data = vcpu->kvm->arch.wall_clock; 2461 break; 2462 case MSR_KVM_SYSTEM_TIME: 2463 case MSR_KVM_SYSTEM_TIME_NEW: 2464 data = vcpu->arch.time; 2465 break; 2466 case MSR_KVM_ASYNC_PF_EN: 2467 data = vcpu->arch.apf.msr_val; 2468 break; 2469 case MSR_KVM_STEAL_TIME: 2470 data = vcpu->arch.st.msr_val; 2471 break; 2472 case MSR_KVM_PV_EOI_EN: 2473 data = vcpu->arch.pv_eoi.msr_val; 2474 break; 2475 case MSR_IA32_P5_MC_ADDR: 2476 case MSR_IA32_P5_MC_TYPE: 2477 case MSR_IA32_MCG_CAP: 2478 case MSR_IA32_MCG_CTL: 2479 case MSR_IA32_MCG_STATUS: 2480 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: 2481 return get_msr_mce(vcpu, msr, pdata); 2482 case MSR_K7_CLK_CTL: 2483 /* 2484 * Provide expected ramp-up count for K7. All other 2485 * are set to zero, indicating minimum divisors for 2486 * every field. 2487 * 2488 * This prevents guest kernels on AMD host with CPU 2489 * type 6, model 8 and higher from exploding due to 2490 * the rdmsr failing. 2491 */ 2492 data = 0x20000000; 2493 break; 2494 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 2495 if (kvm_hv_msr_partition_wide(msr)) { 2496 int r; 2497 mutex_lock(&vcpu->kvm->lock); 2498 r = get_msr_hyperv_pw(vcpu, msr, pdata); 2499 mutex_unlock(&vcpu->kvm->lock); 2500 return r; 2501 } else 2502 return get_msr_hyperv(vcpu, msr, pdata); 2503 break; 2504 case MSR_IA32_BBL_CR_CTL3: 2505 /* This legacy MSR exists but isn't fully documented in current 2506 * silicon. It is however accessed by winxp in very narrow 2507 * scenarios where it sets bit #19, itself documented as 2508 * a "reserved" bit. Best effort attempt to source coherent 2509 * read data here should the balance of the register be 2510 * interpreted by the guest: 2511 * 2512 * L2 cache control register 3: 64GB range, 256KB size, 2513 * enabled, latency 0x1, configured 2514 */ 2515 data = 0xbe702111; 2516 break; 2517 case MSR_AMD64_OSVW_ID_LENGTH: 2518 if (!guest_cpuid_has_osvw(vcpu)) 2519 return 1; 2520 data = vcpu->arch.osvw.length; 2521 break; 2522 case MSR_AMD64_OSVW_STATUS: 2523 if (!guest_cpuid_has_osvw(vcpu)) 2524 return 1; 2525 data = vcpu->arch.osvw.status; 2526 break; 2527 default: 2528 if (kvm_pmu_msr(vcpu, msr)) 2529 return kvm_pmu_get_msr(vcpu, msr, pdata); 2530 if (!ignore_msrs) { 2531 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); 2532 return 1; 2533 } else { 2534 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); 2535 data = 0; 2536 } 2537 break; 2538 } 2539 *pdata = data; 2540 return 0; 2541 } 2542 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 2543 2544 /* 2545 * Read or write a bunch of msrs. All parameters are kernel addresses. 2546 * 2547 * @return number of msrs set successfully. 2548 */ 2549 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, 2550 struct kvm_msr_entry *entries, 2551 int (*do_msr)(struct kvm_vcpu *vcpu, 2552 unsigned index, u64 *data)) 2553 { 2554 int i, idx; 2555 2556 idx = srcu_read_lock(&vcpu->kvm->srcu); 2557 for (i = 0; i < msrs->nmsrs; ++i) 2558 if (do_msr(vcpu, entries[i].index, &entries[i].data)) 2559 break; 2560 srcu_read_unlock(&vcpu->kvm->srcu, idx); 2561 2562 return i; 2563 } 2564 2565 /* 2566 * Read or write a bunch of msrs. Parameters are user addresses. 2567 * 2568 * @return number of msrs set successfully. 2569 */ 2570 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, 2571 int (*do_msr)(struct kvm_vcpu *vcpu, 2572 unsigned index, u64 *data), 2573 int writeback) 2574 { 2575 struct kvm_msrs msrs; 2576 struct kvm_msr_entry *entries; 2577 int r, n; 2578 unsigned size; 2579 2580 r = -EFAULT; 2581 if (copy_from_user(&msrs, user_msrs, sizeof msrs)) 2582 goto out; 2583 2584 r = -E2BIG; 2585 if (msrs.nmsrs >= MAX_IO_MSRS) 2586 goto out; 2587 2588 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; 2589 entries = memdup_user(user_msrs->entries, size); 2590 if (IS_ERR(entries)) { 2591 r = PTR_ERR(entries); 2592 goto out; 2593 } 2594 2595 r = n = __msr_io(vcpu, &msrs, entries, do_msr); 2596 if (r < 0) 2597 goto out_free; 2598 2599 r = -EFAULT; 2600 if (writeback && copy_to_user(user_msrs->entries, entries, size)) 2601 goto out_free; 2602 2603 r = n; 2604 2605 out_free: 2606 kfree(entries); 2607 out: 2608 return r; 2609 } 2610 2611 int kvm_dev_ioctl_check_extension(long ext) 2612 { 2613 int r; 2614 2615 switch (ext) { 2616 case KVM_CAP_IRQCHIP: 2617 case KVM_CAP_HLT: 2618 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 2619 case KVM_CAP_SET_TSS_ADDR: 2620 case KVM_CAP_EXT_CPUID: 2621 case KVM_CAP_EXT_EMUL_CPUID: 2622 case KVM_CAP_CLOCKSOURCE: 2623 case KVM_CAP_PIT: 2624 case KVM_CAP_NOP_IO_DELAY: 2625 case KVM_CAP_MP_STATE: 2626 case KVM_CAP_SYNC_MMU: 2627 case KVM_CAP_USER_NMI: 2628 case KVM_CAP_REINJECT_CONTROL: 2629 case KVM_CAP_IRQ_INJECT_STATUS: 2630 case KVM_CAP_IRQFD: 2631 case KVM_CAP_IOEVENTFD: 2632 case KVM_CAP_IOEVENTFD_NO_LENGTH: 2633 case KVM_CAP_PIT2: 2634 case KVM_CAP_PIT_STATE2: 2635 case KVM_CAP_SET_IDENTITY_MAP_ADDR: 2636 case KVM_CAP_XEN_HVM: 2637 case KVM_CAP_ADJUST_CLOCK: 2638 case KVM_CAP_VCPU_EVENTS: 2639 case KVM_CAP_HYPERV: 2640 case KVM_CAP_HYPERV_VAPIC: 2641 case KVM_CAP_HYPERV_SPIN: 2642 case KVM_CAP_PCI_SEGMENT: 2643 case KVM_CAP_DEBUGREGS: 2644 case KVM_CAP_X86_ROBUST_SINGLESTEP: 2645 case KVM_CAP_XSAVE: 2646 case KVM_CAP_ASYNC_PF: 2647 case KVM_CAP_GET_TSC_KHZ: 2648 case KVM_CAP_KVMCLOCK_CTRL: 2649 case KVM_CAP_READONLY_MEM: 2650 case KVM_CAP_HYPERV_TIME: 2651 case KVM_CAP_IOAPIC_POLARITY_IGNORED: 2652 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2653 case KVM_CAP_ASSIGN_DEV_IRQ: 2654 case KVM_CAP_PCI_2_3: 2655 #endif 2656 r = 1; 2657 break; 2658 case KVM_CAP_COALESCED_MMIO: 2659 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 2660 break; 2661 case KVM_CAP_VAPIC: 2662 r = !kvm_x86_ops->cpu_has_accelerated_tpr(); 2663 break; 2664 case KVM_CAP_NR_VCPUS: 2665 r = KVM_SOFT_MAX_VCPUS; 2666 break; 2667 case KVM_CAP_MAX_VCPUS: 2668 r = KVM_MAX_VCPUS; 2669 break; 2670 case KVM_CAP_NR_MEMSLOTS: 2671 r = KVM_USER_MEM_SLOTS; 2672 break; 2673 case KVM_CAP_PV_MMU: /* obsolete */ 2674 r = 0; 2675 break; 2676 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT 2677 case KVM_CAP_IOMMU: 2678 r = iommu_present(&pci_bus_type); 2679 break; 2680 #endif 2681 case KVM_CAP_MCE: 2682 r = KVM_MAX_MCE_BANKS; 2683 break; 2684 case KVM_CAP_XCRS: 2685 r = cpu_has_xsave; 2686 break; 2687 case KVM_CAP_TSC_CONTROL: 2688 r = kvm_has_tsc_control; 2689 break; 2690 case KVM_CAP_TSC_DEADLINE_TIMER: 2691 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER); 2692 break; 2693 default: 2694 r = 0; 2695 break; 2696 } 2697 return r; 2698 2699 } 2700 2701 long kvm_arch_dev_ioctl(struct file *filp, 2702 unsigned int ioctl, unsigned long arg) 2703 { 2704 void __user *argp = (void __user *)arg; 2705 long r; 2706 2707 switch (ioctl) { 2708 case KVM_GET_MSR_INDEX_LIST: { 2709 struct kvm_msr_list __user *user_msr_list = argp; 2710 struct kvm_msr_list msr_list; 2711 unsigned n; 2712 2713 r = -EFAULT; 2714 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) 2715 goto out; 2716 n = msr_list.nmsrs; 2717 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); 2718 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) 2719 goto out; 2720 r = -E2BIG; 2721 if (n < msr_list.nmsrs) 2722 goto out; 2723 r = -EFAULT; 2724 if (copy_to_user(user_msr_list->indices, &msrs_to_save, 2725 num_msrs_to_save * sizeof(u32))) 2726 goto out; 2727 if (copy_to_user(user_msr_list->indices + num_msrs_to_save, 2728 &emulated_msrs, 2729 ARRAY_SIZE(emulated_msrs) * sizeof(u32))) 2730 goto out; 2731 r = 0; 2732 break; 2733 } 2734 case KVM_GET_SUPPORTED_CPUID: 2735 case KVM_GET_EMULATED_CPUID: { 2736 struct kvm_cpuid2 __user *cpuid_arg = argp; 2737 struct kvm_cpuid2 cpuid; 2738 2739 r = -EFAULT; 2740 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 2741 goto out; 2742 2743 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, 2744 ioctl); 2745 if (r) 2746 goto out; 2747 2748 r = -EFAULT; 2749 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 2750 goto out; 2751 r = 0; 2752 break; 2753 } 2754 case KVM_X86_GET_MCE_CAP_SUPPORTED: { 2755 u64 mce_cap; 2756 2757 mce_cap = KVM_MCE_CAP_SUPPORTED; 2758 r = -EFAULT; 2759 if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) 2760 goto out; 2761 r = 0; 2762 break; 2763 } 2764 default: 2765 r = -EINVAL; 2766 } 2767 out: 2768 return r; 2769 } 2770 2771 static void wbinvd_ipi(void *garbage) 2772 { 2773 wbinvd(); 2774 } 2775 2776 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) 2777 { 2778 return kvm_arch_has_noncoherent_dma(vcpu->kvm); 2779 } 2780 2781 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 2782 { 2783 /* Address WBINVD may be executed by guest */ 2784 if (need_emulate_wbinvd(vcpu)) { 2785 if (kvm_x86_ops->has_wbinvd_exit()) 2786 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 2787 else if (vcpu->cpu != -1 && vcpu->cpu != cpu) 2788 smp_call_function_single(vcpu->cpu, 2789 wbinvd_ipi, NULL, 1); 2790 } 2791 2792 kvm_x86_ops->vcpu_load(vcpu, cpu); 2793 2794 /* Apply any externally detected TSC adjustments (due to suspend) */ 2795 if (unlikely(vcpu->arch.tsc_offset_adjustment)) { 2796 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); 2797 vcpu->arch.tsc_offset_adjustment = 0; 2798 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); 2799 } 2800 2801 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) { 2802 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : 2803 native_read_tsc() - vcpu->arch.last_host_tsc; 2804 if (tsc_delta < 0) 2805 mark_tsc_unstable("KVM discovered backwards TSC"); 2806 if (check_tsc_unstable()) { 2807 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu, 2808 vcpu->arch.last_guest_tsc); 2809 kvm_x86_ops->write_tsc_offset(vcpu, offset); 2810 vcpu->arch.tsc_catchup = 1; 2811 } 2812 /* 2813 * On a host with synchronized TSC, there is no need to update 2814 * kvmclock on vcpu->cpu migration 2815 */ 2816 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) 2817 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); 2818 if (vcpu->cpu != cpu) 2819 kvm_migrate_timers(vcpu); 2820 vcpu->cpu = cpu; 2821 } 2822 2823 accumulate_steal_time(vcpu); 2824 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 2825 } 2826 2827 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 2828 { 2829 kvm_x86_ops->vcpu_put(vcpu); 2830 kvm_put_guest_fpu(vcpu); 2831 vcpu->arch.last_host_tsc = native_read_tsc(); 2832 } 2833 2834 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, 2835 struct kvm_lapic_state *s) 2836 { 2837 kvm_x86_ops->sync_pir_to_irr(vcpu); 2838 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); 2839 2840 return 0; 2841 } 2842 2843 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, 2844 struct kvm_lapic_state *s) 2845 { 2846 kvm_apic_post_state_restore(vcpu, s); 2847 update_cr8_intercept(vcpu); 2848 2849 return 0; 2850 } 2851 2852 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 2853 struct kvm_interrupt *irq) 2854 { 2855 if (irq->irq >= KVM_NR_INTERRUPTS) 2856 return -EINVAL; 2857 if (irqchip_in_kernel(vcpu->kvm)) 2858 return -ENXIO; 2859 2860 kvm_queue_interrupt(vcpu, irq->irq, false); 2861 kvm_make_request(KVM_REQ_EVENT, vcpu); 2862 2863 return 0; 2864 } 2865 2866 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) 2867 { 2868 kvm_inject_nmi(vcpu); 2869 2870 return 0; 2871 } 2872 2873 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, 2874 struct kvm_tpr_access_ctl *tac) 2875 { 2876 if (tac->flags) 2877 return -EINVAL; 2878 vcpu->arch.tpr_access_reporting = !!tac->enabled; 2879 return 0; 2880 } 2881 2882 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, 2883 u64 mcg_cap) 2884 { 2885 int r; 2886 unsigned bank_num = mcg_cap & 0xff, bank; 2887 2888 r = -EINVAL; 2889 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) 2890 goto out; 2891 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) 2892 goto out; 2893 r = 0; 2894 vcpu->arch.mcg_cap = mcg_cap; 2895 /* Init IA32_MCG_CTL to all 1s */ 2896 if (mcg_cap & MCG_CTL_P) 2897 vcpu->arch.mcg_ctl = ~(u64)0; 2898 /* Init IA32_MCi_CTL to all 1s */ 2899 for (bank = 0; bank < bank_num; bank++) 2900 vcpu->arch.mce_banks[bank*4] = ~(u64)0; 2901 out: 2902 return r; 2903 } 2904 2905 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, 2906 struct kvm_x86_mce *mce) 2907 { 2908 u64 mcg_cap = vcpu->arch.mcg_cap; 2909 unsigned bank_num = mcg_cap & 0xff; 2910 u64 *banks = vcpu->arch.mce_banks; 2911 2912 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) 2913 return -EINVAL; 2914 /* 2915 * if IA32_MCG_CTL is not all 1s, the uncorrected error 2916 * reporting is disabled 2917 */ 2918 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && 2919 vcpu->arch.mcg_ctl != ~(u64)0) 2920 return 0; 2921 banks += 4 * mce->bank; 2922 /* 2923 * if IA32_MCi_CTL is not all 1s, the uncorrected error 2924 * reporting is disabled for the bank 2925 */ 2926 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) 2927 return 0; 2928 if (mce->status & MCI_STATUS_UC) { 2929 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || 2930 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { 2931 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); 2932 return 0; 2933 } 2934 if (banks[1] & MCI_STATUS_VAL) 2935 mce->status |= MCI_STATUS_OVER; 2936 banks[2] = mce->addr; 2937 banks[3] = mce->misc; 2938 vcpu->arch.mcg_status = mce->mcg_status; 2939 banks[1] = mce->status; 2940 kvm_queue_exception(vcpu, MC_VECTOR); 2941 } else if (!(banks[1] & MCI_STATUS_VAL) 2942 || !(banks[1] & MCI_STATUS_UC)) { 2943 if (banks[1] & MCI_STATUS_VAL) 2944 mce->status |= MCI_STATUS_OVER; 2945 banks[2] = mce->addr; 2946 banks[3] = mce->misc; 2947 banks[1] = mce->status; 2948 } else 2949 banks[1] |= MCI_STATUS_OVER; 2950 return 0; 2951 } 2952 2953 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, 2954 struct kvm_vcpu_events *events) 2955 { 2956 process_nmi(vcpu); 2957 events->exception.injected = 2958 vcpu->arch.exception.pending && 2959 !kvm_exception_is_soft(vcpu->arch.exception.nr); 2960 events->exception.nr = vcpu->arch.exception.nr; 2961 events->exception.has_error_code = vcpu->arch.exception.has_error_code; 2962 events->exception.pad = 0; 2963 events->exception.error_code = vcpu->arch.exception.error_code; 2964 2965 events->interrupt.injected = 2966 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft; 2967 events->interrupt.nr = vcpu->arch.interrupt.nr; 2968 events->interrupt.soft = 0; 2969 events->interrupt.shadow = 2970 kvm_x86_ops->get_interrupt_shadow(vcpu, 2971 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI); 2972 2973 events->nmi.injected = vcpu->arch.nmi_injected; 2974 events->nmi.pending = vcpu->arch.nmi_pending != 0; 2975 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); 2976 events->nmi.pad = 0; 2977 2978 events->sipi_vector = 0; /* never valid when reporting to user space */ 2979 2980 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING 2981 | KVM_VCPUEVENT_VALID_SHADOW); 2982 memset(&events->reserved, 0, sizeof(events->reserved)); 2983 } 2984 2985 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, 2986 struct kvm_vcpu_events *events) 2987 { 2988 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING 2989 | KVM_VCPUEVENT_VALID_SIPI_VECTOR 2990 | KVM_VCPUEVENT_VALID_SHADOW)) 2991 return -EINVAL; 2992 2993 process_nmi(vcpu); 2994 vcpu->arch.exception.pending = events->exception.injected; 2995 vcpu->arch.exception.nr = events->exception.nr; 2996 vcpu->arch.exception.has_error_code = events->exception.has_error_code; 2997 vcpu->arch.exception.error_code = events->exception.error_code; 2998 2999 vcpu->arch.interrupt.pending = events->interrupt.injected; 3000 vcpu->arch.interrupt.nr = events->interrupt.nr; 3001 vcpu->arch.interrupt.soft = events->interrupt.soft; 3002 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) 3003 kvm_x86_ops->set_interrupt_shadow(vcpu, 3004 events->interrupt.shadow); 3005 3006 vcpu->arch.nmi_injected = events->nmi.injected; 3007 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) 3008 vcpu->arch.nmi_pending = events->nmi.pending; 3009 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); 3010 3011 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && 3012 kvm_vcpu_has_lapic(vcpu)) 3013 vcpu->arch.apic->sipi_vector = events->sipi_vector; 3014 3015 kvm_make_request(KVM_REQ_EVENT, vcpu); 3016 3017 return 0; 3018 } 3019 3020 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, 3021 struct kvm_debugregs *dbgregs) 3022 { 3023 unsigned long val; 3024 3025 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); 3026 _kvm_get_dr(vcpu, 6, &val); 3027 dbgregs->dr6 = val; 3028 dbgregs->dr7 = vcpu->arch.dr7; 3029 dbgregs->flags = 0; 3030 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); 3031 } 3032 3033 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, 3034 struct kvm_debugregs *dbgregs) 3035 { 3036 if (dbgregs->flags) 3037 return -EINVAL; 3038 3039 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); 3040 vcpu->arch.dr6 = dbgregs->dr6; 3041 kvm_update_dr6(vcpu); 3042 vcpu->arch.dr7 = dbgregs->dr7; 3043 kvm_update_dr7(vcpu); 3044 3045 return 0; 3046 } 3047 3048 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, 3049 struct kvm_xsave *guest_xsave) 3050 { 3051 if (cpu_has_xsave) { 3052 memcpy(guest_xsave->region, 3053 &vcpu->arch.guest_fpu.state->xsave, 3054 vcpu->arch.guest_xstate_size); 3055 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &= 3056 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE; 3057 } else { 3058 memcpy(guest_xsave->region, 3059 &vcpu->arch.guest_fpu.state->fxsave, 3060 sizeof(struct i387_fxsave_struct)); 3061 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] = 3062 XSTATE_FPSSE; 3063 } 3064 } 3065 3066 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, 3067 struct kvm_xsave *guest_xsave) 3068 { 3069 u64 xstate_bv = 3070 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)]; 3071 3072 if (cpu_has_xsave) { 3073 /* 3074 * Here we allow setting states that are not present in 3075 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility 3076 * with old userspace. 3077 */ 3078 if (xstate_bv & ~kvm_supported_xcr0()) 3079 return -EINVAL; 3080 memcpy(&vcpu->arch.guest_fpu.state->xsave, 3081 guest_xsave->region, vcpu->arch.guest_xstate_size); 3082 } else { 3083 if (xstate_bv & ~XSTATE_FPSSE) 3084 return -EINVAL; 3085 memcpy(&vcpu->arch.guest_fpu.state->fxsave, 3086 guest_xsave->region, sizeof(struct i387_fxsave_struct)); 3087 } 3088 return 0; 3089 } 3090 3091 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, 3092 struct kvm_xcrs *guest_xcrs) 3093 { 3094 if (!cpu_has_xsave) { 3095 guest_xcrs->nr_xcrs = 0; 3096 return; 3097 } 3098 3099 guest_xcrs->nr_xcrs = 1; 3100 guest_xcrs->flags = 0; 3101 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; 3102 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; 3103 } 3104 3105 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, 3106 struct kvm_xcrs *guest_xcrs) 3107 { 3108 int i, r = 0; 3109 3110 if (!cpu_has_xsave) 3111 return -EINVAL; 3112 3113 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) 3114 return -EINVAL; 3115 3116 for (i = 0; i < guest_xcrs->nr_xcrs; i++) 3117 /* Only support XCR0 currently */ 3118 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { 3119 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, 3120 guest_xcrs->xcrs[i].value); 3121 break; 3122 } 3123 if (r) 3124 r = -EINVAL; 3125 return r; 3126 } 3127 3128 /* 3129 * kvm_set_guest_paused() indicates to the guest kernel that it has been 3130 * stopped by the hypervisor. This function will be called from the host only. 3131 * EINVAL is returned when the host attempts to set the flag for a guest that 3132 * does not support pv clocks. 3133 */ 3134 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) 3135 { 3136 if (!vcpu->arch.pv_time_enabled) 3137 return -EINVAL; 3138 vcpu->arch.pvclock_set_guest_stopped_request = true; 3139 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 3140 return 0; 3141 } 3142 3143 long kvm_arch_vcpu_ioctl(struct file *filp, 3144 unsigned int ioctl, unsigned long arg) 3145 { 3146 struct kvm_vcpu *vcpu = filp->private_data; 3147 void __user *argp = (void __user *)arg; 3148 int r; 3149 union { 3150 struct kvm_lapic_state *lapic; 3151 struct kvm_xsave *xsave; 3152 struct kvm_xcrs *xcrs; 3153 void *buffer; 3154 } u; 3155 3156 u.buffer = NULL; 3157 switch (ioctl) { 3158 case KVM_GET_LAPIC: { 3159 r = -EINVAL; 3160 if (!vcpu->arch.apic) 3161 goto out; 3162 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); 3163 3164 r = -ENOMEM; 3165 if (!u.lapic) 3166 goto out; 3167 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); 3168 if (r) 3169 goto out; 3170 r = -EFAULT; 3171 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) 3172 goto out; 3173 r = 0; 3174 break; 3175 } 3176 case KVM_SET_LAPIC: { 3177 r = -EINVAL; 3178 if (!vcpu->arch.apic) 3179 goto out; 3180 u.lapic = memdup_user(argp, sizeof(*u.lapic)); 3181 if (IS_ERR(u.lapic)) 3182 return PTR_ERR(u.lapic); 3183 3184 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); 3185 break; 3186 } 3187 case KVM_INTERRUPT: { 3188 struct kvm_interrupt irq; 3189 3190 r = -EFAULT; 3191 if (copy_from_user(&irq, argp, sizeof irq)) 3192 goto out; 3193 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 3194 break; 3195 } 3196 case KVM_NMI: { 3197 r = kvm_vcpu_ioctl_nmi(vcpu); 3198 break; 3199 } 3200 case KVM_SET_CPUID: { 3201 struct kvm_cpuid __user *cpuid_arg = argp; 3202 struct kvm_cpuid cpuid; 3203 3204 r = -EFAULT; 3205 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3206 goto out; 3207 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); 3208 break; 3209 } 3210 case KVM_SET_CPUID2: { 3211 struct kvm_cpuid2 __user *cpuid_arg = argp; 3212 struct kvm_cpuid2 cpuid; 3213 3214 r = -EFAULT; 3215 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3216 goto out; 3217 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, 3218 cpuid_arg->entries); 3219 break; 3220 } 3221 case KVM_GET_CPUID2: { 3222 struct kvm_cpuid2 __user *cpuid_arg = argp; 3223 struct kvm_cpuid2 cpuid; 3224 3225 r = -EFAULT; 3226 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) 3227 goto out; 3228 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, 3229 cpuid_arg->entries); 3230 if (r) 3231 goto out; 3232 r = -EFAULT; 3233 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) 3234 goto out; 3235 r = 0; 3236 break; 3237 } 3238 case KVM_GET_MSRS: 3239 r = msr_io(vcpu, argp, kvm_get_msr, 1); 3240 break; 3241 case KVM_SET_MSRS: 3242 r = msr_io(vcpu, argp, do_set_msr, 0); 3243 break; 3244 case KVM_TPR_ACCESS_REPORTING: { 3245 struct kvm_tpr_access_ctl tac; 3246 3247 r = -EFAULT; 3248 if (copy_from_user(&tac, argp, sizeof tac)) 3249 goto out; 3250 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); 3251 if (r) 3252 goto out; 3253 r = -EFAULT; 3254 if (copy_to_user(argp, &tac, sizeof tac)) 3255 goto out; 3256 r = 0; 3257 break; 3258 }; 3259 case KVM_SET_VAPIC_ADDR: { 3260 struct kvm_vapic_addr va; 3261 3262 r = -EINVAL; 3263 if (!irqchip_in_kernel(vcpu->kvm)) 3264 goto out; 3265 r = -EFAULT; 3266 if (copy_from_user(&va, argp, sizeof va)) 3267 goto out; 3268 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); 3269 break; 3270 } 3271 case KVM_X86_SETUP_MCE: { 3272 u64 mcg_cap; 3273 3274 r = -EFAULT; 3275 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) 3276 goto out; 3277 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); 3278 break; 3279 } 3280 case KVM_X86_SET_MCE: { 3281 struct kvm_x86_mce mce; 3282 3283 r = -EFAULT; 3284 if (copy_from_user(&mce, argp, sizeof mce)) 3285 goto out; 3286 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); 3287 break; 3288 } 3289 case KVM_GET_VCPU_EVENTS: { 3290 struct kvm_vcpu_events events; 3291 3292 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); 3293 3294 r = -EFAULT; 3295 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) 3296 break; 3297 r = 0; 3298 break; 3299 } 3300 case KVM_SET_VCPU_EVENTS: { 3301 struct kvm_vcpu_events events; 3302 3303 r = -EFAULT; 3304 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) 3305 break; 3306 3307 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); 3308 break; 3309 } 3310 case KVM_GET_DEBUGREGS: { 3311 struct kvm_debugregs dbgregs; 3312 3313 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); 3314 3315 r = -EFAULT; 3316 if (copy_to_user(argp, &dbgregs, 3317 sizeof(struct kvm_debugregs))) 3318 break; 3319 r = 0; 3320 break; 3321 } 3322 case KVM_SET_DEBUGREGS: { 3323 struct kvm_debugregs dbgregs; 3324 3325 r = -EFAULT; 3326 if (copy_from_user(&dbgregs, argp, 3327 sizeof(struct kvm_debugregs))) 3328 break; 3329 3330 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); 3331 break; 3332 } 3333 case KVM_GET_XSAVE: { 3334 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL); 3335 r = -ENOMEM; 3336 if (!u.xsave) 3337 break; 3338 3339 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); 3340 3341 r = -EFAULT; 3342 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) 3343 break; 3344 r = 0; 3345 break; 3346 } 3347 case KVM_SET_XSAVE: { 3348 u.xsave = memdup_user(argp, sizeof(*u.xsave)); 3349 if (IS_ERR(u.xsave)) 3350 return PTR_ERR(u.xsave); 3351 3352 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); 3353 break; 3354 } 3355 case KVM_GET_XCRS: { 3356 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL); 3357 r = -ENOMEM; 3358 if (!u.xcrs) 3359 break; 3360 3361 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); 3362 3363 r = -EFAULT; 3364 if (copy_to_user(argp, u.xcrs, 3365 sizeof(struct kvm_xcrs))) 3366 break; 3367 r = 0; 3368 break; 3369 } 3370 case KVM_SET_XCRS: { 3371 u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); 3372 if (IS_ERR(u.xcrs)) 3373 return PTR_ERR(u.xcrs); 3374 3375 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); 3376 break; 3377 } 3378 case KVM_SET_TSC_KHZ: { 3379 u32 user_tsc_khz; 3380 3381 r = -EINVAL; 3382 user_tsc_khz = (u32)arg; 3383 3384 if (user_tsc_khz >= kvm_max_guest_tsc_khz) 3385 goto out; 3386 3387 if (user_tsc_khz == 0) 3388 user_tsc_khz = tsc_khz; 3389 3390 kvm_set_tsc_khz(vcpu, user_tsc_khz); 3391 3392 r = 0; 3393 goto out; 3394 } 3395 case KVM_GET_TSC_KHZ: { 3396 r = vcpu->arch.virtual_tsc_khz; 3397 goto out; 3398 } 3399 case KVM_KVMCLOCK_CTRL: { 3400 r = kvm_set_guest_paused(vcpu); 3401 goto out; 3402 } 3403 default: 3404 r = -EINVAL; 3405 } 3406 out: 3407 kfree(u.buffer); 3408 return r; 3409 } 3410 3411 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 3412 { 3413 return VM_FAULT_SIGBUS; 3414 } 3415 3416 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) 3417 { 3418 int ret; 3419 3420 if (addr > (unsigned int)(-3 * PAGE_SIZE)) 3421 return -EINVAL; 3422 ret = kvm_x86_ops->set_tss_addr(kvm, addr); 3423 return ret; 3424 } 3425 3426 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, 3427 u64 ident_addr) 3428 { 3429 kvm->arch.ept_identity_map_addr = ident_addr; 3430 return 0; 3431 } 3432 3433 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, 3434 u32 kvm_nr_mmu_pages) 3435 { 3436 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) 3437 return -EINVAL; 3438 3439 mutex_lock(&kvm->slots_lock); 3440 3441 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); 3442 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; 3443 3444 mutex_unlock(&kvm->slots_lock); 3445 return 0; 3446 } 3447 3448 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) 3449 { 3450 return kvm->arch.n_max_mmu_pages; 3451 } 3452 3453 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3454 { 3455 int r; 3456 3457 r = 0; 3458 switch (chip->chip_id) { 3459 case KVM_IRQCHIP_PIC_MASTER: 3460 memcpy(&chip->chip.pic, 3461 &pic_irqchip(kvm)->pics[0], 3462 sizeof(struct kvm_pic_state)); 3463 break; 3464 case KVM_IRQCHIP_PIC_SLAVE: 3465 memcpy(&chip->chip.pic, 3466 &pic_irqchip(kvm)->pics[1], 3467 sizeof(struct kvm_pic_state)); 3468 break; 3469 case KVM_IRQCHIP_IOAPIC: 3470 r = kvm_get_ioapic(kvm, &chip->chip.ioapic); 3471 break; 3472 default: 3473 r = -EINVAL; 3474 break; 3475 } 3476 return r; 3477 } 3478 3479 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) 3480 { 3481 int r; 3482 3483 r = 0; 3484 switch (chip->chip_id) { 3485 case KVM_IRQCHIP_PIC_MASTER: 3486 spin_lock(&pic_irqchip(kvm)->lock); 3487 memcpy(&pic_irqchip(kvm)->pics[0], 3488 &chip->chip.pic, 3489 sizeof(struct kvm_pic_state)); 3490 spin_unlock(&pic_irqchip(kvm)->lock); 3491 break; 3492 case KVM_IRQCHIP_PIC_SLAVE: 3493 spin_lock(&pic_irqchip(kvm)->lock); 3494 memcpy(&pic_irqchip(kvm)->pics[1], 3495 &chip->chip.pic, 3496 sizeof(struct kvm_pic_state)); 3497 spin_unlock(&pic_irqchip(kvm)->lock); 3498 break; 3499 case KVM_IRQCHIP_IOAPIC: 3500 r = kvm_set_ioapic(kvm, &chip->chip.ioapic); 3501 break; 3502 default: 3503 r = -EINVAL; 3504 break; 3505 } 3506 kvm_pic_update_irq(pic_irqchip(kvm)); 3507 return r; 3508 } 3509 3510 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3511 { 3512 int r = 0; 3513 3514 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3515 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); 3516 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3517 return r; 3518 } 3519 3520 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) 3521 { 3522 int r = 0; 3523 3524 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3525 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); 3526 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); 3527 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3528 return r; 3529 } 3530 3531 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3532 { 3533 int r = 0; 3534 3535 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3536 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, 3537 sizeof(ps->channels)); 3538 ps->flags = kvm->arch.vpit->pit_state.flags; 3539 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3540 memset(&ps->reserved, 0, sizeof(ps->reserved)); 3541 return r; 3542 } 3543 3544 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) 3545 { 3546 int r = 0, start = 0; 3547 u32 prev_legacy, cur_legacy; 3548 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3549 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; 3550 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; 3551 if (!prev_legacy && cur_legacy) 3552 start = 1; 3553 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, 3554 sizeof(kvm->arch.vpit->pit_state.channels)); 3555 kvm->arch.vpit->pit_state.flags = ps->flags; 3556 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); 3557 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3558 return r; 3559 } 3560 3561 static int kvm_vm_ioctl_reinject(struct kvm *kvm, 3562 struct kvm_reinject_control *control) 3563 { 3564 if (!kvm->arch.vpit) 3565 return -ENXIO; 3566 mutex_lock(&kvm->arch.vpit->pit_state.lock); 3567 kvm->arch.vpit->pit_state.reinject = control->pit_reinject; 3568 mutex_unlock(&kvm->arch.vpit->pit_state.lock); 3569 return 0; 3570 } 3571 3572 /** 3573 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 3574 * @kvm: kvm instance 3575 * @log: slot id and address to which we copy the log 3576 * 3577 * We need to keep it in mind that VCPU threads can write to the bitmap 3578 * concurrently. So, to avoid losing data, we keep the following order for 3579 * each bit: 3580 * 3581 * 1. Take a snapshot of the bit and clear it if needed. 3582 * 2. Write protect the corresponding page. 3583 * 3. Flush TLB's if needed. 3584 * 4. Copy the snapshot to the userspace. 3585 * 3586 * Between 2 and 3, the guest may write to the page using the remaining TLB 3587 * entry. This is not a problem because the page will be reported dirty at 3588 * step 4 using the snapshot taken before and step 3 ensures that successive 3589 * writes will be logged for the next call. 3590 */ 3591 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 3592 { 3593 int r; 3594 struct kvm_memory_slot *memslot; 3595 unsigned long n, i; 3596 unsigned long *dirty_bitmap; 3597 unsigned long *dirty_bitmap_buffer; 3598 bool is_dirty = false; 3599 3600 mutex_lock(&kvm->slots_lock); 3601 3602 r = -EINVAL; 3603 if (log->slot >= KVM_USER_MEM_SLOTS) 3604 goto out; 3605 3606 memslot = id_to_memslot(kvm->memslots, log->slot); 3607 3608 dirty_bitmap = memslot->dirty_bitmap; 3609 r = -ENOENT; 3610 if (!dirty_bitmap) 3611 goto out; 3612 3613 n = kvm_dirty_bitmap_bytes(memslot); 3614 3615 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long); 3616 memset(dirty_bitmap_buffer, 0, n); 3617 3618 spin_lock(&kvm->mmu_lock); 3619 3620 for (i = 0; i < n / sizeof(long); i++) { 3621 unsigned long mask; 3622 gfn_t offset; 3623 3624 if (!dirty_bitmap[i]) 3625 continue; 3626 3627 is_dirty = true; 3628 3629 mask = xchg(&dirty_bitmap[i], 0); 3630 dirty_bitmap_buffer[i] = mask; 3631 3632 offset = i * BITS_PER_LONG; 3633 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask); 3634 } 3635 3636 spin_unlock(&kvm->mmu_lock); 3637 3638 /* See the comments in kvm_mmu_slot_remove_write_access(). */ 3639 lockdep_assert_held(&kvm->slots_lock); 3640 3641 /* 3642 * All the TLBs can be flushed out of mmu lock, see the comments in 3643 * kvm_mmu_slot_remove_write_access(). 3644 */ 3645 if (is_dirty) 3646 kvm_flush_remote_tlbs(kvm); 3647 3648 r = -EFAULT; 3649 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n)) 3650 goto out; 3651 3652 r = 0; 3653 out: 3654 mutex_unlock(&kvm->slots_lock); 3655 return r; 3656 } 3657 3658 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, 3659 bool line_status) 3660 { 3661 if (!irqchip_in_kernel(kvm)) 3662 return -ENXIO; 3663 3664 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 3665 irq_event->irq, irq_event->level, 3666 line_status); 3667 return 0; 3668 } 3669 3670 long kvm_arch_vm_ioctl(struct file *filp, 3671 unsigned int ioctl, unsigned long arg) 3672 { 3673 struct kvm *kvm = filp->private_data; 3674 void __user *argp = (void __user *)arg; 3675 int r = -ENOTTY; 3676 /* 3677 * This union makes it completely explicit to gcc-3.x 3678 * that these two variables' stack usage should be 3679 * combined, not added together. 3680 */ 3681 union { 3682 struct kvm_pit_state ps; 3683 struct kvm_pit_state2 ps2; 3684 struct kvm_pit_config pit_config; 3685 } u; 3686 3687 switch (ioctl) { 3688 case KVM_SET_TSS_ADDR: 3689 r = kvm_vm_ioctl_set_tss_addr(kvm, arg); 3690 break; 3691 case KVM_SET_IDENTITY_MAP_ADDR: { 3692 u64 ident_addr; 3693 3694 r = -EFAULT; 3695 if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) 3696 goto out; 3697 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); 3698 break; 3699 } 3700 case KVM_SET_NR_MMU_PAGES: 3701 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); 3702 break; 3703 case KVM_GET_NR_MMU_PAGES: 3704 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); 3705 break; 3706 case KVM_CREATE_IRQCHIP: { 3707 struct kvm_pic *vpic; 3708 3709 mutex_lock(&kvm->lock); 3710 r = -EEXIST; 3711 if (kvm->arch.vpic) 3712 goto create_irqchip_unlock; 3713 r = -EINVAL; 3714 if (atomic_read(&kvm->online_vcpus)) 3715 goto create_irqchip_unlock; 3716 r = -ENOMEM; 3717 vpic = kvm_create_pic(kvm); 3718 if (vpic) { 3719 r = kvm_ioapic_init(kvm); 3720 if (r) { 3721 mutex_lock(&kvm->slots_lock); 3722 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, 3723 &vpic->dev_master); 3724 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, 3725 &vpic->dev_slave); 3726 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, 3727 &vpic->dev_eclr); 3728 mutex_unlock(&kvm->slots_lock); 3729 kfree(vpic); 3730 goto create_irqchip_unlock; 3731 } 3732 } else 3733 goto create_irqchip_unlock; 3734 smp_wmb(); 3735 kvm->arch.vpic = vpic; 3736 smp_wmb(); 3737 r = kvm_setup_default_irq_routing(kvm); 3738 if (r) { 3739 mutex_lock(&kvm->slots_lock); 3740 mutex_lock(&kvm->irq_lock); 3741 kvm_ioapic_destroy(kvm); 3742 kvm_destroy_pic(kvm); 3743 mutex_unlock(&kvm->irq_lock); 3744 mutex_unlock(&kvm->slots_lock); 3745 } 3746 create_irqchip_unlock: 3747 mutex_unlock(&kvm->lock); 3748 break; 3749 } 3750 case KVM_CREATE_PIT: 3751 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; 3752 goto create_pit; 3753 case KVM_CREATE_PIT2: 3754 r = -EFAULT; 3755 if (copy_from_user(&u.pit_config, argp, 3756 sizeof(struct kvm_pit_config))) 3757 goto out; 3758 create_pit: 3759 mutex_lock(&kvm->slots_lock); 3760 r = -EEXIST; 3761 if (kvm->arch.vpit) 3762 goto create_pit_unlock; 3763 r = -ENOMEM; 3764 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); 3765 if (kvm->arch.vpit) 3766 r = 0; 3767 create_pit_unlock: 3768 mutex_unlock(&kvm->slots_lock); 3769 break; 3770 case KVM_GET_IRQCHIP: { 3771 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3772 struct kvm_irqchip *chip; 3773 3774 chip = memdup_user(argp, sizeof(*chip)); 3775 if (IS_ERR(chip)) { 3776 r = PTR_ERR(chip); 3777 goto out; 3778 } 3779 3780 r = -ENXIO; 3781 if (!irqchip_in_kernel(kvm)) 3782 goto get_irqchip_out; 3783 r = kvm_vm_ioctl_get_irqchip(kvm, chip); 3784 if (r) 3785 goto get_irqchip_out; 3786 r = -EFAULT; 3787 if (copy_to_user(argp, chip, sizeof *chip)) 3788 goto get_irqchip_out; 3789 r = 0; 3790 get_irqchip_out: 3791 kfree(chip); 3792 break; 3793 } 3794 case KVM_SET_IRQCHIP: { 3795 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ 3796 struct kvm_irqchip *chip; 3797 3798 chip = memdup_user(argp, sizeof(*chip)); 3799 if (IS_ERR(chip)) { 3800 r = PTR_ERR(chip); 3801 goto out; 3802 } 3803 3804 r = -ENXIO; 3805 if (!irqchip_in_kernel(kvm)) 3806 goto set_irqchip_out; 3807 r = kvm_vm_ioctl_set_irqchip(kvm, chip); 3808 if (r) 3809 goto set_irqchip_out; 3810 r = 0; 3811 set_irqchip_out: 3812 kfree(chip); 3813 break; 3814 } 3815 case KVM_GET_PIT: { 3816 r = -EFAULT; 3817 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) 3818 goto out; 3819 r = -ENXIO; 3820 if (!kvm->arch.vpit) 3821 goto out; 3822 r = kvm_vm_ioctl_get_pit(kvm, &u.ps); 3823 if (r) 3824 goto out; 3825 r = -EFAULT; 3826 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) 3827 goto out; 3828 r = 0; 3829 break; 3830 } 3831 case KVM_SET_PIT: { 3832 r = -EFAULT; 3833 if (copy_from_user(&u.ps, argp, sizeof u.ps)) 3834 goto out; 3835 r = -ENXIO; 3836 if (!kvm->arch.vpit) 3837 goto out; 3838 r = kvm_vm_ioctl_set_pit(kvm, &u.ps); 3839 break; 3840 } 3841 case KVM_GET_PIT2: { 3842 r = -ENXIO; 3843 if (!kvm->arch.vpit) 3844 goto out; 3845 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); 3846 if (r) 3847 goto out; 3848 r = -EFAULT; 3849 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) 3850 goto out; 3851 r = 0; 3852 break; 3853 } 3854 case KVM_SET_PIT2: { 3855 r = -EFAULT; 3856 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) 3857 goto out; 3858 r = -ENXIO; 3859 if (!kvm->arch.vpit) 3860 goto out; 3861 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); 3862 break; 3863 } 3864 case KVM_REINJECT_CONTROL: { 3865 struct kvm_reinject_control control; 3866 r = -EFAULT; 3867 if (copy_from_user(&control, argp, sizeof(control))) 3868 goto out; 3869 r = kvm_vm_ioctl_reinject(kvm, &control); 3870 break; 3871 } 3872 case KVM_XEN_HVM_CONFIG: { 3873 r = -EFAULT; 3874 if (copy_from_user(&kvm->arch.xen_hvm_config, argp, 3875 sizeof(struct kvm_xen_hvm_config))) 3876 goto out; 3877 r = -EINVAL; 3878 if (kvm->arch.xen_hvm_config.flags) 3879 goto out; 3880 r = 0; 3881 break; 3882 } 3883 case KVM_SET_CLOCK: { 3884 struct kvm_clock_data user_ns; 3885 u64 now_ns; 3886 s64 delta; 3887 3888 r = -EFAULT; 3889 if (copy_from_user(&user_ns, argp, sizeof(user_ns))) 3890 goto out; 3891 3892 r = -EINVAL; 3893 if (user_ns.flags) 3894 goto out; 3895 3896 r = 0; 3897 local_irq_disable(); 3898 now_ns = get_kernel_ns(); 3899 delta = user_ns.clock - now_ns; 3900 local_irq_enable(); 3901 kvm->arch.kvmclock_offset = delta; 3902 kvm_gen_update_masterclock(kvm); 3903 break; 3904 } 3905 case KVM_GET_CLOCK: { 3906 struct kvm_clock_data user_ns; 3907 u64 now_ns; 3908 3909 local_irq_disable(); 3910 now_ns = get_kernel_ns(); 3911 user_ns.clock = kvm->arch.kvmclock_offset + now_ns; 3912 local_irq_enable(); 3913 user_ns.flags = 0; 3914 memset(&user_ns.pad, 0, sizeof(user_ns.pad)); 3915 3916 r = -EFAULT; 3917 if (copy_to_user(argp, &user_ns, sizeof(user_ns))) 3918 goto out; 3919 r = 0; 3920 break; 3921 } 3922 3923 default: 3924 ; 3925 } 3926 out: 3927 return r; 3928 } 3929 3930 static void kvm_init_msr_list(void) 3931 { 3932 u32 dummy[2]; 3933 unsigned i, j; 3934 3935 /* skip the first msrs in the list. KVM-specific */ 3936 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { 3937 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) 3938 continue; 3939 3940 /* 3941 * Even MSRs that are valid in the host may not be exposed 3942 * to the guests in some cases. We could work around this 3943 * in VMX with the generic MSR save/load machinery, but it 3944 * is not really worthwhile since it will really only 3945 * happen with nested virtualization. 3946 */ 3947 switch (msrs_to_save[i]) { 3948 case MSR_IA32_BNDCFGS: 3949 if (!kvm_x86_ops->mpx_supported()) 3950 continue; 3951 break; 3952 default: 3953 break; 3954 } 3955 3956 if (j < i) 3957 msrs_to_save[j] = msrs_to_save[i]; 3958 j++; 3959 } 3960 num_msrs_to_save = j; 3961 } 3962 3963 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, 3964 const void *v) 3965 { 3966 int handled = 0; 3967 int n; 3968 3969 do { 3970 n = min(len, 8); 3971 if (!(vcpu->arch.apic && 3972 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v)) 3973 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v)) 3974 break; 3975 handled += n; 3976 addr += n; 3977 len -= n; 3978 v += n; 3979 } while (len); 3980 3981 return handled; 3982 } 3983 3984 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) 3985 { 3986 int handled = 0; 3987 int n; 3988 3989 do { 3990 n = min(len, 8); 3991 if (!(vcpu->arch.apic && 3992 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v)) 3993 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v)) 3994 break; 3995 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v); 3996 handled += n; 3997 addr += n; 3998 len -= n; 3999 v += n; 4000 } while (len); 4001 4002 return handled; 4003 } 4004 4005 static void kvm_set_segment(struct kvm_vcpu *vcpu, 4006 struct kvm_segment *var, int seg) 4007 { 4008 kvm_x86_ops->set_segment(vcpu, var, seg); 4009 } 4010 4011 void kvm_get_segment(struct kvm_vcpu *vcpu, 4012 struct kvm_segment *var, int seg) 4013 { 4014 kvm_x86_ops->get_segment(vcpu, var, seg); 4015 } 4016 4017 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access) 4018 { 4019 gpa_t t_gpa; 4020 struct x86_exception exception; 4021 4022 BUG_ON(!mmu_is_nested(vcpu)); 4023 4024 /* NPT walks are always user-walks */ 4025 access |= PFERR_USER_MASK; 4026 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception); 4027 4028 return t_gpa; 4029 } 4030 4031 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, 4032 struct x86_exception *exception) 4033 { 4034 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4035 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4036 } 4037 4038 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, 4039 struct x86_exception *exception) 4040 { 4041 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4042 access |= PFERR_FETCH_MASK; 4043 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4044 } 4045 4046 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, 4047 struct x86_exception *exception) 4048 { 4049 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4050 access |= PFERR_WRITE_MASK; 4051 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4052 } 4053 4054 /* uses this to access any guest's mapped memory without checking CPL */ 4055 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, 4056 struct x86_exception *exception) 4057 { 4058 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception); 4059 } 4060 4061 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, 4062 struct kvm_vcpu *vcpu, u32 access, 4063 struct x86_exception *exception) 4064 { 4065 void *data = val; 4066 int r = X86EMUL_CONTINUE; 4067 4068 while (bytes) { 4069 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access, 4070 exception); 4071 unsigned offset = addr & (PAGE_SIZE-1); 4072 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); 4073 int ret; 4074 4075 if (gpa == UNMAPPED_GVA) 4076 return X86EMUL_PROPAGATE_FAULT; 4077 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread); 4078 if (ret < 0) { 4079 r = X86EMUL_IO_NEEDED; 4080 goto out; 4081 } 4082 4083 bytes -= toread; 4084 data += toread; 4085 addr += toread; 4086 } 4087 out: 4088 return r; 4089 } 4090 4091 /* used for instruction fetching */ 4092 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, 4093 gva_t addr, void *val, unsigned int bytes, 4094 struct x86_exception *exception) 4095 { 4096 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4097 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4098 4099 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 4100 access | PFERR_FETCH_MASK, 4101 exception); 4102 } 4103 4104 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt, 4105 gva_t addr, void *val, unsigned int bytes, 4106 struct x86_exception *exception) 4107 { 4108 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4109 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0; 4110 4111 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, 4112 exception); 4113 } 4114 EXPORT_SYMBOL_GPL(kvm_read_guest_virt); 4115 4116 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4117 gva_t addr, void *val, unsigned int bytes, 4118 struct x86_exception *exception) 4119 { 4120 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4121 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception); 4122 } 4123 4124 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt, 4125 gva_t addr, void *val, 4126 unsigned int bytes, 4127 struct x86_exception *exception) 4128 { 4129 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4130 void *data = val; 4131 int r = X86EMUL_CONTINUE; 4132 4133 while (bytes) { 4134 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, 4135 PFERR_WRITE_MASK, 4136 exception); 4137 unsigned offset = addr & (PAGE_SIZE-1); 4138 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); 4139 int ret; 4140 4141 if (gpa == UNMAPPED_GVA) 4142 return X86EMUL_PROPAGATE_FAULT; 4143 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); 4144 if (ret < 0) { 4145 r = X86EMUL_IO_NEEDED; 4146 goto out; 4147 } 4148 4149 bytes -= towrite; 4150 data += towrite; 4151 addr += towrite; 4152 } 4153 out: 4154 return r; 4155 } 4156 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); 4157 4158 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, 4159 gpa_t *gpa, struct x86_exception *exception, 4160 bool write) 4161 { 4162 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0) 4163 | (write ? PFERR_WRITE_MASK : 0); 4164 4165 if (vcpu_match_mmio_gva(vcpu, gva) 4166 && !permission_fault(vcpu, vcpu->arch.walk_mmu, 4167 vcpu->arch.access, access)) { 4168 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | 4169 (gva & (PAGE_SIZE - 1)); 4170 trace_vcpu_match_mmio(gva, *gpa, write, false); 4171 return 1; 4172 } 4173 4174 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception); 4175 4176 if (*gpa == UNMAPPED_GVA) 4177 return -1; 4178 4179 /* For APIC access vmexit */ 4180 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4181 return 1; 4182 4183 if (vcpu_match_mmio_gpa(vcpu, *gpa)) { 4184 trace_vcpu_match_mmio(gva, *gpa, write, true); 4185 return 1; 4186 } 4187 4188 return 0; 4189 } 4190 4191 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, 4192 const void *val, int bytes) 4193 { 4194 int ret; 4195 4196 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); 4197 if (ret < 0) 4198 return 0; 4199 kvm_mmu_pte_write(vcpu, gpa, val, bytes); 4200 return 1; 4201 } 4202 4203 struct read_write_emulator_ops { 4204 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, 4205 int bytes); 4206 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, 4207 void *val, int bytes); 4208 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4209 int bytes, void *val); 4210 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, 4211 void *val, int bytes); 4212 bool write; 4213 }; 4214 4215 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) 4216 { 4217 if (vcpu->mmio_read_completed) { 4218 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, 4219 vcpu->mmio_fragments[0].gpa, *(u64 *)val); 4220 vcpu->mmio_read_completed = 0; 4221 return 1; 4222 } 4223 4224 return 0; 4225 } 4226 4227 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4228 void *val, int bytes) 4229 { 4230 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes); 4231 } 4232 4233 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, 4234 void *val, int bytes) 4235 { 4236 return emulator_write_phys(vcpu, gpa, val, bytes); 4237 } 4238 4239 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) 4240 { 4241 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); 4242 return vcpu_mmio_write(vcpu, gpa, bytes, val); 4243 } 4244 4245 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4246 void *val, int bytes) 4247 { 4248 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); 4249 return X86EMUL_IO_NEEDED; 4250 } 4251 4252 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, 4253 void *val, int bytes) 4254 { 4255 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; 4256 4257 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); 4258 return X86EMUL_CONTINUE; 4259 } 4260 4261 static const struct read_write_emulator_ops read_emultor = { 4262 .read_write_prepare = read_prepare, 4263 .read_write_emulate = read_emulate, 4264 .read_write_mmio = vcpu_mmio_read, 4265 .read_write_exit_mmio = read_exit_mmio, 4266 }; 4267 4268 static const struct read_write_emulator_ops write_emultor = { 4269 .read_write_emulate = write_emulate, 4270 .read_write_mmio = write_mmio, 4271 .read_write_exit_mmio = write_exit_mmio, 4272 .write = true, 4273 }; 4274 4275 static int emulator_read_write_onepage(unsigned long addr, void *val, 4276 unsigned int bytes, 4277 struct x86_exception *exception, 4278 struct kvm_vcpu *vcpu, 4279 const struct read_write_emulator_ops *ops) 4280 { 4281 gpa_t gpa; 4282 int handled, ret; 4283 bool write = ops->write; 4284 struct kvm_mmio_fragment *frag; 4285 4286 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); 4287 4288 if (ret < 0) 4289 return X86EMUL_PROPAGATE_FAULT; 4290 4291 /* For APIC access vmexit */ 4292 if (ret) 4293 goto mmio; 4294 4295 if (ops->read_write_emulate(vcpu, gpa, val, bytes)) 4296 return X86EMUL_CONTINUE; 4297 4298 mmio: 4299 /* 4300 * Is this MMIO handled locally? 4301 */ 4302 handled = ops->read_write_mmio(vcpu, gpa, bytes, val); 4303 if (handled == bytes) 4304 return X86EMUL_CONTINUE; 4305 4306 gpa += handled; 4307 bytes -= handled; 4308 val += handled; 4309 4310 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); 4311 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; 4312 frag->gpa = gpa; 4313 frag->data = val; 4314 frag->len = bytes; 4315 return X86EMUL_CONTINUE; 4316 } 4317 4318 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr, 4319 void *val, unsigned int bytes, 4320 struct x86_exception *exception, 4321 const struct read_write_emulator_ops *ops) 4322 { 4323 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4324 gpa_t gpa; 4325 int rc; 4326 4327 if (ops->read_write_prepare && 4328 ops->read_write_prepare(vcpu, val, bytes)) 4329 return X86EMUL_CONTINUE; 4330 4331 vcpu->mmio_nr_fragments = 0; 4332 4333 /* Crossing a page boundary? */ 4334 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { 4335 int now; 4336 4337 now = -addr & ~PAGE_MASK; 4338 rc = emulator_read_write_onepage(addr, val, now, exception, 4339 vcpu, ops); 4340 4341 if (rc != X86EMUL_CONTINUE) 4342 return rc; 4343 addr += now; 4344 val += now; 4345 bytes -= now; 4346 } 4347 4348 rc = emulator_read_write_onepage(addr, val, bytes, exception, 4349 vcpu, ops); 4350 if (rc != X86EMUL_CONTINUE) 4351 return rc; 4352 4353 if (!vcpu->mmio_nr_fragments) 4354 return rc; 4355 4356 gpa = vcpu->mmio_fragments[0].gpa; 4357 4358 vcpu->mmio_needed = 1; 4359 vcpu->mmio_cur_fragment = 0; 4360 4361 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); 4362 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; 4363 vcpu->run->exit_reason = KVM_EXIT_MMIO; 4364 vcpu->run->mmio.phys_addr = gpa; 4365 4366 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); 4367 } 4368 4369 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, 4370 unsigned long addr, 4371 void *val, 4372 unsigned int bytes, 4373 struct x86_exception *exception) 4374 { 4375 return emulator_read_write(ctxt, addr, val, bytes, 4376 exception, &read_emultor); 4377 } 4378 4379 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, 4380 unsigned long addr, 4381 const void *val, 4382 unsigned int bytes, 4383 struct x86_exception *exception) 4384 { 4385 return emulator_read_write(ctxt, addr, (void *)val, bytes, 4386 exception, &write_emultor); 4387 } 4388 4389 #define CMPXCHG_TYPE(t, ptr, old, new) \ 4390 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old)) 4391 4392 #ifdef CONFIG_X86_64 4393 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new) 4394 #else 4395 # define CMPXCHG64(ptr, old, new) \ 4396 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old)) 4397 #endif 4398 4399 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, 4400 unsigned long addr, 4401 const void *old, 4402 const void *new, 4403 unsigned int bytes, 4404 struct x86_exception *exception) 4405 { 4406 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4407 gpa_t gpa; 4408 struct page *page; 4409 char *kaddr; 4410 bool exchanged; 4411 4412 /* guests cmpxchg8b have to be emulated atomically */ 4413 if (bytes > 8 || (bytes & (bytes - 1))) 4414 goto emul_write; 4415 4416 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); 4417 4418 if (gpa == UNMAPPED_GVA || 4419 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) 4420 goto emul_write; 4421 4422 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) 4423 goto emul_write; 4424 4425 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); 4426 if (is_error_page(page)) 4427 goto emul_write; 4428 4429 kaddr = kmap_atomic(page); 4430 kaddr += offset_in_page(gpa); 4431 switch (bytes) { 4432 case 1: 4433 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new); 4434 break; 4435 case 2: 4436 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new); 4437 break; 4438 case 4: 4439 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new); 4440 break; 4441 case 8: 4442 exchanged = CMPXCHG64(kaddr, old, new); 4443 break; 4444 default: 4445 BUG(); 4446 } 4447 kunmap_atomic(kaddr); 4448 kvm_release_page_dirty(page); 4449 4450 if (!exchanged) 4451 return X86EMUL_CMPXCHG_FAILED; 4452 4453 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT); 4454 kvm_mmu_pte_write(vcpu, gpa, new, bytes); 4455 4456 return X86EMUL_CONTINUE; 4457 4458 emul_write: 4459 printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); 4460 4461 return emulator_write_emulated(ctxt, addr, new, bytes, exception); 4462 } 4463 4464 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) 4465 { 4466 /* TODO: String I/O for in kernel device */ 4467 int r; 4468 4469 if (vcpu->arch.pio.in) 4470 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port, 4471 vcpu->arch.pio.size, pd); 4472 else 4473 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS, 4474 vcpu->arch.pio.port, vcpu->arch.pio.size, 4475 pd); 4476 return r; 4477 } 4478 4479 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, 4480 unsigned short port, void *val, 4481 unsigned int count, bool in) 4482 { 4483 trace_kvm_pio(!in, port, size, count); 4484 4485 vcpu->arch.pio.port = port; 4486 vcpu->arch.pio.in = in; 4487 vcpu->arch.pio.count = count; 4488 vcpu->arch.pio.size = size; 4489 4490 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { 4491 vcpu->arch.pio.count = 0; 4492 return 1; 4493 } 4494 4495 vcpu->run->exit_reason = KVM_EXIT_IO; 4496 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; 4497 vcpu->run->io.size = size; 4498 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; 4499 vcpu->run->io.count = count; 4500 vcpu->run->io.port = port; 4501 4502 return 0; 4503 } 4504 4505 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, 4506 int size, unsigned short port, void *val, 4507 unsigned int count) 4508 { 4509 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4510 int ret; 4511 4512 if (vcpu->arch.pio.count) 4513 goto data_avail; 4514 4515 ret = emulator_pio_in_out(vcpu, size, port, val, count, true); 4516 if (ret) { 4517 data_avail: 4518 memcpy(val, vcpu->arch.pio_data, size * count); 4519 vcpu->arch.pio.count = 0; 4520 return 1; 4521 } 4522 4523 return 0; 4524 } 4525 4526 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, 4527 int size, unsigned short port, 4528 const void *val, unsigned int count) 4529 { 4530 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4531 4532 memcpy(vcpu->arch.pio_data, val, size * count); 4533 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); 4534 } 4535 4536 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) 4537 { 4538 return kvm_x86_ops->get_segment_base(vcpu, seg); 4539 } 4540 4541 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) 4542 { 4543 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); 4544 } 4545 4546 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) 4547 { 4548 if (!need_emulate_wbinvd(vcpu)) 4549 return X86EMUL_CONTINUE; 4550 4551 if (kvm_x86_ops->has_wbinvd_exit()) { 4552 int cpu = get_cpu(); 4553 4554 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); 4555 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask, 4556 wbinvd_ipi, NULL, 1); 4557 put_cpu(); 4558 cpumask_clear(vcpu->arch.wbinvd_dirty_mask); 4559 } else 4560 wbinvd(); 4561 return X86EMUL_CONTINUE; 4562 } 4563 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); 4564 4565 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) 4566 { 4567 kvm_emulate_wbinvd(emul_to_vcpu(ctxt)); 4568 } 4569 4570 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest) 4571 { 4572 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); 4573 } 4574 4575 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value) 4576 { 4577 4578 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value); 4579 } 4580 4581 static u64 mk_cr_64(u64 curr_cr, u32 new_val) 4582 { 4583 return (curr_cr & ~((1ULL << 32) - 1)) | new_val; 4584 } 4585 4586 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) 4587 { 4588 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4589 unsigned long value; 4590 4591 switch (cr) { 4592 case 0: 4593 value = kvm_read_cr0(vcpu); 4594 break; 4595 case 2: 4596 value = vcpu->arch.cr2; 4597 break; 4598 case 3: 4599 value = kvm_read_cr3(vcpu); 4600 break; 4601 case 4: 4602 value = kvm_read_cr4(vcpu); 4603 break; 4604 case 8: 4605 value = kvm_get_cr8(vcpu); 4606 break; 4607 default: 4608 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4609 return 0; 4610 } 4611 4612 return value; 4613 } 4614 4615 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) 4616 { 4617 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4618 int res = 0; 4619 4620 switch (cr) { 4621 case 0: 4622 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); 4623 break; 4624 case 2: 4625 vcpu->arch.cr2 = val; 4626 break; 4627 case 3: 4628 res = kvm_set_cr3(vcpu, val); 4629 break; 4630 case 4: 4631 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); 4632 break; 4633 case 8: 4634 res = kvm_set_cr8(vcpu, val); 4635 break; 4636 default: 4637 kvm_err("%s: unexpected cr %u\n", __func__, cr); 4638 res = -1; 4639 } 4640 4641 return res; 4642 } 4643 4644 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val) 4645 { 4646 kvm_set_rflags(emul_to_vcpu(ctxt), val); 4647 } 4648 4649 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) 4650 { 4651 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt)); 4652 } 4653 4654 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4655 { 4656 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt); 4657 } 4658 4659 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4660 { 4661 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt); 4662 } 4663 4664 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4665 { 4666 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt); 4667 } 4668 4669 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) 4670 { 4671 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt); 4672 } 4673 4674 static unsigned long emulator_get_cached_segment_base( 4675 struct x86_emulate_ctxt *ctxt, int seg) 4676 { 4677 return get_segment_base(emul_to_vcpu(ctxt), seg); 4678 } 4679 4680 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, 4681 struct desc_struct *desc, u32 *base3, 4682 int seg) 4683 { 4684 struct kvm_segment var; 4685 4686 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); 4687 *selector = var.selector; 4688 4689 if (var.unusable) { 4690 memset(desc, 0, sizeof(*desc)); 4691 return false; 4692 } 4693 4694 if (var.g) 4695 var.limit >>= 12; 4696 set_desc_limit(desc, var.limit); 4697 set_desc_base(desc, (unsigned long)var.base); 4698 #ifdef CONFIG_X86_64 4699 if (base3) 4700 *base3 = var.base >> 32; 4701 #endif 4702 desc->type = var.type; 4703 desc->s = var.s; 4704 desc->dpl = var.dpl; 4705 desc->p = var.present; 4706 desc->avl = var.avl; 4707 desc->l = var.l; 4708 desc->d = var.db; 4709 desc->g = var.g; 4710 4711 return true; 4712 } 4713 4714 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, 4715 struct desc_struct *desc, u32 base3, 4716 int seg) 4717 { 4718 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 4719 struct kvm_segment var; 4720 4721 var.selector = selector; 4722 var.base = get_desc_base(desc); 4723 #ifdef CONFIG_X86_64 4724 var.base |= ((u64)base3) << 32; 4725 #endif 4726 var.limit = get_desc_limit(desc); 4727 if (desc->g) 4728 var.limit = (var.limit << 12) | 0xfff; 4729 var.type = desc->type; 4730 var.present = desc->p; 4731 var.dpl = desc->dpl; 4732 var.db = desc->d; 4733 var.s = desc->s; 4734 var.l = desc->l; 4735 var.g = desc->g; 4736 var.avl = desc->avl; 4737 var.present = desc->p; 4738 var.unusable = !var.present; 4739 var.padding = 0; 4740 4741 kvm_set_segment(vcpu, &var, seg); 4742 return; 4743 } 4744 4745 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, 4746 u32 msr_index, u64 *pdata) 4747 { 4748 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); 4749 } 4750 4751 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, 4752 u32 msr_index, u64 data) 4753 { 4754 struct msr_data msr; 4755 4756 msr.data = data; 4757 msr.index = msr_index; 4758 msr.host_initiated = false; 4759 return kvm_set_msr(emul_to_vcpu(ctxt), &msr); 4760 } 4761 4762 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, 4763 u32 pmc, u64 *pdata) 4764 { 4765 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata); 4766 } 4767 4768 static void emulator_halt(struct x86_emulate_ctxt *ctxt) 4769 { 4770 emul_to_vcpu(ctxt)->arch.halt_request = 1; 4771 } 4772 4773 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt) 4774 { 4775 preempt_disable(); 4776 kvm_load_guest_fpu(emul_to_vcpu(ctxt)); 4777 /* 4778 * CR0.TS may reference the host fpu state, not the guest fpu state, 4779 * so it may be clear at this point. 4780 */ 4781 clts(); 4782 } 4783 4784 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt) 4785 { 4786 preempt_enable(); 4787 } 4788 4789 static int emulator_intercept(struct x86_emulate_ctxt *ctxt, 4790 struct x86_instruction_info *info, 4791 enum x86_intercept_stage stage) 4792 { 4793 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage); 4794 } 4795 4796 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, 4797 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) 4798 { 4799 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx); 4800 } 4801 4802 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) 4803 { 4804 return kvm_register_read(emul_to_vcpu(ctxt), reg); 4805 } 4806 4807 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) 4808 { 4809 kvm_register_write(emul_to_vcpu(ctxt), reg, val); 4810 } 4811 4812 static const struct x86_emulate_ops emulate_ops = { 4813 .read_gpr = emulator_read_gpr, 4814 .write_gpr = emulator_write_gpr, 4815 .read_std = kvm_read_guest_virt_system, 4816 .write_std = kvm_write_guest_virt_system, 4817 .fetch = kvm_fetch_guest_virt, 4818 .read_emulated = emulator_read_emulated, 4819 .write_emulated = emulator_write_emulated, 4820 .cmpxchg_emulated = emulator_cmpxchg_emulated, 4821 .invlpg = emulator_invlpg, 4822 .pio_in_emulated = emulator_pio_in_emulated, 4823 .pio_out_emulated = emulator_pio_out_emulated, 4824 .get_segment = emulator_get_segment, 4825 .set_segment = emulator_set_segment, 4826 .get_cached_segment_base = emulator_get_cached_segment_base, 4827 .get_gdt = emulator_get_gdt, 4828 .get_idt = emulator_get_idt, 4829 .set_gdt = emulator_set_gdt, 4830 .set_idt = emulator_set_idt, 4831 .get_cr = emulator_get_cr, 4832 .set_cr = emulator_set_cr, 4833 .set_rflags = emulator_set_rflags, 4834 .cpl = emulator_get_cpl, 4835 .get_dr = emulator_get_dr, 4836 .set_dr = emulator_set_dr, 4837 .set_msr = emulator_set_msr, 4838 .get_msr = emulator_get_msr, 4839 .read_pmc = emulator_read_pmc, 4840 .halt = emulator_halt, 4841 .wbinvd = emulator_wbinvd, 4842 .fix_hypercall = emulator_fix_hypercall, 4843 .get_fpu = emulator_get_fpu, 4844 .put_fpu = emulator_put_fpu, 4845 .intercept = emulator_intercept, 4846 .get_cpuid = emulator_get_cpuid, 4847 }; 4848 4849 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) 4850 { 4851 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask); 4852 /* 4853 * an sti; sti; sequence only disable interrupts for the first 4854 * instruction. So, if the last instruction, be it emulated or 4855 * not, left the system with the INT_STI flag enabled, it 4856 * means that the last instruction is an sti. We should not 4857 * leave the flag on in this case. The same goes for mov ss 4858 */ 4859 if (!(int_shadow & mask)) 4860 kvm_x86_ops->set_interrupt_shadow(vcpu, mask); 4861 } 4862 4863 static void inject_emulated_exception(struct kvm_vcpu *vcpu) 4864 { 4865 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 4866 if (ctxt->exception.vector == PF_VECTOR) 4867 kvm_propagate_fault(vcpu, &ctxt->exception); 4868 else if (ctxt->exception.error_code_valid) 4869 kvm_queue_exception_e(vcpu, ctxt->exception.vector, 4870 ctxt->exception.error_code); 4871 else 4872 kvm_queue_exception(vcpu, ctxt->exception.vector); 4873 } 4874 4875 static void init_decode_cache(struct x86_emulate_ctxt *ctxt) 4876 { 4877 memset(&ctxt->opcode_len, 0, 4878 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len); 4879 4880 ctxt->fetch.start = 0; 4881 ctxt->fetch.end = 0; 4882 ctxt->io_read.pos = 0; 4883 ctxt->io_read.end = 0; 4884 ctxt->mem_read.pos = 0; 4885 ctxt->mem_read.end = 0; 4886 } 4887 4888 static void init_emulate_ctxt(struct kvm_vcpu *vcpu) 4889 { 4890 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 4891 int cs_db, cs_l; 4892 4893 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 4894 4895 ctxt->eflags = kvm_get_rflags(vcpu); 4896 ctxt->eip = kvm_rip_read(vcpu); 4897 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : 4898 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : 4899 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : 4900 cs_db ? X86EMUL_MODE_PROT32 : 4901 X86EMUL_MODE_PROT16; 4902 ctxt->guest_mode = is_guest_mode(vcpu); 4903 4904 init_decode_cache(ctxt); 4905 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 4906 } 4907 4908 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) 4909 { 4910 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 4911 int ret; 4912 4913 init_emulate_ctxt(vcpu); 4914 4915 ctxt->op_bytes = 2; 4916 ctxt->ad_bytes = 2; 4917 ctxt->_eip = ctxt->eip + inc_eip; 4918 ret = emulate_int_real(ctxt, irq); 4919 4920 if (ret != X86EMUL_CONTINUE) 4921 return EMULATE_FAIL; 4922 4923 ctxt->eip = ctxt->_eip; 4924 kvm_rip_write(vcpu, ctxt->eip); 4925 kvm_set_rflags(vcpu, ctxt->eflags); 4926 4927 if (irq == NMI_VECTOR) 4928 vcpu->arch.nmi_pending = 0; 4929 else 4930 vcpu->arch.interrupt.pending = false; 4931 4932 return EMULATE_DONE; 4933 } 4934 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); 4935 4936 static int handle_emulation_failure(struct kvm_vcpu *vcpu) 4937 { 4938 int r = EMULATE_DONE; 4939 4940 ++vcpu->stat.insn_emulation_fail; 4941 trace_kvm_emulate_insn_failed(vcpu); 4942 if (!is_guest_mode(vcpu)) { 4943 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 4944 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; 4945 vcpu->run->internal.ndata = 0; 4946 r = EMULATE_FAIL; 4947 } 4948 kvm_queue_exception(vcpu, UD_VECTOR); 4949 4950 return r; 4951 } 4952 4953 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2, 4954 bool write_fault_to_shadow_pgtable, 4955 int emulation_type) 4956 { 4957 gpa_t gpa = cr2; 4958 pfn_t pfn; 4959 4960 if (emulation_type & EMULTYPE_NO_REEXECUTE) 4961 return false; 4962 4963 if (!vcpu->arch.mmu.direct_map) { 4964 /* 4965 * Write permission should be allowed since only 4966 * write access need to be emulated. 4967 */ 4968 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 4969 4970 /* 4971 * If the mapping is invalid in guest, let cpu retry 4972 * it to generate fault. 4973 */ 4974 if (gpa == UNMAPPED_GVA) 4975 return true; 4976 } 4977 4978 /* 4979 * Do not retry the unhandleable instruction if it faults on the 4980 * readonly host memory, otherwise it will goto a infinite loop: 4981 * retry instruction -> write #PF -> emulation fail -> retry 4982 * instruction -> ... 4983 */ 4984 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); 4985 4986 /* 4987 * If the instruction failed on the error pfn, it can not be fixed, 4988 * report the error to userspace. 4989 */ 4990 if (is_error_noslot_pfn(pfn)) 4991 return false; 4992 4993 kvm_release_pfn_clean(pfn); 4994 4995 /* The instructions are well-emulated on direct mmu. */ 4996 if (vcpu->arch.mmu.direct_map) { 4997 unsigned int indirect_shadow_pages; 4998 4999 spin_lock(&vcpu->kvm->mmu_lock); 5000 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; 5001 spin_unlock(&vcpu->kvm->mmu_lock); 5002 5003 if (indirect_shadow_pages) 5004 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5005 5006 return true; 5007 } 5008 5009 /* 5010 * if emulation was due to access to shadowed page table 5011 * and it failed try to unshadow page and re-enter the 5012 * guest to let CPU execute the instruction. 5013 */ 5014 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5015 5016 /* 5017 * If the access faults on its page table, it can not 5018 * be fixed by unprotecting shadow page and it should 5019 * be reported to userspace. 5020 */ 5021 return !write_fault_to_shadow_pgtable; 5022 } 5023 5024 static bool retry_instruction(struct x86_emulate_ctxt *ctxt, 5025 unsigned long cr2, int emulation_type) 5026 { 5027 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5028 unsigned long last_retry_eip, last_retry_addr, gpa = cr2; 5029 5030 last_retry_eip = vcpu->arch.last_retry_eip; 5031 last_retry_addr = vcpu->arch.last_retry_addr; 5032 5033 /* 5034 * If the emulation is caused by #PF and it is non-page_table 5035 * writing instruction, it means the VM-EXIT is caused by shadow 5036 * page protected, we can zap the shadow page and retry this 5037 * instruction directly. 5038 * 5039 * Note: if the guest uses a non-page-table modifying instruction 5040 * on the PDE that points to the instruction, then we will unmap 5041 * the instruction and go to an infinite loop. So, we cache the 5042 * last retried eip and the last fault address, if we meet the eip 5043 * and the address again, we can break out of the potential infinite 5044 * loop. 5045 */ 5046 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; 5047 5048 if (!(emulation_type & EMULTYPE_RETRY)) 5049 return false; 5050 5051 if (x86_page_table_writing_insn(ctxt)) 5052 return false; 5053 5054 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2) 5055 return false; 5056 5057 vcpu->arch.last_retry_eip = ctxt->eip; 5058 vcpu->arch.last_retry_addr = cr2; 5059 5060 if (!vcpu->arch.mmu.direct_map) 5061 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL); 5062 5063 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); 5064 5065 return true; 5066 } 5067 5068 static int complete_emulated_mmio(struct kvm_vcpu *vcpu); 5069 static int complete_emulated_pio(struct kvm_vcpu *vcpu); 5070 5071 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, 5072 unsigned long *db) 5073 { 5074 u32 dr6 = 0; 5075 int i; 5076 u32 enable, rwlen; 5077 5078 enable = dr7; 5079 rwlen = dr7 >> 16; 5080 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) 5081 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) 5082 dr6 |= (1 << i); 5083 return dr6; 5084 } 5085 5086 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r) 5087 { 5088 struct kvm_run *kvm_run = vcpu->run; 5089 5090 /* 5091 * Use the "raw" value to see if TF was passed to the processor. 5092 * Note that the new value of the flags has not been saved yet. 5093 * 5094 * This is correct even for TF set by the guest, because "the 5095 * processor will not generate this exception after the instruction 5096 * that sets the TF flag". 5097 */ 5098 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu); 5099 5100 if (unlikely(rflags & X86_EFLAGS_TF)) { 5101 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { 5102 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1; 5103 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip; 5104 kvm_run->debug.arch.exception = DB_VECTOR; 5105 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5106 *r = EMULATE_USER_EXIT; 5107 } else { 5108 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF; 5109 /* 5110 * "Certain debug exceptions may clear bit 0-3. The 5111 * remaining contents of the DR6 register are never 5112 * cleared by the processor". 5113 */ 5114 vcpu->arch.dr6 &= ~15; 5115 vcpu->arch.dr6 |= DR6_BS; 5116 kvm_queue_exception(vcpu, DB_VECTOR); 5117 } 5118 } 5119 } 5120 5121 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r) 5122 { 5123 struct kvm_run *kvm_run = vcpu->run; 5124 unsigned long eip = vcpu->arch.emulate_ctxt.eip; 5125 u32 dr6 = 0; 5126 5127 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && 5128 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { 5129 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5130 vcpu->arch.guest_debug_dr7, 5131 vcpu->arch.eff_db); 5132 5133 if (dr6 != 0) { 5134 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; 5135 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) + 5136 get_segment_base(vcpu, VCPU_SREG_CS); 5137 5138 kvm_run->debug.arch.exception = DB_VECTOR; 5139 kvm_run->exit_reason = KVM_EXIT_DEBUG; 5140 *r = EMULATE_USER_EXIT; 5141 return true; 5142 } 5143 } 5144 5145 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) { 5146 dr6 = kvm_vcpu_check_hw_bp(eip, 0, 5147 vcpu->arch.dr7, 5148 vcpu->arch.db); 5149 5150 if (dr6 != 0) { 5151 vcpu->arch.dr6 &= ~15; 5152 vcpu->arch.dr6 |= dr6; 5153 kvm_queue_exception(vcpu, DB_VECTOR); 5154 *r = EMULATE_DONE; 5155 return true; 5156 } 5157 } 5158 5159 return false; 5160 } 5161 5162 int x86_emulate_instruction(struct kvm_vcpu *vcpu, 5163 unsigned long cr2, 5164 int emulation_type, 5165 void *insn, 5166 int insn_len) 5167 { 5168 int r; 5169 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 5170 bool writeback = true; 5171 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; 5172 5173 /* 5174 * Clear write_fault_to_shadow_pgtable here to ensure it is 5175 * never reused. 5176 */ 5177 vcpu->arch.write_fault_to_shadow_pgtable = false; 5178 kvm_clear_exception_queue(vcpu); 5179 5180 if (!(emulation_type & EMULTYPE_NO_DECODE)) { 5181 init_emulate_ctxt(vcpu); 5182 5183 /* 5184 * We will reenter on the same instruction since 5185 * we do not set complete_userspace_io. This does not 5186 * handle watchpoints yet, those would be handled in 5187 * the emulate_ops. 5188 */ 5189 if (kvm_vcpu_check_breakpoint(vcpu, &r)) 5190 return r; 5191 5192 ctxt->interruptibility = 0; 5193 ctxt->have_exception = false; 5194 ctxt->perm_ok = false; 5195 5196 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD; 5197 5198 r = x86_decode_insn(ctxt, insn, insn_len); 5199 5200 trace_kvm_emulate_insn_start(vcpu); 5201 ++vcpu->stat.insn_emulation; 5202 if (r != EMULATION_OK) { 5203 if (emulation_type & EMULTYPE_TRAP_UD) 5204 return EMULATE_FAIL; 5205 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5206 emulation_type)) 5207 return EMULATE_DONE; 5208 if (emulation_type & EMULTYPE_SKIP) 5209 return EMULATE_FAIL; 5210 return handle_emulation_failure(vcpu); 5211 } 5212 } 5213 5214 if (emulation_type & EMULTYPE_SKIP) { 5215 kvm_rip_write(vcpu, ctxt->_eip); 5216 return EMULATE_DONE; 5217 } 5218 5219 if (retry_instruction(ctxt, cr2, emulation_type)) 5220 return EMULATE_DONE; 5221 5222 /* this is needed for vmware backdoor interface to work since it 5223 changes registers values during IO operation */ 5224 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { 5225 vcpu->arch.emulate_regs_need_sync_from_vcpu = false; 5226 emulator_invalidate_register_cache(ctxt); 5227 } 5228 5229 restart: 5230 r = x86_emulate_insn(ctxt); 5231 5232 if (r == EMULATION_INTERCEPTED) 5233 return EMULATE_DONE; 5234 5235 if (r == EMULATION_FAILED) { 5236 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt, 5237 emulation_type)) 5238 return EMULATE_DONE; 5239 5240 return handle_emulation_failure(vcpu); 5241 } 5242 5243 if (ctxt->have_exception) { 5244 inject_emulated_exception(vcpu); 5245 r = EMULATE_DONE; 5246 } else if (vcpu->arch.pio.count) { 5247 if (!vcpu->arch.pio.in) { 5248 /* FIXME: return into emulator if single-stepping. */ 5249 vcpu->arch.pio.count = 0; 5250 } else { 5251 writeback = false; 5252 vcpu->arch.complete_userspace_io = complete_emulated_pio; 5253 } 5254 r = EMULATE_USER_EXIT; 5255 } else if (vcpu->mmio_needed) { 5256 if (!vcpu->mmio_is_write) 5257 writeback = false; 5258 r = EMULATE_USER_EXIT; 5259 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 5260 } else if (r == EMULATION_RESTART) 5261 goto restart; 5262 else 5263 r = EMULATE_DONE; 5264 5265 if (writeback) { 5266 toggle_interruptibility(vcpu, ctxt->interruptibility); 5267 kvm_make_request(KVM_REQ_EVENT, vcpu); 5268 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 5269 kvm_rip_write(vcpu, ctxt->eip); 5270 if (r == EMULATE_DONE) 5271 kvm_vcpu_check_singlestep(vcpu, &r); 5272 kvm_set_rflags(vcpu, ctxt->eflags); 5273 } else 5274 vcpu->arch.emulate_regs_need_sync_to_vcpu = true; 5275 5276 return r; 5277 } 5278 EXPORT_SYMBOL_GPL(x86_emulate_instruction); 5279 5280 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port) 5281 { 5282 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX); 5283 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt, 5284 size, port, &val, 1); 5285 /* do not return to emulator after return from userspace */ 5286 vcpu->arch.pio.count = 0; 5287 return ret; 5288 } 5289 EXPORT_SYMBOL_GPL(kvm_fast_pio_out); 5290 5291 static void tsc_bad(void *info) 5292 { 5293 __this_cpu_write(cpu_tsc_khz, 0); 5294 } 5295 5296 static void tsc_khz_changed(void *data) 5297 { 5298 struct cpufreq_freqs *freq = data; 5299 unsigned long khz = 0; 5300 5301 if (data) 5302 khz = freq->new; 5303 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5304 khz = cpufreq_quick_get(raw_smp_processor_id()); 5305 if (!khz) 5306 khz = tsc_khz; 5307 __this_cpu_write(cpu_tsc_khz, khz); 5308 } 5309 5310 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 5311 void *data) 5312 { 5313 struct cpufreq_freqs *freq = data; 5314 struct kvm *kvm; 5315 struct kvm_vcpu *vcpu; 5316 int i, send_ipi = 0; 5317 5318 /* 5319 * We allow guests to temporarily run on slowing clocks, 5320 * provided we notify them after, or to run on accelerating 5321 * clocks, provided we notify them before. Thus time never 5322 * goes backwards. 5323 * 5324 * However, we have a problem. We can't atomically update 5325 * the frequency of a given CPU from this function; it is 5326 * merely a notifier, which can be called from any CPU. 5327 * Changing the TSC frequency at arbitrary points in time 5328 * requires a recomputation of local variables related to 5329 * the TSC for each VCPU. We must flag these local variables 5330 * to be updated and be sure the update takes place with the 5331 * new frequency before any guests proceed. 5332 * 5333 * Unfortunately, the combination of hotplug CPU and frequency 5334 * change creates an intractable locking scenario; the order 5335 * of when these callouts happen is undefined with respect to 5336 * CPU hotplug, and they can race with each other. As such, 5337 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is 5338 * undefined; you can actually have a CPU frequency change take 5339 * place in between the computation of X and the setting of the 5340 * variable. To protect against this problem, all updates of 5341 * the per_cpu tsc_khz variable are done in an interrupt 5342 * protected IPI, and all callers wishing to update the value 5343 * must wait for a synchronous IPI to complete (which is trivial 5344 * if the caller is on the CPU already). This establishes the 5345 * necessary total order on variable updates. 5346 * 5347 * Note that because a guest time update may take place 5348 * anytime after the setting of the VCPU's request bit, the 5349 * correct TSC value must be set before the request. However, 5350 * to ensure the update actually makes it to any guest which 5351 * starts running in hardware virtualization between the set 5352 * and the acquisition of the spinlock, we must also ping the 5353 * CPU after setting the request bit. 5354 * 5355 */ 5356 5357 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) 5358 return 0; 5359 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) 5360 return 0; 5361 5362 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5363 5364 spin_lock(&kvm_lock); 5365 list_for_each_entry(kvm, &vm_list, vm_list) { 5366 kvm_for_each_vcpu(i, vcpu, kvm) { 5367 if (vcpu->cpu != freq->cpu) 5368 continue; 5369 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 5370 if (vcpu->cpu != smp_processor_id()) 5371 send_ipi = 1; 5372 } 5373 } 5374 spin_unlock(&kvm_lock); 5375 5376 if (freq->old < freq->new && send_ipi) { 5377 /* 5378 * We upscale the frequency. Must make the guest 5379 * doesn't see old kvmclock values while running with 5380 * the new frequency, otherwise we risk the guest sees 5381 * time go backwards. 5382 * 5383 * In case we update the frequency for another cpu 5384 * (which might be in guest context) send an interrupt 5385 * to kick the cpu out of guest context. Next time 5386 * guest context is entered kvmclock will be updated, 5387 * so the guest will not see stale values. 5388 */ 5389 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1); 5390 } 5391 return 0; 5392 } 5393 5394 static struct notifier_block kvmclock_cpufreq_notifier_block = { 5395 .notifier_call = kvmclock_cpufreq_notifier 5396 }; 5397 5398 static int kvmclock_cpu_notifier(struct notifier_block *nfb, 5399 unsigned long action, void *hcpu) 5400 { 5401 unsigned int cpu = (unsigned long)hcpu; 5402 5403 switch (action) { 5404 case CPU_ONLINE: 5405 case CPU_DOWN_FAILED: 5406 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5407 break; 5408 case CPU_DOWN_PREPARE: 5409 smp_call_function_single(cpu, tsc_bad, NULL, 1); 5410 break; 5411 } 5412 return NOTIFY_OK; 5413 } 5414 5415 static struct notifier_block kvmclock_cpu_notifier_block = { 5416 .notifier_call = kvmclock_cpu_notifier, 5417 .priority = -INT_MAX 5418 }; 5419 5420 static void kvm_timer_init(void) 5421 { 5422 int cpu; 5423 5424 max_tsc_khz = tsc_khz; 5425 5426 cpu_notifier_register_begin(); 5427 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { 5428 #ifdef CONFIG_CPU_FREQ 5429 struct cpufreq_policy policy; 5430 memset(&policy, 0, sizeof(policy)); 5431 cpu = get_cpu(); 5432 cpufreq_get_policy(&policy, cpu); 5433 if (policy.cpuinfo.max_freq) 5434 max_tsc_khz = policy.cpuinfo.max_freq; 5435 put_cpu(); 5436 #endif 5437 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, 5438 CPUFREQ_TRANSITION_NOTIFIER); 5439 } 5440 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz); 5441 for_each_online_cpu(cpu) 5442 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1); 5443 5444 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5445 cpu_notifier_register_done(); 5446 5447 } 5448 5449 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu); 5450 5451 int kvm_is_in_guest(void) 5452 { 5453 return __this_cpu_read(current_vcpu) != NULL; 5454 } 5455 5456 static int kvm_is_user_mode(void) 5457 { 5458 int user_mode = 3; 5459 5460 if (__this_cpu_read(current_vcpu)) 5461 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu)); 5462 5463 return user_mode != 0; 5464 } 5465 5466 static unsigned long kvm_get_guest_ip(void) 5467 { 5468 unsigned long ip = 0; 5469 5470 if (__this_cpu_read(current_vcpu)) 5471 ip = kvm_rip_read(__this_cpu_read(current_vcpu)); 5472 5473 return ip; 5474 } 5475 5476 static struct perf_guest_info_callbacks kvm_guest_cbs = { 5477 .is_in_guest = kvm_is_in_guest, 5478 .is_user_mode = kvm_is_user_mode, 5479 .get_guest_ip = kvm_get_guest_ip, 5480 }; 5481 5482 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu) 5483 { 5484 __this_cpu_write(current_vcpu, vcpu); 5485 } 5486 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi); 5487 5488 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu) 5489 { 5490 __this_cpu_write(current_vcpu, NULL); 5491 } 5492 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi); 5493 5494 static void kvm_set_mmio_spte_mask(void) 5495 { 5496 u64 mask; 5497 int maxphyaddr = boot_cpu_data.x86_phys_bits; 5498 5499 /* 5500 * Set the reserved bits and the present bit of an paging-structure 5501 * entry to generate page fault with PFER.RSV = 1. 5502 */ 5503 /* Mask the reserved physical address bits. */ 5504 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr; 5505 5506 /* Bit 62 is always reserved for 32bit host. */ 5507 mask |= 0x3ull << 62; 5508 5509 /* Set the present bit. */ 5510 mask |= 1ull; 5511 5512 #ifdef CONFIG_X86_64 5513 /* 5514 * If reserved bit is not supported, clear the present bit to disable 5515 * mmio page fault. 5516 */ 5517 if (maxphyaddr == 52) 5518 mask &= ~1ull; 5519 #endif 5520 5521 kvm_mmu_set_mmio_spte_mask(mask); 5522 } 5523 5524 #ifdef CONFIG_X86_64 5525 static void pvclock_gtod_update_fn(struct work_struct *work) 5526 { 5527 struct kvm *kvm; 5528 5529 struct kvm_vcpu *vcpu; 5530 int i; 5531 5532 spin_lock(&kvm_lock); 5533 list_for_each_entry(kvm, &vm_list, vm_list) 5534 kvm_for_each_vcpu(i, vcpu, kvm) 5535 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests); 5536 atomic_set(&kvm_guest_has_master_clock, 0); 5537 spin_unlock(&kvm_lock); 5538 } 5539 5540 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); 5541 5542 /* 5543 * Notification about pvclock gtod data update. 5544 */ 5545 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, 5546 void *priv) 5547 { 5548 struct pvclock_gtod_data *gtod = &pvclock_gtod_data; 5549 struct timekeeper *tk = priv; 5550 5551 update_pvclock_gtod(tk); 5552 5553 /* disable master clock if host does not trust, or does not 5554 * use, TSC clocksource 5555 */ 5556 if (gtod->clock.vclock_mode != VCLOCK_TSC && 5557 atomic_read(&kvm_guest_has_master_clock) != 0) 5558 queue_work(system_long_wq, &pvclock_gtod_work); 5559 5560 return 0; 5561 } 5562 5563 static struct notifier_block pvclock_gtod_notifier = { 5564 .notifier_call = pvclock_gtod_notify, 5565 }; 5566 #endif 5567 5568 int kvm_arch_init(void *opaque) 5569 { 5570 int r; 5571 struct kvm_x86_ops *ops = opaque; 5572 5573 if (kvm_x86_ops) { 5574 printk(KERN_ERR "kvm: already loaded the other module\n"); 5575 r = -EEXIST; 5576 goto out; 5577 } 5578 5579 if (!ops->cpu_has_kvm_support()) { 5580 printk(KERN_ERR "kvm: no hardware support\n"); 5581 r = -EOPNOTSUPP; 5582 goto out; 5583 } 5584 if (ops->disabled_by_bios()) { 5585 printk(KERN_ERR "kvm: disabled by bios\n"); 5586 r = -EOPNOTSUPP; 5587 goto out; 5588 } 5589 5590 r = -ENOMEM; 5591 shared_msrs = alloc_percpu(struct kvm_shared_msrs); 5592 if (!shared_msrs) { 5593 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n"); 5594 goto out; 5595 } 5596 5597 r = kvm_mmu_module_init(); 5598 if (r) 5599 goto out_free_percpu; 5600 5601 kvm_set_mmio_spte_mask(); 5602 5603 kvm_x86_ops = ops; 5604 kvm_init_msr_list(); 5605 5606 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, 5607 PT_DIRTY_MASK, PT64_NX_MASK, 0); 5608 5609 kvm_timer_init(); 5610 5611 perf_register_guest_info_callbacks(&kvm_guest_cbs); 5612 5613 if (cpu_has_xsave) 5614 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); 5615 5616 kvm_lapic_init(); 5617 #ifdef CONFIG_X86_64 5618 pvclock_gtod_register_notifier(&pvclock_gtod_notifier); 5619 #endif 5620 5621 return 0; 5622 5623 out_free_percpu: 5624 free_percpu(shared_msrs); 5625 out: 5626 return r; 5627 } 5628 5629 void kvm_arch_exit(void) 5630 { 5631 perf_unregister_guest_info_callbacks(&kvm_guest_cbs); 5632 5633 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 5634 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, 5635 CPUFREQ_TRANSITION_NOTIFIER); 5636 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block); 5637 #ifdef CONFIG_X86_64 5638 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); 5639 #endif 5640 kvm_x86_ops = NULL; 5641 kvm_mmu_module_exit(); 5642 free_percpu(shared_msrs); 5643 } 5644 5645 int kvm_emulate_halt(struct kvm_vcpu *vcpu) 5646 { 5647 ++vcpu->stat.halt_exits; 5648 if (irqchip_in_kernel(vcpu->kvm)) { 5649 vcpu->arch.mp_state = KVM_MP_STATE_HALTED; 5650 return 1; 5651 } else { 5652 vcpu->run->exit_reason = KVM_EXIT_HLT; 5653 return 0; 5654 } 5655 } 5656 EXPORT_SYMBOL_GPL(kvm_emulate_halt); 5657 5658 int kvm_hv_hypercall(struct kvm_vcpu *vcpu) 5659 { 5660 u64 param, ingpa, outgpa, ret; 5661 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0; 5662 bool fast, longmode; 5663 int cs_db, cs_l; 5664 5665 /* 5666 * hypercall generates UD from non zero cpl and real mode 5667 * per HYPER-V spec 5668 */ 5669 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) { 5670 kvm_queue_exception(vcpu, UD_VECTOR); 5671 return 0; 5672 } 5673 5674 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); 5675 longmode = is_long_mode(vcpu) && cs_l == 1; 5676 5677 if (!longmode) { 5678 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) | 5679 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff); 5680 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) | 5681 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff); 5682 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) | 5683 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff); 5684 } 5685 #ifdef CONFIG_X86_64 5686 else { 5687 param = kvm_register_read(vcpu, VCPU_REGS_RCX); 5688 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX); 5689 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8); 5690 } 5691 #endif 5692 5693 code = param & 0xffff; 5694 fast = (param >> 16) & 0x1; 5695 rep_cnt = (param >> 32) & 0xfff; 5696 rep_idx = (param >> 48) & 0xfff; 5697 5698 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa); 5699 5700 switch (code) { 5701 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT: 5702 kvm_vcpu_on_spin(vcpu); 5703 break; 5704 default: 5705 res = HV_STATUS_INVALID_HYPERCALL_CODE; 5706 break; 5707 } 5708 5709 ret = res | (((u64)rep_done & 0xfff) << 32); 5710 if (longmode) { 5711 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 5712 } else { 5713 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32); 5714 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff); 5715 } 5716 5717 return 1; 5718 } 5719 5720 /* 5721 * kvm_pv_kick_cpu_op: Kick a vcpu. 5722 * 5723 * @apicid - apicid of vcpu to be kicked. 5724 */ 5725 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid) 5726 { 5727 struct kvm_lapic_irq lapic_irq; 5728 5729 lapic_irq.shorthand = 0; 5730 lapic_irq.dest_mode = 0; 5731 lapic_irq.dest_id = apicid; 5732 5733 lapic_irq.delivery_mode = APIC_DM_REMRD; 5734 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL); 5735 } 5736 5737 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) 5738 { 5739 unsigned long nr, a0, a1, a2, a3, ret; 5740 int r = 1; 5741 5742 if (kvm_hv_hypercall_enabled(vcpu->kvm)) 5743 return kvm_hv_hypercall(vcpu); 5744 5745 nr = kvm_register_read(vcpu, VCPU_REGS_RAX); 5746 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); 5747 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); 5748 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); 5749 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); 5750 5751 trace_kvm_hypercall(nr, a0, a1, a2, a3); 5752 5753 if (!is_long_mode(vcpu)) { 5754 nr &= 0xFFFFFFFF; 5755 a0 &= 0xFFFFFFFF; 5756 a1 &= 0xFFFFFFFF; 5757 a2 &= 0xFFFFFFFF; 5758 a3 &= 0xFFFFFFFF; 5759 } 5760 5761 if (kvm_x86_ops->get_cpl(vcpu) != 0) { 5762 ret = -KVM_EPERM; 5763 goto out; 5764 } 5765 5766 switch (nr) { 5767 case KVM_HC_VAPIC_POLL_IRQ: 5768 ret = 0; 5769 break; 5770 case KVM_HC_KICK_CPU: 5771 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); 5772 ret = 0; 5773 break; 5774 default: 5775 ret = -KVM_ENOSYS; 5776 break; 5777 } 5778 out: 5779 kvm_register_write(vcpu, VCPU_REGS_RAX, ret); 5780 ++vcpu->stat.hypercalls; 5781 return r; 5782 } 5783 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); 5784 5785 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) 5786 { 5787 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); 5788 char instruction[3]; 5789 unsigned long rip = kvm_rip_read(vcpu); 5790 5791 kvm_x86_ops->patch_hypercall(vcpu, instruction); 5792 5793 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL); 5794 } 5795 5796 /* 5797 * Check if userspace requested an interrupt window, and that the 5798 * interrupt window is open. 5799 * 5800 * No need to exit to userspace if we already have an interrupt queued. 5801 */ 5802 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) 5803 { 5804 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && 5805 vcpu->run->request_interrupt_window && 5806 kvm_arch_interrupt_allowed(vcpu)); 5807 } 5808 5809 static void post_kvm_run_save(struct kvm_vcpu *vcpu) 5810 { 5811 struct kvm_run *kvm_run = vcpu->run; 5812 5813 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; 5814 kvm_run->cr8 = kvm_get_cr8(vcpu); 5815 kvm_run->apic_base = kvm_get_apic_base(vcpu); 5816 if (irqchip_in_kernel(vcpu->kvm)) 5817 kvm_run->ready_for_interrupt_injection = 1; 5818 else 5819 kvm_run->ready_for_interrupt_injection = 5820 kvm_arch_interrupt_allowed(vcpu) && 5821 !kvm_cpu_has_interrupt(vcpu) && 5822 !kvm_event_needs_reinjection(vcpu); 5823 } 5824 5825 static void update_cr8_intercept(struct kvm_vcpu *vcpu) 5826 { 5827 int max_irr, tpr; 5828 5829 if (!kvm_x86_ops->update_cr8_intercept) 5830 return; 5831 5832 if (!vcpu->arch.apic) 5833 return; 5834 5835 if (!vcpu->arch.apic->vapic_addr) 5836 max_irr = kvm_lapic_find_highest_irr(vcpu); 5837 else 5838 max_irr = -1; 5839 5840 if (max_irr != -1) 5841 max_irr >>= 4; 5842 5843 tpr = kvm_lapic_get_cr8(vcpu); 5844 5845 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); 5846 } 5847 5848 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win) 5849 { 5850 int r; 5851 5852 /* try to reinject previous events if any */ 5853 if (vcpu->arch.exception.pending) { 5854 trace_kvm_inj_exception(vcpu->arch.exception.nr, 5855 vcpu->arch.exception.has_error_code, 5856 vcpu->arch.exception.error_code); 5857 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, 5858 vcpu->arch.exception.has_error_code, 5859 vcpu->arch.exception.error_code, 5860 vcpu->arch.exception.reinject); 5861 return 0; 5862 } 5863 5864 if (vcpu->arch.nmi_injected) { 5865 kvm_x86_ops->set_nmi(vcpu); 5866 return 0; 5867 } 5868 5869 if (vcpu->arch.interrupt.pending) { 5870 kvm_x86_ops->set_irq(vcpu); 5871 return 0; 5872 } 5873 5874 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) { 5875 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win); 5876 if (r != 0) 5877 return r; 5878 } 5879 5880 /* try to inject new event if pending */ 5881 if (vcpu->arch.nmi_pending) { 5882 if (kvm_x86_ops->nmi_allowed(vcpu)) { 5883 --vcpu->arch.nmi_pending; 5884 vcpu->arch.nmi_injected = true; 5885 kvm_x86_ops->set_nmi(vcpu); 5886 } 5887 } else if (kvm_cpu_has_injectable_intr(vcpu)) { 5888 if (kvm_x86_ops->interrupt_allowed(vcpu)) { 5889 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), 5890 false); 5891 kvm_x86_ops->set_irq(vcpu); 5892 } 5893 } 5894 return 0; 5895 } 5896 5897 static void process_nmi(struct kvm_vcpu *vcpu) 5898 { 5899 unsigned limit = 2; 5900 5901 /* 5902 * x86 is limited to one NMI running, and one NMI pending after it. 5903 * If an NMI is already in progress, limit further NMIs to just one. 5904 * Otherwise, allow two (and we'll inject the first one immediately). 5905 */ 5906 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected) 5907 limit = 1; 5908 5909 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); 5910 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); 5911 kvm_make_request(KVM_REQ_EVENT, vcpu); 5912 } 5913 5914 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) 5915 { 5916 u64 eoi_exit_bitmap[4]; 5917 u32 tmr[8]; 5918 5919 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 5920 return; 5921 5922 memset(eoi_exit_bitmap, 0, 32); 5923 memset(tmr, 0, 32); 5924 5925 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr); 5926 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap); 5927 kvm_apic_update_tmr(vcpu, tmr); 5928 } 5929 5930 /* 5931 * Returns 1 to let __vcpu_run() continue the guest execution loop without 5932 * exiting to the userspace. Otherwise, the value will be returned to the 5933 * userspace. 5934 */ 5935 static int vcpu_enter_guest(struct kvm_vcpu *vcpu) 5936 { 5937 int r; 5938 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && 5939 vcpu->run->request_interrupt_window; 5940 bool req_immediate_exit = false; 5941 5942 if (vcpu->requests) { 5943 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) 5944 kvm_mmu_unload(vcpu); 5945 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) 5946 __kvm_migrate_timers(vcpu); 5947 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) 5948 kvm_gen_update_masterclock(vcpu->kvm); 5949 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) 5950 kvm_gen_kvmclock_update(vcpu); 5951 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { 5952 r = kvm_guest_time_update(vcpu); 5953 if (unlikely(r)) 5954 goto out; 5955 } 5956 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) 5957 kvm_mmu_sync_roots(vcpu); 5958 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 5959 kvm_x86_ops->tlb_flush(vcpu); 5960 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { 5961 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; 5962 r = 0; 5963 goto out; 5964 } 5965 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { 5966 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 5967 r = 0; 5968 goto out; 5969 } 5970 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) { 5971 vcpu->fpu_active = 0; 5972 kvm_x86_ops->fpu_deactivate(vcpu); 5973 } 5974 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { 5975 /* Page is swapped out. Do synthetic halt */ 5976 vcpu->arch.apf.halted = true; 5977 r = 1; 5978 goto out; 5979 } 5980 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 5981 record_steal_time(vcpu); 5982 if (kvm_check_request(KVM_REQ_NMI, vcpu)) 5983 process_nmi(vcpu); 5984 if (kvm_check_request(KVM_REQ_PMU, vcpu)) 5985 kvm_handle_pmu_event(vcpu); 5986 if (kvm_check_request(KVM_REQ_PMI, vcpu)) 5987 kvm_deliver_pmi(vcpu); 5988 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) 5989 vcpu_scan_ioapic(vcpu); 5990 } 5991 5992 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) { 5993 kvm_apic_accept_events(vcpu); 5994 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 5995 r = 1; 5996 goto out; 5997 } 5998 5999 if (inject_pending_event(vcpu, req_int_win) != 0) 6000 req_immediate_exit = true; 6001 /* enable NMI/IRQ window open exits if needed */ 6002 else if (vcpu->arch.nmi_pending) 6003 kvm_x86_ops->enable_nmi_window(vcpu); 6004 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win) 6005 kvm_x86_ops->enable_irq_window(vcpu); 6006 6007 if (kvm_lapic_enabled(vcpu)) { 6008 /* 6009 * Update architecture specific hints for APIC 6010 * virtual interrupt delivery. 6011 */ 6012 if (kvm_x86_ops->hwapic_irr_update) 6013 kvm_x86_ops->hwapic_irr_update(vcpu, 6014 kvm_lapic_find_highest_irr(vcpu)); 6015 update_cr8_intercept(vcpu); 6016 kvm_lapic_sync_to_vapic(vcpu); 6017 } 6018 } 6019 6020 r = kvm_mmu_reload(vcpu); 6021 if (unlikely(r)) { 6022 goto cancel_injection; 6023 } 6024 6025 preempt_disable(); 6026 6027 kvm_x86_ops->prepare_guest_switch(vcpu); 6028 if (vcpu->fpu_active) 6029 kvm_load_guest_fpu(vcpu); 6030 kvm_load_guest_xcr0(vcpu); 6031 6032 vcpu->mode = IN_GUEST_MODE; 6033 6034 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6035 6036 /* We should set ->mode before check ->requests, 6037 * see the comment in make_all_cpus_request. 6038 */ 6039 smp_mb__after_srcu_read_unlock(); 6040 6041 local_irq_disable(); 6042 6043 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests 6044 || need_resched() || signal_pending(current)) { 6045 vcpu->mode = OUTSIDE_GUEST_MODE; 6046 smp_wmb(); 6047 local_irq_enable(); 6048 preempt_enable(); 6049 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6050 r = 1; 6051 goto cancel_injection; 6052 } 6053 6054 if (req_immediate_exit) 6055 smp_send_reschedule(vcpu->cpu); 6056 6057 kvm_guest_enter(); 6058 6059 if (unlikely(vcpu->arch.switch_db_regs)) { 6060 set_debugreg(0, 7); 6061 set_debugreg(vcpu->arch.eff_db[0], 0); 6062 set_debugreg(vcpu->arch.eff_db[1], 1); 6063 set_debugreg(vcpu->arch.eff_db[2], 2); 6064 set_debugreg(vcpu->arch.eff_db[3], 3); 6065 set_debugreg(vcpu->arch.dr6, 6); 6066 } 6067 6068 trace_kvm_entry(vcpu->vcpu_id); 6069 kvm_x86_ops->run(vcpu); 6070 6071 /* 6072 * Do this here before restoring debug registers on the host. And 6073 * since we do this before handling the vmexit, a DR access vmexit 6074 * can (a) read the correct value of the debug registers, (b) set 6075 * KVM_DEBUGREG_WONT_EXIT again. 6076 */ 6077 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { 6078 int i; 6079 6080 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); 6081 kvm_x86_ops->sync_dirty_debug_regs(vcpu); 6082 for (i = 0; i < KVM_NR_DB_REGS; i++) 6083 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 6084 } 6085 6086 /* 6087 * If the guest has used debug registers, at least dr7 6088 * will be disabled while returning to the host. 6089 * If we don't have active breakpoints in the host, we don't 6090 * care about the messed up debug address registers. But if 6091 * we have some of them active, restore the old state. 6092 */ 6093 if (hw_breakpoint_active()) 6094 hw_breakpoint_restore(); 6095 6096 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, 6097 native_read_tsc()); 6098 6099 vcpu->mode = OUTSIDE_GUEST_MODE; 6100 smp_wmb(); 6101 6102 /* Interrupt is enabled by handle_external_intr() */ 6103 kvm_x86_ops->handle_external_intr(vcpu); 6104 6105 ++vcpu->stat.exits; 6106 6107 /* 6108 * We must have an instruction between local_irq_enable() and 6109 * kvm_guest_exit(), so the timer interrupt isn't delayed by 6110 * the interrupt shadow. The stat.exits increment will do nicely. 6111 * But we need to prevent reordering, hence this barrier(): 6112 */ 6113 barrier(); 6114 6115 kvm_guest_exit(); 6116 6117 preempt_enable(); 6118 6119 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6120 6121 /* 6122 * Profile KVM exit RIPs: 6123 */ 6124 if (unlikely(prof_on == KVM_PROFILING)) { 6125 unsigned long rip = kvm_rip_read(vcpu); 6126 profile_hit(KVM_PROFILING, (void *)rip); 6127 } 6128 6129 if (unlikely(vcpu->arch.tsc_always_catchup)) 6130 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); 6131 6132 if (vcpu->arch.apic_attention) 6133 kvm_lapic_sync_from_vapic(vcpu); 6134 6135 r = kvm_x86_ops->handle_exit(vcpu); 6136 return r; 6137 6138 cancel_injection: 6139 kvm_x86_ops->cancel_injection(vcpu); 6140 if (unlikely(vcpu->arch.apic_attention)) 6141 kvm_lapic_sync_from_vapic(vcpu); 6142 out: 6143 return r; 6144 } 6145 6146 6147 static int __vcpu_run(struct kvm_vcpu *vcpu) 6148 { 6149 int r; 6150 struct kvm *kvm = vcpu->kvm; 6151 6152 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6153 6154 r = 1; 6155 while (r > 0) { 6156 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 6157 !vcpu->arch.apf.halted) 6158 r = vcpu_enter_guest(vcpu); 6159 else { 6160 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6161 kvm_vcpu_block(vcpu); 6162 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6163 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) { 6164 kvm_apic_accept_events(vcpu); 6165 switch(vcpu->arch.mp_state) { 6166 case KVM_MP_STATE_HALTED: 6167 vcpu->arch.pv.pv_unhalted = false; 6168 vcpu->arch.mp_state = 6169 KVM_MP_STATE_RUNNABLE; 6170 case KVM_MP_STATE_RUNNABLE: 6171 vcpu->arch.apf.halted = false; 6172 break; 6173 case KVM_MP_STATE_INIT_RECEIVED: 6174 break; 6175 default: 6176 r = -EINTR; 6177 break; 6178 } 6179 } 6180 } 6181 6182 if (r <= 0) 6183 break; 6184 6185 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); 6186 if (kvm_cpu_has_pending_timer(vcpu)) 6187 kvm_inject_pending_timer_irqs(vcpu); 6188 6189 if (dm_request_for_irq_injection(vcpu)) { 6190 r = -EINTR; 6191 vcpu->run->exit_reason = KVM_EXIT_INTR; 6192 ++vcpu->stat.request_irq_exits; 6193 } 6194 6195 kvm_check_async_pf_completion(vcpu); 6196 6197 if (signal_pending(current)) { 6198 r = -EINTR; 6199 vcpu->run->exit_reason = KVM_EXIT_INTR; 6200 ++vcpu->stat.signal_exits; 6201 } 6202 if (need_resched()) { 6203 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6204 cond_resched(); 6205 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu); 6206 } 6207 } 6208 6209 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx); 6210 6211 return r; 6212 } 6213 6214 static inline int complete_emulated_io(struct kvm_vcpu *vcpu) 6215 { 6216 int r; 6217 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); 6218 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE); 6219 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); 6220 if (r != EMULATE_DONE) 6221 return 0; 6222 return 1; 6223 } 6224 6225 static int complete_emulated_pio(struct kvm_vcpu *vcpu) 6226 { 6227 BUG_ON(!vcpu->arch.pio.count); 6228 6229 return complete_emulated_io(vcpu); 6230 } 6231 6232 /* 6233 * Implements the following, as a state machine: 6234 * 6235 * read: 6236 * for each fragment 6237 * for each mmio piece in the fragment 6238 * write gpa, len 6239 * exit 6240 * copy data 6241 * execute insn 6242 * 6243 * write: 6244 * for each fragment 6245 * for each mmio piece in the fragment 6246 * write gpa, len 6247 * copy data 6248 * exit 6249 */ 6250 static int complete_emulated_mmio(struct kvm_vcpu *vcpu) 6251 { 6252 struct kvm_run *run = vcpu->run; 6253 struct kvm_mmio_fragment *frag; 6254 unsigned len; 6255 6256 BUG_ON(!vcpu->mmio_needed); 6257 6258 /* Complete previous fragment */ 6259 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; 6260 len = min(8u, frag->len); 6261 if (!vcpu->mmio_is_write) 6262 memcpy(frag->data, run->mmio.data, len); 6263 6264 if (frag->len <= 8) { 6265 /* Switch to the next fragment. */ 6266 frag++; 6267 vcpu->mmio_cur_fragment++; 6268 } else { 6269 /* Go forward to the next mmio piece. */ 6270 frag->data += len; 6271 frag->gpa += len; 6272 frag->len -= len; 6273 } 6274 6275 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { 6276 vcpu->mmio_needed = 0; 6277 6278 /* FIXME: return into emulator if single-stepping. */ 6279 if (vcpu->mmio_is_write) 6280 return 1; 6281 vcpu->mmio_read_completed = 1; 6282 return complete_emulated_io(vcpu); 6283 } 6284 6285 run->exit_reason = KVM_EXIT_MMIO; 6286 run->mmio.phys_addr = frag->gpa; 6287 if (vcpu->mmio_is_write) 6288 memcpy(run->mmio.data, frag->data, min(8u, frag->len)); 6289 run->mmio.len = min(8u, frag->len); 6290 run->mmio.is_write = vcpu->mmio_is_write; 6291 vcpu->arch.complete_userspace_io = complete_emulated_mmio; 6292 return 0; 6293 } 6294 6295 6296 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) 6297 { 6298 int r; 6299 sigset_t sigsaved; 6300 6301 if (!tsk_used_math(current) && init_fpu(current)) 6302 return -ENOMEM; 6303 6304 if (vcpu->sigset_active) 6305 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 6306 6307 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { 6308 kvm_vcpu_block(vcpu); 6309 kvm_apic_accept_events(vcpu); 6310 clear_bit(KVM_REQ_UNHALT, &vcpu->requests); 6311 r = -EAGAIN; 6312 goto out; 6313 } 6314 6315 /* re-sync apic's tpr */ 6316 if (!irqchip_in_kernel(vcpu->kvm)) { 6317 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { 6318 r = -EINVAL; 6319 goto out; 6320 } 6321 } 6322 6323 if (unlikely(vcpu->arch.complete_userspace_io)) { 6324 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; 6325 vcpu->arch.complete_userspace_io = NULL; 6326 r = cui(vcpu); 6327 if (r <= 0) 6328 goto out; 6329 } else 6330 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed); 6331 6332 r = __vcpu_run(vcpu); 6333 6334 out: 6335 post_kvm_run_save(vcpu); 6336 if (vcpu->sigset_active) 6337 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 6338 6339 return r; 6340 } 6341 6342 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6343 { 6344 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { 6345 /* 6346 * We are here if userspace calls get_regs() in the middle of 6347 * instruction emulation. Registers state needs to be copied 6348 * back from emulation context to vcpu. Userspace shouldn't do 6349 * that usually, but some bad designed PV devices (vmware 6350 * backdoor interface) need this to work 6351 */ 6352 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt); 6353 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6354 } 6355 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); 6356 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); 6357 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); 6358 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); 6359 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); 6360 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); 6361 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); 6362 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); 6363 #ifdef CONFIG_X86_64 6364 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); 6365 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); 6366 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); 6367 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); 6368 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); 6369 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); 6370 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); 6371 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); 6372 #endif 6373 6374 regs->rip = kvm_rip_read(vcpu); 6375 regs->rflags = kvm_get_rflags(vcpu); 6376 6377 return 0; 6378 } 6379 6380 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 6381 { 6382 vcpu->arch.emulate_regs_need_sync_from_vcpu = true; 6383 vcpu->arch.emulate_regs_need_sync_to_vcpu = false; 6384 6385 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); 6386 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); 6387 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); 6388 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); 6389 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); 6390 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); 6391 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); 6392 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); 6393 #ifdef CONFIG_X86_64 6394 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); 6395 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); 6396 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); 6397 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); 6398 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); 6399 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); 6400 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); 6401 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); 6402 #endif 6403 6404 kvm_rip_write(vcpu, regs->rip); 6405 kvm_set_rflags(vcpu, regs->rflags); 6406 6407 vcpu->arch.exception.pending = false; 6408 6409 kvm_make_request(KVM_REQ_EVENT, vcpu); 6410 6411 return 0; 6412 } 6413 6414 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 6415 { 6416 struct kvm_segment cs; 6417 6418 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 6419 *db = cs.db; 6420 *l = cs.l; 6421 } 6422 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); 6423 6424 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 6425 struct kvm_sregs *sregs) 6426 { 6427 struct desc_ptr dt; 6428 6429 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 6430 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 6431 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); 6432 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 6433 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 6434 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 6435 6436 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 6437 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 6438 6439 kvm_x86_ops->get_idt(vcpu, &dt); 6440 sregs->idt.limit = dt.size; 6441 sregs->idt.base = dt.address; 6442 kvm_x86_ops->get_gdt(vcpu, &dt); 6443 sregs->gdt.limit = dt.size; 6444 sregs->gdt.base = dt.address; 6445 6446 sregs->cr0 = kvm_read_cr0(vcpu); 6447 sregs->cr2 = vcpu->arch.cr2; 6448 sregs->cr3 = kvm_read_cr3(vcpu); 6449 sregs->cr4 = kvm_read_cr4(vcpu); 6450 sregs->cr8 = kvm_get_cr8(vcpu); 6451 sregs->efer = vcpu->arch.efer; 6452 sregs->apic_base = kvm_get_apic_base(vcpu); 6453 6454 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); 6455 6456 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) 6457 set_bit(vcpu->arch.interrupt.nr, 6458 (unsigned long *)sregs->interrupt_bitmap); 6459 6460 return 0; 6461 } 6462 6463 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 6464 struct kvm_mp_state *mp_state) 6465 { 6466 kvm_apic_accept_events(vcpu); 6467 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED && 6468 vcpu->arch.pv.pv_unhalted) 6469 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 6470 else 6471 mp_state->mp_state = vcpu->arch.mp_state; 6472 6473 return 0; 6474 } 6475 6476 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 6477 struct kvm_mp_state *mp_state) 6478 { 6479 if (!kvm_vcpu_has_lapic(vcpu) && 6480 mp_state->mp_state != KVM_MP_STATE_RUNNABLE) 6481 return -EINVAL; 6482 6483 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { 6484 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 6485 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); 6486 } else 6487 vcpu->arch.mp_state = mp_state->mp_state; 6488 kvm_make_request(KVM_REQ_EVENT, vcpu); 6489 return 0; 6490 } 6491 6492 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, 6493 int reason, bool has_error_code, u32 error_code) 6494 { 6495 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 6496 int ret; 6497 6498 init_emulate_ctxt(vcpu); 6499 6500 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, 6501 has_error_code, error_code); 6502 6503 if (ret) 6504 return EMULATE_FAIL; 6505 6506 kvm_rip_write(vcpu, ctxt->eip); 6507 kvm_set_rflags(vcpu, ctxt->eflags); 6508 kvm_make_request(KVM_REQ_EVENT, vcpu); 6509 return EMULATE_DONE; 6510 } 6511 EXPORT_SYMBOL_GPL(kvm_task_switch); 6512 6513 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 6514 struct kvm_sregs *sregs) 6515 { 6516 struct msr_data apic_base_msr; 6517 int mmu_reset_needed = 0; 6518 int pending_vec, max_bits, idx; 6519 struct desc_ptr dt; 6520 6521 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE)) 6522 return -EINVAL; 6523 6524 dt.size = sregs->idt.limit; 6525 dt.address = sregs->idt.base; 6526 kvm_x86_ops->set_idt(vcpu, &dt); 6527 dt.size = sregs->gdt.limit; 6528 dt.address = sregs->gdt.base; 6529 kvm_x86_ops->set_gdt(vcpu, &dt); 6530 6531 vcpu->arch.cr2 = sregs->cr2; 6532 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; 6533 vcpu->arch.cr3 = sregs->cr3; 6534 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); 6535 6536 kvm_set_cr8(vcpu, sregs->cr8); 6537 6538 mmu_reset_needed |= vcpu->arch.efer != sregs->efer; 6539 kvm_x86_ops->set_efer(vcpu, sregs->efer); 6540 apic_base_msr.data = sregs->apic_base; 6541 apic_base_msr.host_initiated = true; 6542 kvm_set_apic_base(vcpu, &apic_base_msr); 6543 6544 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; 6545 kvm_x86_ops->set_cr0(vcpu, sregs->cr0); 6546 vcpu->arch.cr0 = sregs->cr0; 6547 6548 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; 6549 kvm_x86_ops->set_cr4(vcpu, sregs->cr4); 6550 if (sregs->cr4 & X86_CR4_OSXSAVE) 6551 kvm_update_cpuid(vcpu); 6552 6553 idx = srcu_read_lock(&vcpu->kvm->srcu); 6554 if (!is_long_mode(vcpu) && is_pae(vcpu)) { 6555 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)); 6556 mmu_reset_needed = 1; 6557 } 6558 srcu_read_unlock(&vcpu->kvm->srcu, idx); 6559 6560 if (mmu_reset_needed) 6561 kvm_mmu_reset_context(vcpu); 6562 6563 max_bits = KVM_NR_INTERRUPTS; 6564 pending_vec = find_first_bit( 6565 (const unsigned long *)sregs->interrupt_bitmap, max_bits); 6566 if (pending_vec < max_bits) { 6567 kvm_queue_interrupt(vcpu, pending_vec, false); 6568 pr_debug("Set back pending irq %d\n", pending_vec); 6569 } 6570 6571 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); 6572 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); 6573 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); 6574 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); 6575 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); 6576 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); 6577 6578 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); 6579 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); 6580 6581 update_cr8_intercept(vcpu); 6582 6583 /* Older userspace won't unhalt the vcpu on reset. */ 6584 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && 6585 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && 6586 !is_protmode(vcpu)) 6587 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 6588 6589 kvm_make_request(KVM_REQ_EVENT, vcpu); 6590 6591 return 0; 6592 } 6593 6594 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 6595 struct kvm_guest_debug *dbg) 6596 { 6597 unsigned long rflags; 6598 int i, r; 6599 6600 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { 6601 r = -EBUSY; 6602 if (vcpu->arch.exception.pending) 6603 goto out; 6604 if (dbg->control & KVM_GUESTDBG_INJECT_DB) 6605 kvm_queue_exception(vcpu, DB_VECTOR); 6606 else 6607 kvm_queue_exception(vcpu, BP_VECTOR); 6608 } 6609 6610 /* 6611 * Read rflags as long as potentially injected trace flags are still 6612 * filtered out. 6613 */ 6614 rflags = kvm_get_rflags(vcpu); 6615 6616 vcpu->guest_debug = dbg->control; 6617 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) 6618 vcpu->guest_debug = 0; 6619 6620 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 6621 for (i = 0; i < KVM_NR_DB_REGS; ++i) 6622 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; 6623 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; 6624 } else { 6625 for (i = 0; i < KVM_NR_DB_REGS; i++) 6626 vcpu->arch.eff_db[i] = vcpu->arch.db[i]; 6627 } 6628 kvm_update_dr7(vcpu); 6629 6630 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6631 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) + 6632 get_segment_base(vcpu, VCPU_SREG_CS); 6633 6634 /* 6635 * Trigger an rflags update that will inject or remove the trace 6636 * flags. 6637 */ 6638 kvm_set_rflags(vcpu, rflags); 6639 6640 kvm_x86_ops->update_db_bp_intercept(vcpu); 6641 6642 r = 0; 6643 6644 out: 6645 6646 return r; 6647 } 6648 6649 /* 6650 * Translate a guest virtual address to a guest physical address. 6651 */ 6652 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 6653 struct kvm_translation *tr) 6654 { 6655 unsigned long vaddr = tr->linear_address; 6656 gpa_t gpa; 6657 int idx; 6658 6659 idx = srcu_read_lock(&vcpu->kvm->srcu); 6660 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); 6661 srcu_read_unlock(&vcpu->kvm->srcu, idx); 6662 tr->physical_address = gpa; 6663 tr->valid = gpa != UNMAPPED_GVA; 6664 tr->writeable = 1; 6665 tr->usermode = 0; 6666 6667 return 0; 6668 } 6669 6670 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 6671 { 6672 struct i387_fxsave_struct *fxsave = 6673 &vcpu->arch.guest_fpu.state->fxsave; 6674 6675 memcpy(fpu->fpr, fxsave->st_space, 128); 6676 fpu->fcw = fxsave->cwd; 6677 fpu->fsw = fxsave->swd; 6678 fpu->ftwx = fxsave->twd; 6679 fpu->last_opcode = fxsave->fop; 6680 fpu->last_ip = fxsave->rip; 6681 fpu->last_dp = fxsave->rdp; 6682 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); 6683 6684 return 0; 6685 } 6686 6687 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 6688 { 6689 struct i387_fxsave_struct *fxsave = 6690 &vcpu->arch.guest_fpu.state->fxsave; 6691 6692 memcpy(fxsave->st_space, fpu->fpr, 128); 6693 fxsave->cwd = fpu->fcw; 6694 fxsave->swd = fpu->fsw; 6695 fxsave->twd = fpu->ftwx; 6696 fxsave->fop = fpu->last_opcode; 6697 fxsave->rip = fpu->last_ip; 6698 fxsave->rdp = fpu->last_dp; 6699 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); 6700 6701 return 0; 6702 } 6703 6704 int fx_init(struct kvm_vcpu *vcpu) 6705 { 6706 int err; 6707 6708 err = fpu_alloc(&vcpu->arch.guest_fpu); 6709 if (err) 6710 return err; 6711 6712 fpu_finit(&vcpu->arch.guest_fpu); 6713 6714 /* 6715 * Ensure guest xcr0 is valid for loading 6716 */ 6717 vcpu->arch.xcr0 = XSTATE_FP; 6718 6719 vcpu->arch.cr0 |= X86_CR0_ET; 6720 6721 return 0; 6722 } 6723 EXPORT_SYMBOL_GPL(fx_init); 6724 6725 static void fx_free(struct kvm_vcpu *vcpu) 6726 { 6727 fpu_free(&vcpu->arch.guest_fpu); 6728 } 6729 6730 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) 6731 { 6732 if (vcpu->guest_fpu_loaded) 6733 return; 6734 6735 /* 6736 * Restore all possible states in the guest, 6737 * and assume host would use all available bits. 6738 * Guest xcr0 would be loaded later. 6739 */ 6740 kvm_put_guest_xcr0(vcpu); 6741 vcpu->guest_fpu_loaded = 1; 6742 __kernel_fpu_begin(); 6743 fpu_restore_checking(&vcpu->arch.guest_fpu); 6744 trace_kvm_fpu(1); 6745 } 6746 6747 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) 6748 { 6749 kvm_put_guest_xcr0(vcpu); 6750 6751 if (!vcpu->guest_fpu_loaded) 6752 return; 6753 6754 vcpu->guest_fpu_loaded = 0; 6755 fpu_save_init(&vcpu->arch.guest_fpu); 6756 __kernel_fpu_end(); 6757 ++vcpu->stat.fpu_reload; 6758 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu); 6759 trace_kvm_fpu(0); 6760 } 6761 6762 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 6763 { 6764 kvmclock_reset(vcpu); 6765 6766 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 6767 fx_free(vcpu); 6768 kvm_x86_ops->vcpu_free(vcpu); 6769 } 6770 6771 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, 6772 unsigned int id) 6773 { 6774 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0) 6775 printk_once(KERN_WARNING 6776 "kvm: SMP vm created on host with unstable TSC; " 6777 "guest TSC will not be reliable\n"); 6778 return kvm_x86_ops->vcpu_create(kvm, id); 6779 } 6780 6781 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 6782 { 6783 int r; 6784 6785 vcpu->arch.mtrr_state.have_fixed = 1; 6786 r = vcpu_load(vcpu); 6787 if (r) 6788 return r; 6789 kvm_vcpu_reset(vcpu); 6790 kvm_mmu_setup(vcpu); 6791 vcpu_put(vcpu); 6792 6793 return r; 6794 } 6795 6796 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 6797 { 6798 int r; 6799 struct msr_data msr; 6800 struct kvm *kvm = vcpu->kvm; 6801 6802 r = vcpu_load(vcpu); 6803 if (r) 6804 return r; 6805 msr.data = 0x0; 6806 msr.index = MSR_IA32_TSC; 6807 msr.host_initiated = true; 6808 kvm_write_tsc(vcpu, &msr); 6809 vcpu_put(vcpu); 6810 6811 schedule_delayed_work(&kvm->arch.kvmclock_sync_work, 6812 KVMCLOCK_SYNC_PERIOD); 6813 6814 return r; 6815 } 6816 6817 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 6818 { 6819 int r; 6820 vcpu->arch.apf.msr_val = 0; 6821 6822 r = vcpu_load(vcpu); 6823 BUG_ON(r); 6824 kvm_mmu_unload(vcpu); 6825 vcpu_put(vcpu); 6826 6827 fx_free(vcpu); 6828 kvm_x86_ops->vcpu_free(vcpu); 6829 } 6830 6831 void kvm_vcpu_reset(struct kvm_vcpu *vcpu) 6832 { 6833 atomic_set(&vcpu->arch.nmi_queued, 0); 6834 vcpu->arch.nmi_pending = 0; 6835 vcpu->arch.nmi_injected = false; 6836 6837 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); 6838 vcpu->arch.dr6 = DR6_FIXED_1; 6839 kvm_update_dr6(vcpu); 6840 vcpu->arch.dr7 = DR7_FIXED_1; 6841 kvm_update_dr7(vcpu); 6842 6843 kvm_make_request(KVM_REQ_EVENT, vcpu); 6844 vcpu->arch.apf.msr_val = 0; 6845 vcpu->arch.st.msr_val = 0; 6846 6847 kvmclock_reset(vcpu); 6848 6849 kvm_clear_async_pf_completion_queue(vcpu); 6850 kvm_async_pf_hash_reset(vcpu); 6851 vcpu->arch.apf.halted = false; 6852 6853 kvm_pmu_reset(vcpu); 6854 6855 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); 6856 vcpu->arch.regs_avail = ~0; 6857 vcpu->arch.regs_dirty = ~0; 6858 6859 kvm_x86_ops->vcpu_reset(vcpu); 6860 } 6861 6862 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector) 6863 { 6864 struct kvm_segment cs; 6865 6866 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); 6867 cs.selector = vector << 8; 6868 cs.base = vector << 12; 6869 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); 6870 kvm_rip_write(vcpu, 0); 6871 } 6872 6873 int kvm_arch_hardware_enable(void *garbage) 6874 { 6875 struct kvm *kvm; 6876 struct kvm_vcpu *vcpu; 6877 int i; 6878 int ret; 6879 u64 local_tsc; 6880 u64 max_tsc = 0; 6881 bool stable, backwards_tsc = false; 6882 6883 kvm_shared_msr_cpu_online(); 6884 ret = kvm_x86_ops->hardware_enable(garbage); 6885 if (ret != 0) 6886 return ret; 6887 6888 local_tsc = native_read_tsc(); 6889 stable = !check_tsc_unstable(); 6890 list_for_each_entry(kvm, &vm_list, vm_list) { 6891 kvm_for_each_vcpu(i, vcpu, kvm) { 6892 if (!stable && vcpu->cpu == smp_processor_id()) 6893 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests); 6894 if (stable && vcpu->arch.last_host_tsc > local_tsc) { 6895 backwards_tsc = true; 6896 if (vcpu->arch.last_host_tsc > max_tsc) 6897 max_tsc = vcpu->arch.last_host_tsc; 6898 } 6899 } 6900 } 6901 6902 /* 6903 * Sometimes, even reliable TSCs go backwards. This happens on 6904 * platforms that reset TSC during suspend or hibernate actions, but 6905 * maintain synchronization. We must compensate. Fortunately, we can 6906 * detect that condition here, which happens early in CPU bringup, 6907 * before any KVM threads can be running. Unfortunately, we can't 6908 * bring the TSCs fully up to date with real time, as we aren't yet far 6909 * enough into CPU bringup that we know how much real time has actually 6910 * elapsed; our helper function, get_kernel_ns() will be using boot 6911 * variables that haven't been updated yet. 6912 * 6913 * So we simply find the maximum observed TSC above, then record the 6914 * adjustment to TSC in each VCPU. When the VCPU later gets loaded, 6915 * the adjustment will be applied. Note that we accumulate 6916 * adjustments, in case multiple suspend cycles happen before some VCPU 6917 * gets a chance to run again. In the event that no KVM threads get a 6918 * chance to run, we will miss the entire elapsed period, as we'll have 6919 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may 6920 * loose cycle time. This isn't too big a deal, since the loss will be 6921 * uniform across all VCPUs (not to mention the scenario is extremely 6922 * unlikely). It is possible that a second hibernate recovery happens 6923 * much faster than a first, causing the observed TSC here to be 6924 * smaller; this would require additional padding adjustment, which is 6925 * why we set last_host_tsc to the local tsc observed here. 6926 * 6927 * N.B. - this code below runs only on platforms with reliable TSC, 6928 * as that is the only way backwards_tsc is set above. Also note 6929 * that this runs for ALL vcpus, which is not a bug; all VCPUs should 6930 * have the same delta_cyc adjustment applied if backwards_tsc 6931 * is detected. Note further, this adjustment is only done once, 6932 * as we reset last_host_tsc on all VCPUs to stop this from being 6933 * called multiple times (one for each physical CPU bringup). 6934 * 6935 * Platforms with unreliable TSCs don't have to deal with this, they 6936 * will be compensated by the logic in vcpu_load, which sets the TSC to 6937 * catchup mode. This will catchup all VCPUs to real time, but cannot 6938 * guarantee that they stay in perfect synchronization. 6939 */ 6940 if (backwards_tsc) { 6941 u64 delta_cyc = max_tsc - local_tsc; 6942 list_for_each_entry(kvm, &vm_list, vm_list) { 6943 kvm_for_each_vcpu(i, vcpu, kvm) { 6944 vcpu->arch.tsc_offset_adjustment += delta_cyc; 6945 vcpu->arch.last_host_tsc = local_tsc; 6946 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, 6947 &vcpu->requests); 6948 } 6949 6950 /* 6951 * We have to disable TSC offset matching.. if you were 6952 * booting a VM while issuing an S4 host suspend.... 6953 * you may have some problem. Solving this issue is 6954 * left as an exercise to the reader. 6955 */ 6956 kvm->arch.last_tsc_nsec = 0; 6957 kvm->arch.last_tsc_write = 0; 6958 } 6959 6960 } 6961 return 0; 6962 } 6963 6964 void kvm_arch_hardware_disable(void *garbage) 6965 { 6966 kvm_x86_ops->hardware_disable(garbage); 6967 drop_user_return_notifiers(garbage); 6968 } 6969 6970 int kvm_arch_hardware_setup(void) 6971 { 6972 return kvm_x86_ops->hardware_setup(); 6973 } 6974 6975 void kvm_arch_hardware_unsetup(void) 6976 { 6977 kvm_x86_ops->hardware_unsetup(); 6978 } 6979 6980 void kvm_arch_check_processor_compat(void *rtn) 6981 { 6982 kvm_x86_ops->check_processor_compatibility(rtn); 6983 } 6984 6985 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu) 6986 { 6987 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL); 6988 } 6989 6990 struct static_key kvm_no_apic_vcpu __read_mostly; 6991 6992 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 6993 { 6994 struct page *page; 6995 struct kvm *kvm; 6996 int r; 6997 6998 BUG_ON(vcpu->kvm == NULL); 6999 kvm = vcpu->kvm; 7000 7001 vcpu->arch.pv.pv_unhalted = false; 7002 vcpu->arch.emulate_ctxt.ops = &emulate_ops; 7003 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu)) 7004 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7005 else 7006 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; 7007 7008 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 7009 if (!page) { 7010 r = -ENOMEM; 7011 goto fail; 7012 } 7013 vcpu->arch.pio_data = page_address(page); 7014 7015 kvm_set_tsc_khz(vcpu, max_tsc_khz); 7016 7017 r = kvm_mmu_create(vcpu); 7018 if (r < 0) 7019 goto fail_free_pio_data; 7020 7021 if (irqchip_in_kernel(kvm)) { 7022 r = kvm_create_lapic(vcpu); 7023 if (r < 0) 7024 goto fail_mmu_destroy; 7025 } else 7026 static_key_slow_inc(&kvm_no_apic_vcpu); 7027 7028 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, 7029 GFP_KERNEL); 7030 if (!vcpu->arch.mce_banks) { 7031 r = -ENOMEM; 7032 goto fail_free_lapic; 7033 } 7034 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; 7035 7036 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) { 7037 r = -ENOMEM; 7038 goto fail_free_mce_banks; 7039 } 7040 7041 r = fx_init(vcpu); 7042 if (r) 7043 goto fail_free_wbinvd_dirty_mask; 7044 7045 vcpu->arch.ia32_tsc_adjust_msr = 0x0; 7046 vcpu->arch.pv_time_enabled = false; 7047 7048 vcpu->arch.guest_supported_xcr0 = 0; 7049 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 7050 7051 kvm_async_pf_hash_reset(vcpu); 7052 kvm_pmu_init(vcpu); 7053 7054 return 0; 7055 fail_free_wbinvd_dirty_mask: 7056 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); 7057 fail_free_mce_banks: 7058 kfree(vcpu->arch.mce_banks); 7059 fail_free_lapic: 7060 kvm_free_lapic(vcpu); 7061 fail_mmu_destroy: 7062 kvm_mmu_destroy(vcpu); 7063 fail_free_pio_data: 7064 free_page((unsigned long)vcpu->arch.pio_data); 7065 fail: 7066 return r; 7067 } 7068 7069 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 7070 { 7071 int idx; 7072 7073 kvm_pmu_destroy(vcpu); 7074 kfree(vcpu->arch.mce_banks); 7075 kvm_free_lapic(vcpu); 7076 idx = srcu_read_lock(&vcpu->kvm->srcu); 7077 kvm_mmu_destroy(vcpu); 7078 srcu_read_unlock(&vcpu->kvm->srcu, idx); 7079 free_page((unsigned long)vcpu->arch.pio_data); 7080 if (!irqchip_in_kernel(vcpu->kvm)) 7081 static_key_slow_dec(&kvm_no_apic_vcpu); 7082 } 7083 7084 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 7085 { 7086 if (type) 7087 return -EINVAL; 7088 7089 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); 7090 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages); 7091 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); 7092 atomic_set(&kvm->arch.noncoherent_dma_count, 0); 7093 7094 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ 7095 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); 7096 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ 7097 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, 7098 &kvm->arch.irq_sources_bitmap); 7099 7100 raw_spin_lock_init(&kvm->arch.tsc_write_lock); 7101 mutex_init(&kvm->arch.apic_map_lock); 7102 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock); 7103 7104 pvclock_update_vm_gtod_copy(kvm); 7105 7106 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); 7107 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); 7108 7109 return 0; 7110 } 7111 7112 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) 7113 { 7114 int r; 7115 r = vcpu_load(vcpu); 7116 BUG_ON(r); 7117 kvm_mmu_unload(vcpu); 7118 vcpu_put(vcpu); 7119 } 7120 7121 static void kvm_free_vcpus(struct kvm *kvm) 7122 { 7123 unsigned int i; 7124 struct kvm_vcpu *vcpu; 7125 7126 /* 7127 * Unpin any mmu pages first. 7128 */ 7129 kvm_for_each_vcpu(i, vcpu, kvm) { 7130 kvm_clear_async_pf_completion_queue(vcpu); 7131 kvm_unload_vcpu_mmu(vcpu); 7132 } 7133 kvm_for_each_vcpu(i, vcpu, kvm) 7134 kvm_arch_vcpu_free(vcpu); 7135 7136 mutex_lock(&kvm->lock); 7137 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 7138 kvm->vcpus[i] = NULL; 7139 7140 atomic_set(&kvm->online_vcpus, 0); 7141 mutex_unlock(&kvm->lock); 7142 } 7143 7144 void kvm_arch_sync_events(struct kvm *kvm) 7145 { 7146 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); 7147 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); 7148 kvm_free_all_assigned_devices(kvm); 7149 kvm_free_pit(kvm); 7150 } 7151 7152 void kvm_arch_destroy_vm(struct kvm *kvm) 7153 { 7154 if (current->mm == kvm->mm) { 7155 /* 7156 * Free memory regions allocated on behalf of userspace, 7157 * unless the the memory map has changed due to process exit 7158 * or fd copying. 7159 */ 7160 struct kvm_userspace_memory_region mem; 7161 memset(&mem, 0, sizeof(mem)); 7162 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; 7163 kvm_set_memory_region(kvm, &mem); 7164 7165 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; 7166 kvm_set_memory_region(kvm, &mem); 7167 7168 mem.slot = TSS_PRIVATE_MEMSLOT; 7169 kvm_set_memory_region(kvm, &mem); 7170 } 7171 kvm_iommu_unmap_guest(kvm); 7172 kfree(kvm->arch.vpic); 7173 kfree(kvm->arch.vioapic); 7174 kvm_free_vcpus(kvm); 7175 if (kvm->arch.apic_access_page) 7176 put_page(kvm->arch.apic_access_page); 7177 if (kvm->arch.ept_identity_pagetable) 7178 put_page(kvm->arch.ept_identity_pagetable); 7179 kfree(rcu_dereference_check(kvm->arch.apic_map, 1)); 7180 } 7181 7182 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, 7183 struct kvm_memory_slot *dont) 7184 { 7185 int i; 7186 7187 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7188 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) { 7189 kvm_kvfree(free->arch.rmap[i]); 7190 free->arch.rmap[i] = NULL; 7191 } 7192 if (i == 0) 7193 continue; 7194 7195 if (!dont || free->arch.lpage_info[i - 1] != 7196 dont->arch.lpage_info[i - 1]) { 7197 kvm_kvfree(free->arch.lpage_info[i - 1]); 7198 free->arch.lpage_info[i - 1] = NULL; 7199 } 7200 } 7201 } 7202 7203 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 7204 unsigned long npages) 7205 { 7206 int i; 7207 7208 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7209 unsigned long ugfn; 7210 int lpages; 7211 int level = i + 1; 7212 7213 lpages = gfn_to_index(slot->base_gfn + npages - 1, 7214 slot->base_gfn, level) + 1; 7215 7216 slot->arch.rmap[i] = 7217 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i])); 7218 if (!slot->arch.rmap[i]) 7219 goto out_free; 7220 if (i == 0) 7221 continue; 7222 7223 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages * 7224 sizeof(*slot->arch.lpage_info[i - 1])); 7225 if (!slot->arch.lpage_info[i - 1]) 7226 goto out_free; 7227 7228 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) 7229 slot->arch.lpage_info[i - 1][0].write_count = 1; 7230 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) 7231 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1; 7232 ugfn = slot->userspace_addr >> PAGE_SHIFT; 7233 /* 7234 * If the gfn and userspace address are not aligned wrt each 7235 * other, or if explicitly asked to, disable large page 7236 * support for this slot 7237 */ 7238 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) || 7239 !kvm_largepages_enabled()) { 7240 unsigned long j; 7241 7242 for (j = 0; j < lpages; ++j) 7243 slot->arch.lpage_info[i - 1][j].write_count = 1; 7244 } 7245 } 7246 7247 return 0; 7248 7249 out_free: 7250 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { 7251 kvm_kvfree(slot->arch.rmap[i]); 7252 slot->arch.rmap[i] = NULL; 7253 if (i == 0) 7254 continue; 7255 7256 kvm_kvfree(slot->arch.lpage_info[i - 1]); 7257 slot->arch.lpage_info[i - 1] = NULL; 7258 } 7259 return -ENOMEM; 7260 } 7261 7262 void kvm_arch_memslots_updated(struct kvm *kvm) 7263 { 7264 /* 7265 * memslots->generation has been incremented. 7266 * mmio generation may have reached its maximum value. 7267 */ 7268 kvm_mmu_invalidate_mmio_sptes(kvm); 7269 } 7270 7271 int kvm_arch_prepare_memory_region(struct kvm *kvm, 7272 struct kvm_memory_slot *memslot, 7273 struct kvm_userspace_memory_region *mem, 7274 enum kvm_mr_change change) 7275 { 7276 /* 7277 * Only private memory slots need to be mapped here since 7278 * KVM_SET_MEMORY_REGION ioctl is no longer supported. 7279 */ 7280 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) { 7281 unsigned long userspace_addr; 7282 7283 /* 7284 * MAP_SHARED to prevent internal slot pages from being moved 7285 * by fork()/COW. 7286 */ 7287 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE, 7288 PROT_READ | PROT_WRITE, 7289 MAP_SHARED | MAP_ANONYMOUS, 0); 7290 7291 if (IS_ERR((void *)userspace_addr)) 7292 return PTR_ERR((void *)userspace_addr); 7293 7294 memslot->userspace_addr = userspace_addr; 7295 } 7296 7297 return 0; 7298 } 7299 7300 void kvm_arch_commit_memory_region(struct kvm *kvm, 7301 struct kvm_userspace_memory_region *mem, 7302 const struct kvm_memory_slot *old, 7303 enum kvm_mr_change change) 7304 { 7305 7306 int nr_mmu_pages = 0; 7307 7308 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) { 7309 int ret; 7310 7311 ret = vm_munmap(old->userspace_addr, 7312 old->npages * PAGE_SIZE); 7313 if (ret < 0) 7314 printk(KERN_WARNING 7315 "kvm_vm_ioctl_set_memory_region: " 7316 "failed to munmap memory\n"); 7317 } 7318 7319 if (!kvm->arch.n_requested_mmu_pages) 7320 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); 7321 7322 if (nr_mmu_pages) 7323 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); 7324 /* 7325 * Write protect all pages for dirty logging. 7326 * 7327 * All the sptes including the large sptes which point to this 7328 * slot are set to readonly. We can not create any new large 7329 * spte on this slot until the end of the logging. 7330 * 7331 * See the comments in fast_page_fault(). 7332 */ 7333 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES)) 7334 kvm_mmu_slot_remove_write_access(kvm, mem->slot); 7335 } 7336 7337 void kvm_arch_flush_shadow_all(struct kvm *kvm) 7338 { 7339 kvm_mmu_invalidate_zap_all_pages(kvm); 7340 } 7341 7342 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 7343 struct kvm_memory_slot *slot) 7344 { 7345 kvm_mmu_invalidate_zap_all_pages(kvm); 7346 } 7347 7348 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 7349 { 7350 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) 7351 kvm_x86_ops->check_nested_events(vcpu, false); 7352 7353 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && 7354 !vcpu->arch.apf.halted) 7355 || !list_empty_careful(&vcpu->async_pf.done) 7356 || kvm_apic_has_events(vcpu) 7357 || vcpu->arch.pv.pv_unhalted 7358 || atomic_read(&vcpu->arch.nmi_queued) || 7359 (kvm_arch_interrupt_allowed(vcpu) && 7360 kvm_cpu_has_interrupt(vcpu)); 7361 } 7362 7363 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 7364 { 7365 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 7366 } 7367 7368 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) 7369 { 7370 return kvm_x86_ops->interrupt_allowed(vcpu); 7371 } 7372 7373 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) 7374 { 7375 unsigned long current_rip = kvm_rip_read(vcpu) + 7376 get_segment_base(vcpu, VCPU_SREG_CS); 7377 7378 return current_rip == linear_rip; 7379 } 7380 EXPORT_SYMBOL_GPL(kvm_is_linear_rip); 7381 7382 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) 7383 { 7384 unsigned long rflags; 7385 7386 rflags = kvm_x86_ops->get_rflags(vcpu); 7387 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 7388 rflags &= ~X86_EFLAGS_TF; 7389 return rflags; 7390 } 7391 EXPORT_SYMBOL_GPL(kvm_get_rflags); 7392 7393 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 7394 { 7395 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && 7396 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) 7397 rflags |= X86_EFLAGS_TF; 7398 kvm_x86_ops->set_rflags(vcpu, rflags); 7399 kvm_make_request(KVM_REQ_EVENT, vcpu); 7400 } 7401 EXPORT_SYMBOL_GPL(kvm_set_rflags); 7402 7403 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work) 7404 { 7405 int r; 7406 7407 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) || 7408 work->wakeup_all) 7409 return; 7410 7411 r = kvm_mmu_reload(vcpu); 7412 if (unlikely(r)) 7413 return; 7414 7415 if (!vcpu->arch.mmu.direct_map && 7416 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu)) 7417 return; 7418 7419 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true); 7420 } 7421 7422 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) 7423 { 7424 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); 7425 } 7426 7427 static inline u32 kvm_async_pf_next_probe(u32 key) 7428 { 7429 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1); 7430 } 7431 7432 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7433 { 7434 u32 key = kvm_async_pf_hash_fn(gfn); 7435 7436 while (vcpu->arch.apf.gfns[key] != ~0) 7437 key = kvm_async_pf_next_probe(key); 7438 7439 vcpu->arch.apf.gfns[key] = gfn; 7440 } 7441 7442 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) 7443 { 7444 int i; 7445 u32 key = kvm_async_pf_hash_fn(gfn); 7446 7447 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) && 7448 (vcpu->arch.apf.gfns[key] != gfn && 7449 vcpu->arch.apf.gfns[key] != ~0); i++) 7450 key = kvm_async_pf_next_probe(key); 7451 7452 return key; 7453 } 7454 7455 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7456 { 7457 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; 7458 } 7459 7460 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) 7461 { 7462 u32 i, j, k; 7463 7464 i = j = kvm_async_pf_gfn_slot(vcpu, gfn); 7465 while (true) { 7466 vcpu->arch.apf.gfns[i] = ~0; 7467 do { 7468 j = kvm_async_pf_next_probe(j); 7469 if (vcpu->arch.apf.gfns[j] == ~0) 7470 return; 7471 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); 7472 /* 7473 * k lies cyclically in ]i,j] 7474 * | i.k.j | 7475 * |....j i.k.| or |.k..j i...| 7476 */ 7477 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); 7478 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; 7479 i = j; 7480 } 7481 } 7482 7483 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val) 7484 { 7485 7486 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val, 7487 sizeof(val)); 7488 } 7489 7490 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, 7491 struct kvm_async_pf *work) 7492 { 7493 struct x86_exception fault; 7494 7495 trace_kvm_async_pf_not_present(work->arch.token, work->gva); 7496 kvm_add_async_pf_gfn(vcpu, work->arch.gfn); 7497 7498 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) || 7499 (vcpu->arch.apf.send_user_only && 7500 kvm_x86_ops->get_cpl(vcpu) == 0)) 7501 kvm_make_request(KVM_REQ_APF_HALT, vcpu); 7502 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) { 7503 fault.vector = PF_VECTOR; 7504 fault.error_code_valid = true; 7505 fault.error_code = 0; 7506 fault.nested_page_fault = false; 7507 fault.address = work->arch.token; 7508 kvm_inject_page_fault(vcpu, &fault); 7509 } 7510 } 7511 7512 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, 7513 struct kvm_async_pf *work) 7514 { 7515 struct x86_exception fault; 7516 7517 trace_kvm_async_pf_ready(work->arch.token, work->gva); 7518 if (work->wakeup_all) 7519 work->arch.token = ~0; /* broadcast wakeup */ 7520 else 7521 kvm_del_async_pf_gfn(vcpu, work->arch.gfn); 7522 7523 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) && 7524 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) { 7525 fault.vector = PF_VECTOR; 7526 fault.error_code_valid = true; 7527 fault.error_code = 0; 7528 fault.nested_page_fault = false; 7529 fault.address = work->arch.token; 7530 kvm_inject_page_fault(vcpu, &fault); 7531 } 7532 vcpu->arch.apf.halted = false; 7533 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 7534 } 7535 7536 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu) 7537 { 7538 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED)) 7539 return true; 7540 else 7541 return !kvm_event_needs_reinjection(vcpu) && 7542 kvm_x86_ops->interrupt_allowed(vcpu); 7543 } 7544 7545 void kvm_arch_register_noncoherent_dma(struct kvm *kvm) 7546 { 7547 atomic_inc(&kvm->arch.noncoherent_dma_count); 7548 } 7549 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); 7550 7551 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) 7552 { 7553 atomic_dec(&kvm->arch.noncoherent_dma_count); 7554 } 7555 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); 7556 7557 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) 7558 { 7559 return atomic_read(&kvm->arch.noncoherent_dma_count); 7560 } 7561 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); 7562 7563 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); 7564 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); 7565 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); 7566 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); 7567 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); 7568 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); 7569 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); 7570 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); 7571 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); 7572 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); 7573 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); 7574 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); 7575 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); 7576