1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_H 3 #define __KVM_X86_VMX_H 4 5 #include <linux/kvm_host.h> 6 7 #include <asm/kvm.h> 8 #include <asm/intel_pt.h> 9 10 #include "capabilities.h" 11 #include "../kvm_cache_regs.h" 12 #include "posted_intr.h" 13 #include "vmcs.h" 14 #include "vmx_ops.h" 15 #include "../cpuid.h" 16 #include "run_flags.h" 17 18 #define MSR_TYPE_R 1 19 #define MSR_TYPE_W 2 20 #define MSR_TYPE_RW 3 21 22 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4)) 23 24 #ifdef CONFIG_X86_64 25 #define MAX_NR_USER_RETURN_MSRS 7 26 #else 27 #define MAX_NR_USER_RETURN_MSRS 4 28 #endif 29 30 #define MAX_NR_LOADSTORE_MSRS 8 31 32 struct vmx_msrs { 33 unsigned int nr; 34 struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS]; 35 }; 36 37 struct vmx_uret_msr { 38 bool load_into_hardware; 39 u64 data; 40 u64 mask; 41 }; 42 43 enum segment_cache_field { 44 SEG_FIELD_SEL = 0, 45 SEG_FIELD_BASE = 1, 46 SEG_FIELD_LIMIT = 2, 47 SEG_FIELD_AR = 3, 48 49 SEG_FIELD_NR = 4 50 }; 51 52 #define RTIT_ADDR_RANGE 4 53 54 struct pt_ctx { 55 u64 ctl; 56 u64 status; 57 u64 output_base; 58 u64 output_mask; 59 u64 cr3_match; 60 u64 addr_a[RTIT_ADDR_RANGE]; 61 u64 addr_b[RTIT_ADDR_RANGE]; 62 }; 63 64 struct pt_desc { 65 u64 ctl_bitmask; 66 u32 num_address_ranges; 67 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; 68 struct pt_ctx host; 69 struct pt_ctx guest; 70 }; 71 72 union vmx_exit_reason { 73 struct { 74 u32 basic : 16; 75 u32 reserved16 : 1; 76 u32 reserved17 : 1; 77 u32 reserved18 : 1; 78 u32 reserved19 : 1; 79 u32 reserved20 : 1; 80 u32 reserved21 : 1; 81 u32 reserved22 : 1; 82 u32 reserved23 : 1; 83 u32 reserved24 : 1; 84 u32 reserved25 : 1; 85 u32 bus_lock_detected : 1; 86 u32 enclave_mode : 1; 87 u32 smi_pending_mtf : 1; 88 u32 smi_from_vmx_root : 1; 89 u32 reserved30 : 1; 90 u32 failed_vmentry : 1; 91 }; 92 u32 full; 93 }; 94 95 static inline bool intel_pmu_has_perf_global_ctrl(struct kvm_pmu *pmu) 96 { 97 /* 98 * Architecturally, Intel's SDM states that IA32_PERF_GLOBAL_CTRL is 99 * supported if "CPUID.0AH: EAX[7:0] > 0", i.e. if the PMU version is 100 * greater than zero. However, KVM only exposes and emulates the MSR 101 * to/for the guest if the guest PMU supports at least "Architectural 102 * Performance Monitoring Version 2". 103 */ 104 return pmu->version > 1; 105 } 106 107 #define vcpu_to_lbr_desc(vcpu) (&to_vmx(vcpu)->lbr_desc) 108 #define vcpu_to_lbr_records(vcpu) (&to_vmx(vcpu)->lbr_desc.records) 109 110 void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu); 111 bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu); 112 113 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu); 114 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu); 115 116 struct lbr_desc { 117 /* Basic info about guest LBR records. */ 118 struct x86_pmu_lbr records; 119 120 /* 121 * Emulate LBR feature via passthrough LBR registers when the 122 * per-vcpu guest LBR event is scheduled on the current pcpu. 123 * 124 * The records may be inaccurate if the host reclaims the LBR. 125 */ 126 struct perf_event *event; 127 128 /* True if LBRs are marked as not intercepted in the MSR bitmap */ 129 bool msr_passthrough; 130 }; 131 132 /* 133 * The nested_vmx structure is part of vcpu_vmx, and holds information we need 134 * for correct emulation of VMX (i.e., nested VMX) on this vcpu. 135 */ 136 struct nested_vmx { 137 /* Has the level1 guest done vmxon? */ 138 bool vmxon; 139 gpa_t vmxon_ptr; 140 bool pml_full; 141 142 /* The guest-physical address of the current VMCS L1 keeps for L2 */ 143 gpa_t current_vmptr; 144 /* 145 * Cache of the guest's VMCS, existing outside of guest memory. 146 * Loaded from guest memory during VMPTRLD. Flushed to guest 147 * memory during VMCLEAR and VMPTRLD. 148 */ 149 struct vmcs12 *cached_vmcs12; 150 /* 151 * Cache of the guest's shadow VMCS, existing outside of guest 152 * memory. Loaded from guest memory during VM entry. Flushed 153 * to guest memory during VM exit. 154 */ 155 struct vmcs12 *cached_shadow_vmcs12; 156 157 /* 158 * GPA to HVA cache for accessing vmcs12->vmcs_link_pointer 159 */ 160 struct gfn_to_hva_cache shadow_vmcs12_cache; 161 162 /* 163 * GPA to HVA cache for VMCS12 164 */ 165 struct gfn_to_hva_cache vmcs12_cache; 166 167 /* 168 * Indicates if the shadow vmcs or enlightened vmcs must be updated 169 * with the data held by struct vmcs12. 170 */ 171 bool need_vmcs12_to_shadow_sync; 172 bool dirty_vmcs12; 173 174 /* 175 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to 176 * changes in MSR bitmap for L1 or switching to a different L2. Note, 177 * this flag can only be used reliably in conjunction with a paravirt L1 178 * which informs L0 whether any changes to MSR bitmap for L2 were done 179 * on its side. 180 */ 181 bool force_msr_bitmap_recalc; 182 183 /* 184 * Indicates lazily loaded guest state has not yet been decached from 185 * vmcs02. 186 */ 187 bool need_sync_vmcs02_to_vmcs12_rare; 188 189 /* 190 * vmcs02 has been initialized, i.e. state that is constant for 191 * vmcs02 has been written to the backing VMCS. Initialization 192 * is delayed until L1 actually attempts to run a nested VM. 193 */ 194 bool vmcs02_initialized; 195 196 bool change_vmcs01_virtual_apic_mode; 197 bool reload_vmcs01_apic_access_page; 198 bool update_vmcs01_cpu_dirty_logging; 199 bool update_vmcs01_apicv_status; 200 201 /* 202 * Enlightened VMCS has been enabled. It does not mean that L1 has to 203 * use it. However, VMX features available to L1 will be limited based 204 * on what the enlightened VMCS supports. 205 */ 206 bool enlightened_vmcs_enabled; 207 208 /* L2 must run next, and mustn't decide to exit to L1. */ 209 bool nested_run_pending; 210 211 /* Pending MTF VM-exit into L1. */ 212 bool mtf_pending; 213 214 struct loaded_vmcs vmcs02; 215 216 /* 217 * Guest pages referred to in the vmcs02 with host-physical 218 * pointers, so we must keep them pinned while L2 runs. 219 */ 220 struct kvm_host_map apic_access_page_map; 221 struct kvm_host_map virtual_apic_map; 222 struct kvm_host_map pi_desc_map; 223 224 struct kvm_host_map msr_bitmap_map; 225 226 struct pi_desc *pi_desc; 227 bool pi_pending; 228 u16 posted_intr_nv; 229 230 struct hrtimer preemption_timer; 231 u64 preemption_timer_deadline; 232 bool has_preemption_timer_deadline; 233 bool preemption_timer_expired; 234 235 /* 236 * Used to snapshot MSRs that are conditionally loaded on VM-Enter in 237 * order to propagate the guest's pre-VM-Enter value into vmcs02. For 238 * emulation of VMLAUNCH/VMRESUME, the snapshot will be of L1's value. 239 * For KVM_SET_NESTED_STATE, the snapshot is of L2's value, _if_ 240 * userspace restores MSRs before nested state. If userspace restores 241 * MSRs after nested state, the snapshot holds garbage, but KVM can't 242 * detect that, and the garbage value in vmcs02 will be overwritten by 243 * MSR restoration in any case. 244 */ 245 u64 pre_vmenter_debugctl; 246 u64 pre_vmenter_bndcfgs; 247 248 /* to migrate it to L1 if L2 writes to L1's CR8 directly */ 249 int l1_tpr_threshold; 250 251 u16 vpid02; 252 u16 last_vpid; 253 254 struct nested_vmx_msrs msrs; 255 256 /* SMM related state */ 257 struct { 258 /* in VMX operation on SMM entry? */ 259 bool vmxon; 260 /* in guest mode on SMM entry? */ 261 bool guest_mode; 262 } smm; 263 264 gpa_t hv_evmcs_vmptr; 265 struct kvm_host_map hv_evmcs_map; 266 struct hv_enlightened_vmcs *hv_evmcs; 267 }; 268 269 struct vcpu_vmx { 270 struct kvm_vcpu vcpu; 271 u8 fail; 272 u8 x2apic_msr_bitmap_mode; 273 274 /* 275 * If true, host state has been stored in vmx->loaded_vmcs for 276 * the CPU registers that only need to be switched when transitioning 277 * to/from the kernel, and the registers have been loaded with guest 278 * values. If false, host state is loaded in the CPU registers 279 * and vmx->loaded_vmcs->host_state is invalid. 280 */ 281 bool guest_state_loaded; 282 283 unsigned long exit_qualification; 284 u32 exit_intr_info; 285 u32 idt_vectoring_info; 286 ulong rflags; 287 288 /* 289 * User return MSRs are always emulated when enabled in the guest, but 290 * only loaded into hardware when necessary, e.g. SYSCALL #UDs outside 291 * of 64-bit mode or if EFER.SCE=1, thus the SYSCALL MSRs don't need to 292 * be loaded into hardware if those conditions aren't met. 293 */ 294 struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS]; 295 bool guest_uret_msrs_loaded; 296 #ifdef CONFIG_X86_64 297 u64 msr_host_kernel_gs_base; 298 u64 msr_guest_kernel_gs_base; 299 #endif 300 301 u64 spec_ctrl; 302 u32 msr_ia32_umwait_control; 303 304 /* 305 * loaded_vmcs points to the VMCS currently used in this vcpu. For a 306 * non-nested (L1) guest, it always points to vmcs01. For a nested 307 * guest (L2), it points to a different VMCS. 308 */ 309 struct loaded_vmcs vmcs01; 310 struct loaded_vmcs *loaded_vmcs; 311 312 struct msr_autoload { 313 struct vmx_msrs guest; 314 struct vmx_msrs host; 315 } msr_autoload; 316 317 struct msr_autostore { 318 struct vmx_msrs guest; 319 } msr_autostore; 320 321 struct { 322 int vm86_active; 323 ulong save_rflags; 324 struct kvm_segment segs[8]; 325 } rmode; 326 struct { 327 u32 bitmask; /* 4 bits per segment (1 bit per field) */ 328 struct kvm_save_segment { 329 u16 selector; 330 unsigned long base; 331 u32 limit; 332 u32 ar; 333 } seg[8]; 334 } segment_cache; 335 int vpid; 336 bool emulation_required; 337 338 union vmx_exit_reason exit_reason; 339 340 /* Posted interrupt descriptor */ 341 struct pi_desc pi_desc; 342 343 /* Used if this vCPU is waiting for PI notification wakeup. */ 344 struct list_head pi_wakeup_list; 345 346 /* Support for a guest hypervisor (nested VMX) */ 347 struct nested_vmx nested; 348 349 /* Dynamic PLE window. */ 350 unsigned int ple_window; 351 bool ple_window_dirty; 352 353 bool req_immediate_exit; 354 355 /* Support for PML */ 356 #define PML_ENTITY_NUM 512 357 struct page *pml_pg; 358 359 /* apic deadline value in host tsc */ 360 u64 hv_deadline_tsc; 361 362 unsigned long host_debugctlmsr; 363 364 /* 365 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in 366 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included 367 * in msr_ia32_feature_control_valid_bits. 368 */ 369 u64 msr_ia32_feature_control; 370 u64 msr_ia32_feature_control_valid_bits; 371 /* SGX Launch Control public key hash */ 372 u64 msr_ia32_sgxlepubkeyhash[4]; 373 u64 msr_ia32_mcu_opt_ctrl; 374 bool disable_fb_clear; 375 376 struct pt_desc pt_desc; 377 struct lbr_desc lbr_desc; 378 379 /* Save desired MSR intercept (read: pass-through) state */ 380 #define MAX_POSSIBLE_PASSTHROUGH_MSRS 15 381 struct { 382 DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS); 383 DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS); 384 } shadow_msr_intercept; 385 }; 386 387 struct kvm_vmx { 388 struct kvm kvm; 389 390 unsigned int tss_addr; 391 bool ept_identity_pagetable_done; 392 gpa_t ept_identity_map_addr; 393 /* Posted Interrupt Descriptor (PID) table for IPI virtualization */ 394 u64 *pid_table; 395 }; 396 397 bool nested_vmx_allowed(struct kvm_vcpu *vcpu); 398 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu, 399 struct loaded_vmcs *buddy); 400 int allocate_vpid(void); 401 void free_vpid(int vpid); 402 void vmx_set_constant_host_state(struct vcpu_vmx *vmx); 403 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu); 404 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 405 unsigned long fs_base, unsigned long gs_base); 406 int vmx_get_cpl(struct kvm_vcpu *vcpu); 407 bool vmx_emulation_required(struct kvm_vcpu *vcpu); 408 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu); 409 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); 410 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu); 411 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask); 412 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer); 413 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 414 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 415 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx); 416 void ept_save_pdptrs(struct kvm_vcpu *vcpu); 417 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 418 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); 419 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level); 420 421 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu); 422 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu); 423 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu); 424 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu); 425 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu); 426 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); 427 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu); 428 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr); 429 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu); 430 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp); 431 void vmx_spec_ctrl_restore_host(struct vcpu_vmx *vmx, unsigned int flags); 432 unsigned int __vmx_vcpu_run_flags(struct vcpu_vmx *vmx); 433 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, 434 unsigned int flags); 435 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr); 436 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu); 437 438 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type); 439 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type); 440 441 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu); 442 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu); 443 444 static inline void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, 445 int type, bool value) 446 { 447 if (value) 448 vmx_enable_intercept_for_msr(vcpu, msr, type); 449 else 450 vmx_disable_intercept_for_msr(vcpu, msr, type); 451 } 452 453 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu); 454 455 /* 456 * Note, early Intel manuals have the write-low and read-high bitmap offsets 457 * the wrong way round. The bitmaps control MSRs 0x00000000-0x00001fff and 458 * 0xc0000000-0xc0001fff. The former (low) uses bytes 0-0x3ff for reads and 459 * 0x800-0xbff for writes. The latter (high) uses 0x400-0x7ff for reads and 460 * 0xc00-0xfff for writes. MSRs not covered by either of the ranges always 461 * VM-Exit. 462 */ 463 #define __BUILD_VMX_MSR_BITMAP_HELPER(rtype, action, bitop, access, base) \ 464 static inline rtype vmx_##action##_msr_bitmap_##access(unsigned long *bitmap, \ 465 u32 msr) \ 466 { \ 467 int f = sizeof(unsigned long); \ 468 \ 469 if (msr <= 0x1fff) \ 470 return bitop##_bit(msr, bitmap + base / f); \ 471 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) \ 472 return bitop##_bit(msr & 0x1fff, bitmap + (base + 0x400) / f); \ 473 return (rtype)true; \ 474 } 475 #define BUILD_VMX_MSR_BITMAP_HELPERS(ret_type, action, bitop) \ 476 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, read, 0x0) \ 477 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 0x800) 478 479 BUILD_VMX_MSR_BITMAP_HELPERS(bool, test, test) 480 BUILD_VMX_MSR_BITMAP_HELPERS(void, clear, __clear) 481 BUILD_VMX_MSR_BITMAP_HELPERS(void, set, __set) 482 483 static inline u8 vmx_get_rvi(void) 484 { 485 return vmcs_read16(GUEST_INTR_STATUS) & 0xff; 486 } 487 488 #define BUILD_CONTROLS_SHADOW(lname, uname, bits) \ 489 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u##bits val) \ 490 { \ 491 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \ 492 vmcs_write##bits(uname, val); \ 493 vmx->loaded_vmcs->controls_shadow.lname = val; \ 494 } \ 495 } \ 496 static inline u##bits __##lname##_controls_get(struct loaded_vmcs *vmcs) \ 497 { \ 498 return vmcs->controls_shadow.lname; \ 499 } \ 500 static inline u##bits lname##_controls_get(struct vcpu_vmx *vmx) \ 501 { \ 502 return __##lname##_controls_get(vmx->loaded_vmcs); \ 503 } \ 504 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u##bits val) \ 505 { \ 506 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \ 507 } \ 508 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u##bits val) \ 509 { \ 510 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \ 511 } 512 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS, 32) 513 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS, 32) 514 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL, 32) 515 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL, 32) 516 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL, 32) 517 BUILD_CONTROLS_SHADOW(tertiary_exec, TERTIARY_VM_EXEC_CONTROL, 64) 518 519 /* 520 * VMX_REGS_LAZY_LOAD_SET - The set of registers that will be updated in the 521 * cache on demand. Other registers not listed here are synced to 522 * the cache immediately after VM-Exit. 523 */ 524 #define VMX_REGS_LAZY_LOAD_SET ((1 << VCPU_REGS_RIP) | \ 525 (1 << VCPU_REGS_RSP) | \ 526 (1 << VCPU_EXREG_RFLAGS) | \ 527 (1 << VCPU_EXREG_PDPTR) | \ 528 (1 << VCPU_EXREG_SEGMENTS) | \ 529 (1 << VCPU_EXREG_CR0) | \ 530 (1 << VCPU_EXREG_CR3) | \ 531 (1 << VCPU_EXREG_CR4) | \ 532 (1 << VCPU_EXREG_EXIT_INFO_1) | \ 533 (1 << VCPU_EXREG_EXIT_INFO_2)) 534 535 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm) 536 { 537 return container_of(kvm, struct kvm_vmx, kvm); 538 } 539 540 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) 541 { 542 return container_of(vcpu, struct vcpu_vmx, vcpu); 543 } 544 545 static inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu) 546 { 547 struct vcpu_vmx *vmx = to_vmx(vcpu); 548 549 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_1)) { 550 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1); 551 vmx->exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 552 } 553 return vmx->exit_qualification; 554 } 555 556 static inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu) 557 { 558 struct vcpu_vmx *vmx = to_vmx(vcpu); 559 560 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_2)) { 561 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2); 562 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 563 } 564 return vmx->exit_intr_info; 565 } 566 567 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags); 568 void free_vmcs(struct vmcs *vmcs); 569 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 570 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs); 571 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs); 572 573 static inline struct vmcs *alloc_vmcs(bool shadow) 574 { 575 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(), 576 GFP_KERNEL_ACCOUNT); 577 } 578 579 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx) 580 { 581 return secondary_exec_controls_get(vmx) & 582 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 583 } 584 585 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu) 586 { 587 if (!enable_ept) 588 return true; 589 590 return allow_smaller_maxphyaddr && cpuid_maxphyaddr(vcpu) < boot_cpu_data.x86_phys_bits; 591 } 592 593 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu) 594 { 595 return enable_unrestricted_guest && (!is_guest_mode(vcpu) || 596 (secondary_exec_controls_get(to_vmx(vcpu)) & 597 SECONDARY_EXEC_UNRESTRICTED_GUEST)); 598 } 599 600 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu); 601 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu) 602 { 603 return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu); 604 } 605 606 void dump_vmcs(struct kvm_vcpu *vcpu); 607 608 static inline int vmx_get_instr_info_reg2(u32 vmx_instr_info) 609 { 610 return (vmx_instr_info >> 28) & 0xf; 611 } 612 613 static inline bool vmx_can_use_ipiv(struct kvm_vcpu *vcpu) 614 { 615 return lapic_in_kernel(vcpu) && enable_ipiv; 616 } 617 618 #endif /* __KVM_X86_VMX_H */ 619