1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_MMU_H 3 #define __KVM_X86_MMU_H 4 5 #include <linux/kvm_host.h> 6 #include "kvm_cache_regs.h" 7 #include "cpuid.h" 8 9 #define PT64_PT_BITS 9 10 #define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS) 11 #define PT32_PT_BITS 10 12 #define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS) 13 14 #define PT_WRITABLE_SHIFT 1 15 #define PT_USER_SHIFT 2 16 17 #define PT_PRESENT_MASK (1ULL << 0) 18 #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT) 19 #define PT_USER_MASK (1ULL << PT_USER_SHIFT) 20 #define PT_PWT_MASK (1ULL << 3) 21 #define PT_PCD_MASK (1ULL << 4) 22 #define PT_ACCESSED_SHIFT 5 23 #define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT) 24 #define PT_DIRTY_SHIFT 6 25 #define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT) 26 #define PT_PAGE_SIZE_SHIFT 7 27 #define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT) 28 #define PT_PAT_MASK (1ULL << 7) 29 #define PT_GLOBAL_MASK (1ULL << 8) 30 #define PT64_NX_SHIFT 63 31 #define PT64_NX_MASK (1ULL << PT64_NX_SHIFT) 32 33 #define PT_PAT_SHIFT 7 34 #define PT_DIR_PAT_SHIFT 12 35 #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT) 36 37 #define PT32_DIR_PSE36_SIZE 4 38 #define PT32_DIR_PSE36_SHIFT 13 39 #define PT32_DIR_PSE36_MASK \ 40 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT) 41 42 #define PT64_ROOT_5LEVEL 5 43 #define PT64_ROOT_4LEVEL 4 44 #define PT32_ROOT_LEVEL 2 45 #define PT32E_ROOT_LEVEL 3 46 47 #define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_LA57 | \ 48 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE) 49 50 #define KVM_MMU_CR0_ROLE_BITS (X86_CR0_PG | X86_CR0_WP) 51 #define KVM_MMU_EFER_ROLE_BITS (EFER_LME | EFER_NX) 52 53 static __always_inline u64 rsvd_bits(int s, int e) 54 { 55 BUILD_BUG_ON(__builtin_constant_p(e) && __builtin_constant_p(s) && e < s); 56 57 if (__builtin_constant_p(e)) 58 BUILD_BUG_ON(e > 63); 59 else 60 e &= 63; 61 62 if (e < s) 63 return 0; 64 65 return ((2ULL << (e - s)) - 1) << s; 66 } 67 68 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask); 69 void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only); 70 71 void kvm_init_mmu(struct kvm_vcpu *vcpu); 72 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0, 73 unsigned long cr4, u64 efer, gpa_t nested_cr3); 74 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, 75 int huge_page_level, bool accessed_dirty, 76 gpa_t new_eptp); 77 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu); 78 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, 79 u64 fault_address, char *insn, int insn_len); 80 81 int kvm_mmu_load(struct kvm_vcpu *vcpu); 82 void kvm_mmu_unload(struct kvm_vcpu *vcpu); 83 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); 84 void kvm_mmu_sync_prev_roots(struct kvm_vcpu *vcpu); 85 86 static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu) 87 { 88 if (likely(vcpu->arch.mmu->root_hpa != INVALID_PAGE)) 89 return 0; 90 91 return kvm_mmu_load(vcpu); 92 } 93 94 static inline unsigned long kvm_get_pcid(struct kvm_vcpu *vcpu, gpa_t cr3) 95 { 96 BUILD_BUG_ON((X86_CR3_PCID_MASK & PAGE_MASK) != 0); 97 98 return kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE) 99 ? cr3 & X86_CR3_PCID_MASK 100 : 0; 101 } 102 103 static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu) 104 { 105 return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu)); 106 } 107 108 static inline void kvm_mmu_load_pgd(struct kvm_vcpu *vcpu) 109 { 110 u64 root_hpa = vcpu->arch.mmu->root_hpa; 111 112 if (!VALID_PAGE(root_hpa)) 113 return; 114 115 static_call(kvm_x86_load_mmu_pgd)(vcpu, root_hpa, 116 vcpu->arch.mmu->shadow_root_level); 117 } 118 119 struct kvm_page_fault { 120 /* arguments to kvm_mmu_do_page_fault. */ 121 const gpa_t addr; 122 const u32 error_code; 123 const bool prefetch; 124 125 /* Derived from error_code. */ 126 const bool exec; 127 const bool write; 128 const bool present; 129 const bool rsvd; 130 const bool user; 131 132 /* Derived from mmu and global state. */ 133 const bool is_tdp; 134 const bool nx_huge_page_workaround_enabled; 135 136 /* 137 * Whether a >4KB mapping can be created or is forbidden due to NX 138 * hugepages. 139 */ 140 bool huge_page_disallowed; 141 142 /* 143 * Maximum page size that can be created for this fault; input to 144 * FNAME(fetch), __direct_map and kvm_tdp_mmu_map. 145 */ 146 u8 max_level; 147 148 /* 149 * Page size that can be created based on the max_level and the 150 * page size used by the host mapping. 151 */ 152 u8 req_level; 153 154 /* 155 * Page size that will be created based on the req_level and 156 * huge_page_disallowed. 157 */ 158 u8 goal_level; 159 160 /* Shifted addr, or result of guest page table walk if addr is a gva. */ 161 gfn_t gfn; 162 163 /* The memslot containing gfn. May be NULL. */ 164 struct kvm_memory_slot *slot; 165 166 /* Outputs of kvm_faultin_pfn. */ 167 kvm_pfn_t pfn; 168 hva_t hva; 169 bool map_writable; 170 }; 171 172 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault); 173 174 extern int nx_huge_pages; 175 static inline bool is_nx_huge_page_enabled(void) 176 { 177 return READ_ONCE(nx_huge_pages); 178 } 179 180 static inline int kvm_mmu_do_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 181 u32 err, bool prefetch) 182 { 183 struct kvm_page_fault fault = { 184 .addr = cr2_or_gpa, 185 .error_code = err, 186 .exec = err & PFERR_FETCH_MASK, 187 .write = err & PFERR_WRITE_MASK, 188 .present = err & PFERR_PRESENT_MASK, 189 .rsvd = err & PFERR_RSVD_MASK, 190 .user = err & PFERR_USER_MASK, 191 .prefetch = prefetch, 192 .is_tdp = likely(vcpu->arch.mmu->page_fault == kvm_tdp_page_fault), 193 .nx_huge_page_workaround_enabled = is_nx_huge_page_enabled(), 194 195 .max_level = KVM_MAX_HUGEPAGE_LEVEL, 196 .req_level = PG_LEVEL_4K, 197 .goal_level = PG_LEVEL_4K, 198 }; 199 #ifdef CONFIG_RETPOLINE 200 if (fault.is_tdp) 201 return kvm_tdp_page_fault(vcpu, &fault); 202 #endif 203 return vcpu->arch.mmu->page_fault(vcpu, &fault); 204 } 205 206 /* 207 * Check if a given access (described through the I/D, W/R and U/S bits of a 208 * page fault error code pfec) causes a permission fault with the given PTE 209 * access rights (in ACC_* format). 210 * 211 * Return zero if the access does not fault; return the page fault error code 212 * if the access faults. 213 */ 214 static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 215 unsigned pte_access, unsigned pte_pkey, 216 unsigned pfec) 217 { 218 int cpl = static_call(kvm_x86_get_cpl)(vcpu); 219 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); 220 221 /* 222 * If CPL < 3, SMAP prevention are disabled if EFLAGS.AC = 1. 223 * 224 * If CPL = 3, SMAP applies to all supervisor-mode data accesses 225 * (these are implicit supervisor accesses) regardless of the value 226 * of EFLAGS.AC. 227 * 228 * This computes (cpl < 3) && (rflags & X86_EFLAGS_AC), leaving 229 * the result in X86_EFLAGS_AC. We then insert it in place of 230 * the PFERR_RSVD_MASK bit; this bit will always be zero in pfec, 231 * but it will be one in index if SMAP checks are being overridden. 232 * It is important to keep this branchless. 233 */ 234 unsigned long smap = (cpl - 3) & (rflags & X86_EFLAGS_AC); 235 int index = (pfec >> 1) + 236 (smap >> (X86_EFLAGS_AC_BIT - PFERR_RSVD_BIT + 1)); 237 bool fault = (mmu->permissions[index] >> pte_access) & 1; 238 u32 errcode = PFERR_PRESENT_MASK; 239 240 WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK)); 241 if (unlikely(mmu->pkru_mask)) { 242 u32 pkru_bits, offset; 243 244 /* 245 * PKRU defines 32 bits, there are 16 domains and 2 246 * attribute bits per domain in pkru. pte_pkey is the 247 * index of the protection domain, so pte_pkey * 2 is 248 * is the index of the first bit for the domain. 249 */ 250 pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3; 251 252 /* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */ 253 offset = (pfec & ~1) + 254 ((pte_access & PT_USER_MASK) << (PFERR_RSVD_BIT - PT_USER_SHIFT)); 255 256 pkru_bits &= mmu->pkru_mask >> offset; 257 errcode |= -pkru_bits & PFERR_PK_MASK; 258 fault |= (pkru_bits != 0); 259 } 260 261 return -(u32)fault & errcode; 262 } 263 264 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end); 265 266 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu); 267 268 int kvm_mmu_post_init_vm(struct kvm *kvm); 269 void kvm_mmu_pre_destroy_vm(struct kvm *kvm); 270 271 static inline bool kvm_shadow_root_allocated(struct kvm *kvm) 272 { 273 /* 274 * Read shadow_root_allocated before related pointers. Hence, threads 275 * reading shadow_root_allocated in any lock context are guaranteed to 276 * see the pointers. Pairs with smp_store_release in 277 * mmu_first_shadow_root_alloc. 278 */ 279 return smp_load_acquire(&kvm->arch.shadow_root_allocated); 280 } 281 282 #ifdef CONFIG_X86_64 283 static inline bool is_tdp_mmu_enabled(struct kvm *kvm) { return kvm->arch.tdp_mmu_enabled; } 284 #else 285 static inline bool is_tdp_mmu_enabled(struct kvm *kvm) { return false; } 286 #endif 287 288 static inline bool kvm_memslots_have_rmaps(struct kvm *kvm) 289 { 290 return !is_tdp_mmu_enabled(kvm) || kvm_shadow_root_allocated(kvm); 291 } 292 293 static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) 294 { 295 /* KVM_HPAGE_GFN_SHIFT(PG_LEVEL_4K) must be 0. */ 296 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - 297 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); 298 } 299 300 static inline unsigned long 301 __kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, unsigned long npages, 302 int level) 303 { 304 return gfn_to_index(slot->base_gfn + npages - 1, 305 slot->base_gfn, level) + 1; 306 } 307 308 static inline unsigned long 309 kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, int level) 310 { 311 return __kvm_mmu_slot_lpages(slot, slot->npages, level); 312 } 313 314 static inline void kvm_update_page_stats(struct kvm *kvm, int level, int count) 315 { 316 atomic64_add(count, &kvm->stat.pages[level - 1]); 317 } 318 319 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, 320 struct x86_exception *exception); 321 322 static inline gpa_t kvm_translate_gpa(struct kvm_vcpu *vcpu, 323 struct kvm_mmu *mmu, 324 gpa_t gpa, u32 access, 325 struct x86_exception *exception) 326 { 327 if (mmu != &vcpu->arch.nested_mmu) 328 return gpa; 329 return translate_nested_gpa(vcpu, gpa, access, exception); 330 } 331 #endif 332