1 #ifndef __KVM_X86_LAPIC_H 2 #define __KVM_X86_LAPIC_H 3 4 #include "iodev.h" 5 6 #include <linux/kvm_host.h> 7 8 #define KVM_APIC_INIT 0 9 #define KVM_APIC_SIPI 1 10 11 struct kvm_timer { 12 struct hrtimer timer; 13 s64 period; /* unit: ns */ 14 u32 timer_mode_mask; 15 u64 tscdeadline; 16 atomic_t pending; /* accumulated triggered timers */ 17 }; 18 19 struct kvm_lapic { 20 unsigned long base_address; 21 struct kvm_io_device dev; 22 struct kvm_timer lapic_timer; 23 u32 divide_count; 24 struct kvm_vcpu *vcpu; 25 bool sw_enabled; 26 bool irr_pending; 27 /* Number of bits set in ISR. */ 28 s16 isr_count; 29 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */ 30 int highest_isr_cache; 31 /** 32 * APIC register page. The layout matches the register layout seen by 33 * the guest 1:1, because it is accessed by the vmx microcode. 34 * Note: Only one register, the TPR, is used by the microcode. 35 */ 36 void *regs; 37 gpa_t vapic_addr; 38 struct gfn_to_hva_cache vapic_cache; 39 unsigned long pending_events; 40 unsigned int sipi_vector; 41 }; 42 int kvm_create_lapic(struct kvm_vcpu *vcpu); 43 void kvm_free_lapic(struct kvm_vcpu *vcpu); 44 45 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu); 46 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu); 47 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu); 48 void kvm_apic_accept_events(struct kvm_vcpu *vcpu); 49 void kvm_lapic_reset(struct kvm_vcpu *vcpu); 50 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu); 51 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8); 52 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu); 53 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value); 54 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu); 55 void kvm_apic_set_version(struct kvm_vcpu *vcpu); 56 57 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr); 58 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir); 59 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest); 60 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda); 61 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, 62 unsigned long *dest_map); 63 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type); 64 65 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, 66 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map); 67 68 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu); 69 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 70 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, 71 struct kvm_lapic_state *s); 72 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu); 73 74 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu); 75 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data); 76 77 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset); 78 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector); 79 80 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr); 81 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu); 82 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu); 83 84 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 85 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 86 87 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 88 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 89 90 static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu) 91 { 92 return vcpu->arch.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE; 93 } 94 95 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data); 96 void kvm_lapic_init(void); 97 98 static inline u32 kvm_apic_get_reg(struct kvm_lapic *apic, int reg_off) 99 { 100 return *((u32 *) (apic->regs + reg_off)); 101 } 102 103 extern struct static_key kvm_no_apic_vcpu; 104 105 static inline bool kvm_vcpu_has_lapic(struct kvm_vcpu *vcpu) 106 { 107 if (static_key_false(&kvm_no_apic_vcpu)) 108 return vcpu->arch.apic; 109 return true; 110 } 111 112 extern struct static_key_deferred apic_hw_disabled; 113 114 static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic) 115 { 116 if (static_key_false(&apic_hw_disabled.key)) 117 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; 118 return MSR_IA32_APICBASE_ENABLE; 119 } 120 121 extern struct static_key_deferred apic_sw_disabled; 122 123 static inline int kvm_apic_sw_enabled(struct kvm_lapic *apic) 124 { 125 if (static_key_false(&apic_sw_disabled.key)) 126 return kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED; 127 return APIC_SPIV_APIC_ENABLED; 128 } 129 130 static inline bool kvm_apic_present(struct kvm_vcpu *vcpu) 131 { 132 return kvm_vcpu_has_lapic(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic); 133 } 134 135 static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu) 136 { 137 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic); 138 } 139 140 static inline int apic_x2apic_mode(struct kvm_lapic *apic) 141 { 142 return apic->vcpu->arch.apic_base & X2APIC_ENABLE; 143 } 144 145 static inline bool kvm_apic_vid_enabled(struct kvm *kvm) 146 { 147 return kvm_x86_ops->vm_has_apicv(kvm); 148 } 149 150 static inline u16 apic_cluster_id(struct kvm_apic_map *map, u32 ldr) 151 { 152 u16 cid; 153 ldr >>= 32 - map->ldr_bits; 154 cid = (ldr >> map->cid_shift) & map->cid_mask; 155 156 BUG_ON(cid >= ARRAY_SIZE(map->logical_map)); 157 158 return cid; 159 } 160 161 static inline u16 apic_logical_id(struct kvm_apic_map *map, u32 ldr) 162 { 163 ldr >>= (32 - map->ldr_bits); 164 return ldr & map->lid_mask; 165 } 166 167 static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu) 168 { 169 return vcpu->arch.apic->pending_events; 170 } 171 172 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector); 173 174 #endif 175