1 #ifndef __KVM_X86_LAPIC_H 2 #define __KVM_X86_LAPIC_H 3 4 #include <kvm/iodev.h> 5 6 #include <linux/kvm_host.h> 7 8 #define KVM_APIC_INIT 0 9 #define KVM_APIC_SIPI 1 10 #define KVM_APIC_LVT_NUM 6 11 12 struct kvm_timer { 13 struct hrtimer timer; 14 s64 period; /* unit: ns */ 15 u32 timer_mode; 16 u32 timer_mode_mask; 17 u64 tscdeadline; 18 u64 expired_tscdeadline; 19 atomic_t pending; /* accumulated triggered timers */ 20 }; 21 22 struct kvm_lapic { 23 unsigned long base_address; 24 struct kvm_io_device dev; 25 struct kvm_timer lapic_timer; 26 u32 divide_count; 27 struct kvm_vcpu *vcpu; 28 bool sw_enabled; 29 bool irr_pending; 30 bool lvt0_in_nmi_mode; 31 /* Number of bits set in ISR. */ 32 s16 isr_count; 33 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */ 34 int highest_isr_cache; 35 /** 36 * APIC register page. The layout matches the register layout seen by 37 * the guest 1:1, because it is accessed by the vmx microcode. 38 * Note: Only one register, the TPR, is used by the microcode. 39 */ 40 void *regs; 41 gpa_t vapic_addr; 42 struct gfn_to_hva_cache vapic_cache; 43 unsigned long pending_events; 44 unsigned int sipi_vector; 45 }; 46 47 struct dest_map; 48 49 int kvm_create_lapic(struct kvm_vcpu *vcpu); 50 void kvm_free_lapic(struct kvm_vcpu *vcpu); 51 52 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu); 53 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu); 54 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu); 55 void kvm_apic_accept_events(struct kvm_vcpu *vcpu); 56 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event); 57 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu); 58 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8); 59 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu); 60 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value); 61 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu); 62 void kvm_apic_set_version(struct kvm_vcpu *vcpu); 63 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val); 64 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, 65 void *data); 66 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, 67 int short_hand, unsigned int dest, int dest_mode); 68 69 void __kvm_apic_update_irr(u32 *pir, void *regs); 70 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir); 71 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, 72 struct dest_map *dest_map); 73 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type); 74 75 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, 76 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map); 77 78 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu); 79 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 80 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, 81 struct kvm_lapic_state *s); 82 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu); 83 84 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu); 85 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data); 86 87 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset); 88 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector); 89 90 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr); 91 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu); 92 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu); 93 94 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 95 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 96 97 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 98 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 99 100 static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu) 101 { 102 return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE; 103 } 104 105 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data); 106 void kvm_lapic_init(void); 107 108 #define VEC_POS(v) ((v) & (32 - 1)) 109 #define REG_POS(v) (((v) >> 5) << 4) 110 111 static inline void kvm_lapic_set_vector(int vec, void *bitmap) 112 { 113 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 114 } 115 116 static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic) 117 { 118 kvm_lapic_set_vector(vec, apic->regs + APIC_IRR); 119 /* 120 * irr_pending must be true if any interrupt is pending; set it after 121 * APIC_IRR to avoid race with apic_clear_irr 122 */ 123 apic->irr_pending = true; 124 } 125 126 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) 127 { 128 return *((u32 *) (apic->regs + reg_off)); 129 } 130 131 static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) 132 { 133 *((u32 *) (apic->regs + reg_off)) = val; 134 } 135 136 extern struct static_key kvm_no_apic_vcpu; 137 138 static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu) 139 { 140 if (static_key_false(&kvm_no_apic_vcpu)) 141 return vcpu->arch.apic; 142 return true; 143 } 144 145 extern struct static_key_deferred apic_hw_disabled; 146 147 static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic) 148 { 149 if (static_key_false(&apic_hw_disabled.key)) 150 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; 151 return MSR_IA32_APICBASE_ENABLE; 152 } 153 154 extern struct static_key_deferred apic_sw_disabled; 155 156 static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic) 157 { 158 if (static_key_false(&apic_sw_disabled.key)) 159 return apic->sw_enabled; 160 return true; 161 } 162 163 static inline bool kvm_apic_present(struct kvm_vcpu *vcpu) 164 { 165 return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic); 166 } 167 168 static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu) 169 { 170 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic); 171 } 172 173 static inline int apic_x2apic_mode(struct kvm_lapic *apic) 174 { 175 return apic->vcpu->arch.apic_base & X2APIC_ENABLE; 176 } 177 178 static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu) 179 { 180 return vcpu->arch.apic && vcpu->arch.apicv_active; 181 } 182 183 static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu) 184 { 185 return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events; 186 } 187 188 static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq) 189 { 190 return (irq->delivery_mode == APIC_DM_LOWEST || 191 irq->msi_redir_hint); 192 } 193 194 static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu) 195 { 196 return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 197 } 198 199 static inline int kvm_apic_id(struct kvm_lapic *apic) 200 { 201 return (kvm_lapic_get_reg(apic, APIC_ID) >> 24) & 0xff; 202 } 203 204 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector); 205 206 void wait_lapic_expire(struct kvm_vcpu *vcpu); 207 208 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq, 209 struct kvm_vcpu **dest_vcpu); 210 int kvm_vector_to_index(u32 vector, u32 dest_vcpus, 211 const unsigned long *bitmap, u32 bitmap_size); 212 #endif 213