1 #ifndef __KVM_X86_LAPIC_H 2 #define __KVM_X86_LAPIC_H 3 4 #include "iodev.h" 5 6 #include <linux/kvm_host.h> 7 8 #define KVM_APIC_INIT 0 9 #define KVM_APIC_SIPI 1 10 11 struct kvm_timer { 12 struct hrtimer timer; 13 s64 period; /* unit: ns */ 14 u32 timer_mode; 15 u32 timer_mode_mask; 16 u64 tscdeadline; 17 u64 expired_tscdeadline; 18 atomic_t pending; /* accumulated triggered timers */ 19 }; 20 21 struct kvm_lapic { 22 unsigned long base_address; 23 struct kvm_io_device dev; 24 struct kvm_timer lapic_timer; 25 u32 divide_count; 26 struct kvm_vcpu *vcpu; 27 bool sw_enabled; 28 bool irr_pending; 29 /* Number of bits set in ISR. */ 30 s16 isr_count; 31 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */ 32 int highest_isr_cache; 33 /** 34 * APIC register page. The layout matches the register layout seen by 35 * the guest 1:1, because it is accessed by the vmx microcode. 36 * Note: Only one register, the TPR, is used by the microcode. 37 */ 38 void *regs; 39 gpa_t vapic_addr; 40 struct gfn_to_hva_cache vapic_cache; 41 unsigned long pending_events; 42 unsigned int sipi_vector; 43 }; 44 int kvm_create_lapic(struct kvm_vcpu *vcpu); 45 void kvm_free_lapic(struct kvm_vcpu *vcpu); 46 47 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu); 48 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu); 49 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu); 50 void kvm_apic_accept_events(struct kvm_vcpu *vcpu); 51 void kvm_lapic_reset(struct kvm_vcpu *vcpu); 52 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu); 53 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8); 54 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu); 55 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value); 56 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu); 57 void kvm_apic_set_version(struct kvm_vcpu *vcpu); 58 59 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr); 60 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir); 61 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest); 62 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda); 63 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, 64 unsigned long *dest_map); 65 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type); 66 67 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, 68 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map); 69 70 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu); 71 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 72 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, 73 struct kvm_lapic_state *s); 74 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu); 75 76 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu); 77 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data); 78 79 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset); 80 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector); 81 82 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr); 83 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu); 84 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu); 85 86 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 87 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 88 89 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 90 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 91 92 static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu) 93 { 94 return vcpu->arch.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE; 95 } 96 97 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data); 98 void kvm_lapic_init(void); 99 100 static inline u32 kvm_apic_get_reg(struct kvm_lapic *apic, int reg_off) 101 { 102 return *((u32 *) (apic->regs + reg_off)); 103 } 104 105 extern struct static_key kvm_no_apic_vcpu; 106 107 static inline bool kvm_vcpu_has_lapic(struct kvm_vcpu *vcpu) 108 { 109 if (static_key_false(&kvm_no_apic_vcpu)) 110 return vcpu->arch.apic; 111 return true; 112 } 113 114 extern struct static_key_deferred apic_hw_disabled; 115 116 static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic) 117 { 118 if (static_key_false(&apic_hw_disabled.key)) 119 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; 120 return MSR_IA32_APICBASE_ENABLE; 121 } 122 123 extern struct static_key_deferred apic_sw_disabled; 124 125 static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic) 126 { 127 if (static_key_false(&apic_sw_disabled.key)) 128 return apic->sw_enabled; 129 return true; 130 } 131 132 static inline bool kvm_apic_present(struct kvm_vcpu *vcpu) 133 { 134 return kvm_vcpu_has_lapic(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic); 135 } 136 137 static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu) 138 { 139 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic); 140 } 141 142 static inline int apic_x2apic_mode(struct kvm_lapic *apic) 143 { 144 return apic->vcpu->arch.apic_base & X2APIC_ENABLE; 145 } 146 147 static inline bool kvm_apic_vid_enabled(struct kvm *kvm) 148 { 149 return kvm_x86_ops->vm_has_apicv(kvm); 150 } 151 152 static inline u16 apic_cluster_id(struct kvm_apic_map *map, u32 ldr) 153 { 154 u16 cid; 155 ldr >>= 32 - map->ldr_bits; 156 cid = (ldr >> map->cid_shift) & map->cid_mask; 157 158 return cid; 159 } 160 161 static inline u16 apic_logical_id(struct kvm_apic_map *map, u32 ldr) 162 { 163 ldr >>= (32 - map->ldr_bits); 164 return ldr & map->lid_mask; 165 } 166 167 static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu) 168 { 169 return vcpu->arch.apic->pending_events; 170 } 171 172 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector); 173 174 void wait_lapic_expire(struct kvm_vcpu *vcpu); 175 176 #endif 177