1 2 /* 3 * Local APIC virtualization 4 * 5 * Copyright (C) 2006 Qumranet, Inc. 6 * Copyright (C) 2007 Novell 7 * Copyright (C) 2007 Intel 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Dor Laor <dor.laor@qumranet.com> 12 * Gregory Haskins <ghaskins@novell.com> 13 * Yaozu (Eddie) Dong <eddie.dong@intel.com> 14 * 15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 */ 20 21 #include <linux/kvm_host.h> 22 #include <linux/kvm.h> 23 #include <linux/mm.h> 24 #include <linux/highmem.h> 25 #include <linux/smp.h> 26 #include <linux/hrtimer.h> 27 #include <linux/io.h> 28 #include <linux/module.h> 29 #include <linux/math64.h> 30 #include <linux/slab.h> 31 #include <asm/processor.h> 32 #include <asm/msr.h> 33 #include <asm/page.h> 34 #include <asm/current.h> 35 #include <asm/apicdef.h> 36 #include <linux/atomic.h> 37 #include <linux/jump_label.h> 38 #include "kvm_cache_regs.h" 39 #include "irq.h" 40 #include "trace.h" 41 #include "x86.h" 42 #include "cpuid.h" 43 44 #ifndef CONFIG_X86_64 45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) 46 #else 47 #define mod_64(x, y) ((x) % (y)) 48 #endif 49 50 #define PRId64 "d" 51 #define PRIx64 "llx" 52 #define PRIu64 "u" 53 #define PRIo64 "o" 54 55 #define APIC_BUS_CYCLE_NS 1 56 57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ 58 #define apic_debug(fmt, arg...) 59 60 #define APIC_LVT_NUM 6 61 /* 14 is the version for Xeon and Pentium 8.4.8*/ 62 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16)) 63 #define LAPIC_MMIO_LENGTH (1 << 12) 64 /* followed define is not in apicdef.h */ 65 #define APIC_SHORT_MASK 0xc0000 66 #define APIC_DEST_NOSHORT 0x0 67 #define APIC_DEST_MASK 0x800 68 #define MAX_APIC_VECTOR 256 69 #define APIC_VECTORS_PER_REG 32 70 71 #define APIC_BROADCAST 0xFF 72 #define X2APIC_BROADCAST 0xFFFFFFFFul 73 74 #define VEC_POS(v) ((v) & (32 - 1)) 75 #define REG_POS(v) (((v) >> 5) << 4) 76 77 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) 78 { 79 *((u32 *) (apic->regs + reg_off)) = val; 80 } 81 82 static inline int apic_test_vector(int vec, void *bitmap) 83 { 84 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 85 } 86 87 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector) 88 { 89 struct kvm_lapic *apic = vcpu->arch.apic; 90 91 return apic_test_vector(vector, apic->regs + APIC_ISR) || 92 apic_test_vector(vector, apic->regs + APIC_IRR); 93 } 94 95 static inline void apic_set_vector(int vec, void *bitmap) 96 { 97 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 98 } 99 100 static inline void apic_clear_vector(int vec, void *bitmap) 101 { 102 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 103 } 104 105 static inline int __apic_test_and_set_vector(int vec, void *bitmap) 106 { 107 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 108 } 109 110 static inline int __apic_test_and_clear_vector(int vec, void *bitmap) 111 { 112 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 113 } 114 115 struct static_key_deferred apic_hw_disabled __read_mostly; 116 struct static_key_deferred apic_sw_disabled __read_mostly; 117 118 static inline int apic_enabled(struct kvm_lapic *apic) 119 { 120 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); 121 } 122 123 #define LVT_MASK \ 124 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) 125 126 #define LINT_MASK \ 127 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ 128 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) 129 130 static inline int kvm_apic_id(struct kvm_lapic *apic) 131 { 132 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff; 133 } 134 135 #define KVM_X2APIC_CID_BITS 0 136 137 static void recalculate_apic_map(struct kvm *kvm) 138 { 139 struct kvm_apic_map *new, *old = NULL; 140 struct kvm_vcpu *vcpu; 141 int i; 142 143 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL); 144 145 mutex_lock(&kvm->arch.apic_map_lock); 146 147 if (!new) 148 goto out; 149 150 new->ldr_bits = 8; 151 /* flat mode is default */ 152 new->cid_shift = 8; 153 new->cid_mask = 0; 154 new->lid_mask = 0xff; 155 new->broadcast = APIC_BROADCAST; 156 157 kvm_for_each_vcpu(i, vcpu, kvm) { 158 struct kvm_lapic *apic = vcpu->arch.apic; 159 u16 cid, lid; 160 u32 ldr; 161 162 if (!kvm_apic_present(vcpu)) 163 continue; 164 165 /* 166 * All APICs have to be configured in the same mode by an OS. 167 * We take advatage of this while building logical id loockup 168 * table. After reset APICs are in xapic/flat mode, so if we 169 * find apic with different setting we assume this is the mode 170 * OS wants all apics to be in; build lookup table accordingly. 171 */ 172 if (apic_x2apic_mode(apic)) { 173 new->ldr_bits = 32; 174 new->cid_shift = 16; 175 new->cid_mask = (1 << KVM_X2APIC_CID_BITS) - 1; 176 new->lid_mask = 0xffff; 177 new->broadcast = X2APIC_BROADCAST; 178 } else if (kvm_apic_sw_enabled(apic) && 179 !new->cid_mask /* flat mode */ && 180 kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_CLUSTER) { 181 new->cid_shift = 4; 182 new->cid_mask = 0xf; 183 new->lid_mask = 0xf; 184 } 185 186 new->phys_map[kvm_apic_id(apic)] = apic; 187 188 ldr = kvm_apic_get_reg(apic, APIC_LDR); 189 cid = apic_cluster_id(new, ldr); 190 lid = apic_logical_id(new, ldr); 191 192 if (lid) 193 new->logical_map[cid][ffs(lid) - 1] = apic; 194 } 195 out: 196 old = rcu_dereference_protected(kvm->arch.apic_map, 197 lockdep_is_held(&kvm->arch.apic_map_lock)); 198 rcu_assign_pointer(kvm->arch.apic_map, new); 199 mutex_unlock(&kvm->arch.apic_map_lock); 200 201 if (old) 202 kfree_rcu(old, rcu); 203 204 kvm_vcpu_request_scan_ioapic(kvm); 205 } 206 207 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) 208 { 209 u32 prev = kvm_apic_get_reg(apic, APIC_SPIV); 210 211 apic_set_reg(apic, APIC_SPIV, val); 212 if ((prev ^ val) & APIC_SPIV_APIC_ENABLED) { 213 if (val & APIC_SPIV_APIC_ENABLED) { 214 static_key_slow_dec_deferred(&apic_sw_disabled); 215 recalculate_apic_map(apic->vcpu->kvm); 216 } else 217 static_key_slow_inc(&apic_sw_disabled.key); 218 } 219 } 220 221 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id) 222 { 223 apic_set_reg(apic, APIC_ID, id << 24); 224 recalculate_apic_map(apic->vcpu->kvm); 225 } 226 227 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) 228 { 229 apic_set_reg(apic, APIC_LDR, id); 230 recalculate_apic_map(apic->vcpu->kvm); 231 } 232 233 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) 234 { 235 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); 236 } 237 238 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) 239 { 240 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; 241 } 242 243 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) 244 { 245 return ((kvm_apic_get_reg(apic, APIC_LVTT) & 246 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT); 247 } 248 249 static inline int apic_lvtt_period(struct kvm_lapic *apic) 250 { 251 return ((kvm_apic_get_reg(apic, APIC_LVTT) & 252 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC); 253 } 254 255 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) 256 { 257 return ((kvm_apic_get_reg(apic, APIC_LVTT) & 258 apic->lapic_timer.timer_mode_mask) == 259 APIC_LVT_TIMER_TSCDEADLINE); 260 } 261 262 static inline int apic_lvt_nmi_mode(u32 lvt_val) 263 { 264 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; 265 } 266 267 void kvm_apic_set_version(struct kvm_vcpu *vcpu) 268 { 269 struct kvm_lapic *apic = vcpu->arch.apic; 270 struct kvm_cpuid_entry2 *feat; 271 u32 v = APIC_VERSION; 272 273 if (!kvm_vcpu_has_lapic(vcpu)) 274 return; 275 276 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0); 277 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31)))) 278 v |= APIC_LVR_DIRECTED_EOI; 279 apic_set_reg(apic, APIC_LVR, v); 280 } 281 282 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = { 283 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */ 284 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ 285 LVT_MASK | APIC_MODE_MASK, /* LVTPC */ 286 LINT_MASK, LINT_MASK, /* LVT0-1 */ 287 LVT_MASK /* LVTERR */ 288 }; 289 290 static int find_highest_vector(void *bitmap) 291 { 292 int vec; 293 u32 *reg; 294 295 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; 296 vec >= 0; vec -= APIC_VECTORS_PER_REG) { 297 reg = bitmap + REG_POS(vec); 298 if (*reg) 299 return fls(*reg) - 1 + vec; 300 } 301 302 return -1; 303 } 304 305 static u8 count_vectors(void *bitmap) 306 { 307 int vec; 308 u32 *reg; 309 u8 count = 0; 310 311 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) { 312 reg = bitmap + REG_POS(vec); 313 count += hweight32(*reg); 314 } 315 316 return count; 317 } 318 319 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir) 320 { 321 u32 i, pir_val; 322 struct kvm_lapic *apic = vcpu->arch.apic; 323 324 for (i = 0; i <= 7; i++) { 325 pir_val = xchg(&pir[i], 0); 326 if (pir_val) 327 *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val; 328 } 329 } 330 EXPORT_SYMBOL_GPL(kvm_apic_update_irr); 331 332 static inline void apic_set_irr(int vec, struct kvm_lapic *apic) 333 { 334 apic->irr_pending = true; 335 apic_set_vector(vec, apic->regs + APIC_IRR); 336 } 337 338 static inline int apic_search_irr(struct kvm_lapic *apic) 339 { 340 return find_highest_vector(apic->regs + APIC_IRR); 341 } 342 343 static inline int apic_find_highest_irr(struct kvm_lapic *apic) 344 { 345 int result; 346 347 /* 348 * Note that irr_pending is just a hint. It will be always 349 * true with virtual interrupt delivery enabled. 350 */ 351 if (!apic->irr_pending) 352 return -1; 353 354 kvm_x86_ops->sync_pir_to_irr(apic->vcpu); 355 result = apic_search_irr(apic); 356 ASSERT(result == -1 || result >= 16); 357 358 return result; 359 } 360 361 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) 362 { 363 struct kvm_vcpu *vcpu; 364 365 vcpu = apic->vcpu; 366 367 apic_clear_vector(vec, apic->regs + APIC_IRR); 368 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) 369 /* try to update RVI */ 370 kvm_make_request(KVM_REQ_EVENT, vcpu); 371 else { 372 vec = apic_search_irr(apic); 373 apic->irr_pending = (vec != -1); 374 } 375 } 376 377 static inline void apic_set_isr(int vec, struct kvm_lapic *apic) 378 { 379 struct kvm_vcpu *vcpu; 380 381 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) 382 return; 383 384 vcpu = apic->vcpu; 385 386 /* 387 * With APIC virtualization enabled, all caching is disabled 388 * because the processor can modify ISR under the hood. Instead 389 * just set SVI. 390 */ 391 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) 392 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec); 393 else { 394 ++apic->isr_count; 395 BUG_ON(apic->isr_count > MAX_APIC_VECTOR); 396 /* 397 * ISR (in service register) bit is set when injecting an interrupt. 398 * The highest vector is injected. Thus the latest bit set matches 399 * the highest bit in ISR. 400 */ 401 apic->highest_isr_cache = vec; 402 } 403 } 404 405 static inline int apic_find_highest_isr(struct kvm_lapic *apic) 406 { 407 int result; 408 409 /* 410 * Note that isr_count is always 1, and highest_isr_cache 411 * is always -1, with APIC virtualization enabled. 412 */ 413 if (!apic->isr_count) 414 return -1; 415 if (likely(apic->highest_isr_cache != -1)) 416 return apic->highest_isr_cache; 417 418 result = find_highest_vector(apic->regs + APIC_ISR); 419 ASSERT(result == -1 || result >= 16); 420 421 return result; 422 } 423 424 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) 425 { 426 struct kvm_vcpu *vcpu; 427 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) 428 return; 429 430 vcpu = apic->vcpu; 431 432 /* 433 * We do get here for APIC virtualization enabled if the guest 434 * uses the Hyper-V APIC enlightenment. In this case we may need 435 * to trigger a new interrupt delivery by writing the SVI field; 436 * on the other hand isr_count and highest_isr_cache are unused 437 * and must be left alone. 438 */ 439 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) 440 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, 441 apic_find_highest_isr(apic)); 442 else { 443 --apic->isr_count; 444 BUG_ON(apic->isr_count < 0); 445 apic->highest_isr_cache = -1; 446 } 447 } 448 449 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) 450 { 451 int highest_irr; 452 453 /* This may race with setting of irr in __apic_accept_irq() and 454 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq 455 * will cause vmexit immediately and the value will be recalculated 456 * on the next vmentry. 457 */ 458 if (!kvm_vcpu_has_lapic(vcpu)) 459 return 0; 460 highest_irr = apic_find_highest_irr(vcpu->arch.apic); 461 462 return highest_irr; 463 } 464 465 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, 466 int vector, int level, int trig_mode, 467 unsigned long *dest_map); 468 469 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, 470 unsigned long *dest_map) 471 { 472 struct kvm_lapic *apic = vcpu->arch.apic; 473 474 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, 475 irq->level, irq->trig_mode, dest_map); 476 } 477 478 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val) 479 { 480 481 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, 482 sizeof(val)); 483 } 484 485 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val) 486 { 487 488 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, 489 sizeof(*val)); 490 } 491 492 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu) 493 { 494 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED; 495 } 496 497 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu) 498 { 499 u8 val; 500 if (pv_eoi_get_user(vcpu, &val) < 0) 501 apic_debug("Can't read EOI MSR value: 0x%llx\n", 502 (unsigned long long)vcpu->arch.pv_eoi.msr_val); 503 return val & 0x1; 504 } 505 506 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu) 507 { 508 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) { 509 apic_debug("Can't set EOI MSR value: 0x%llx\n", 510 (unsigned long long)vcpu->arch.pv_eoi.msr_val); 511 return; 512 } 513 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); 514 } 515 516 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu) 517 { 518 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) { 519 apic_debug("Can't clear EOI MSR value: 0x%llx\n", 520 (unsigned long long)vcpu->arch.pv_eoi.msr_val); 521 return; 522 } 523 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); 524 } 525 526 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr) 527 { 528 struct kvm_lapic *apic = vcpu->arch.apic; 529 int i; 530 531 for (i = 0; i < 8; i++) 532 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]); 533 } 534 535 static void apic_update_ppr(struct kvm_lapic *apic) 536 { 537 u32 tpr, isrv, ppr, old_ppr; 538 int isr; 539 540 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI); 541 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI); 542 isr = apic_find_highest_isr(apic); 543 isrv = (isr != -1) ? isr : 0; 544 545 if ((tpr & 0xf0) >= (isrv & 0xf0)) 546 ppr = tpr & 0xff; 547 else 548 ppr = isrv & 0xf0; 549 550 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", 551 apic, ppr, isr, isrv); 552 553 if (old_ppr != ppr) { 554 apic_set_reg(apic, APIC_PROCPRI, ppr); 555 if (ppr < old_ppr) 556 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); 557 } 558 } 559 560 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) 561 { 562 apic_set_reg(apic, APIC_TASKPRI, tpr); 563 apic_update_ppr(apic); 564 } 565 566 static int kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest) 567 { 568 return dest == (apic_x2apic_mode(apic) ? 569 X2APIC_BROADCAST : APIC_BROADCAST); 570 } 571 572 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest) 573 { 574 return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest); 575 } 576 577 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda) 578 { 579 int result = 0; 580 u32 logical_id; 581 582 if (kvm_apic_broadcast(apic, mda)) 583 return 1; 584 585 if (apic_x2apic_mode(apic)) { 586 logical_id = kvm_apic_get_reg(apic, APIC_LDR); 587 return logical_id & mda; 588 } 589 590 logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR)); 591 592 switch (kvm_apic_get_reg(apic, APIC_DFR)) { 593 case APIC_DFR_FLAT: 594 if (logical_id & mda) 595 result = 1; 596 break; 597 case APIC_DFR_CLUSTER: 598 if (((logical_id >> 4) == (mda >> 0x4)) 599 && (logical_id & mda & 0xf)) 600 result = 1; 601 break; 602 default: 603 apic_debug("Bad DFR vcpu %d: %08x\n", 604 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR)); 605 break; 606 } 607 608 return result; 609 } 610 611 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, 612 int short_hand, unsigned int dest, int dest_mode) 613 { 614 int result = 0; 615 struct kvm_lapic *target = vcpu->arch.apic; 616 617 apic_debug("target %p, source %p, dest 0x%x, " 618 "dest_mode 0x%x, short_hand 0x%x\n", 619 target, source, dest, dest_mode, short_hand); 620 621 ASSERT(target); 622 switch (short_hand) { 623 case APIC_DEST_NOSHORT: 624 if (dest_mode == 0) 625 /* Physical mode. */ 626 result = kvm_apic_match_physical_addr(target, dest); 627 else 628 /* Logical mode. */ 629 result = kvm_apic_match_logical_addr(target, dest); 630 break; 631 case APIC_DEST_SELF: 632 result = (target == source); 633 break; 634 case APIC_DEST_ALLINC: 635 result = 1; 636 break; 637 case APIC_DEST_ALLBUT: 638 result = (target != source); 639 break; 640 default: 641 apic_debug("kvm: apic: Bad dest shorthand value %x\n", 642 short_hand); 643 break; 644 } 645 646 return result; 647 } 648 649 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, 650 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map) 651 { 652 struct kvm_apic_map *map; 653 unsigned long bitmap = 1; 654 struct kvm_lapic **dst; 655 int i; 656 bool ret = false; 657 658 *r = -1; 659 660 if (irq->shorthand == APIC_DEST_SELF) { 661 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map); 662 return true; 663 } 664 665 if (irq->shorthand) 666 return false; 667 668 rcu_read_lock(); 669 map = rcu_dereference(kvm->arch.apic_map); 670 671 if (!map) 672 goto out; 673 674 if (irq->dest_id == map->broadcast) 675 goto out; 676 677 if (irq->dest_mode == 0) { /* physical mode */ 678 if (irq->delivery_mode == APIC_DM_LOWEST) 679 goto out; 680 dst = &map->phys_map[irq->dest_id & 0xff]; 681 } else { 682 u32 mda = irq->dest_id << (32 - map->ldr_bits); 683 684 dst = map->logical_map[apic_cluster_id(map, mda)]; 685 686 bitmap = apic_logical_id(map, mda); 687 688 if (irq->delivery_mode == APIC_DM_LOWEST) { 689 int l = -1; 690 for_each_set_bit(i, &bitmap, 16) { 691 if (!dst[i]) 692 continue; 693 if (l < 0) 694 l = i; 695 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0) 696 l = i; 697 } 698 699 bitmap = (l >= 0) ? 1 << l : 0; 700 } 701 } 702 703 for_each_set_bit(i, &bitmap, 16) { 704 if (!dst[i]) 705 continue; 706 if (*r < 0) 707 *r = 0; 708 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map); 709 } 710 711 ret = true; 712 out: 713 rcu_read_unlock(); 714 return ret; 715 } 716 717 /* 718 * Add a pending IRQ into lapic. 719 * Return 1 if successfully added and 0 if discarded. 720 */ 721 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, 722 int vector, int level, int trig_mode, 723 unsigned long *dest_map) 724 { 725 int result = 0; 726 struct kvm_vcpu *vcpu = apic->vcpu; 727 728 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, 729 trig_mode, vector); 730 switch (delivery_mode) { 731 case APIC_DM_LOWEST: 732 vcpu->arch.apic_arb_prio++; 733 case APIC_DM_FIXED: 734 /* FIXME add logic for vcpu on reset */ 735 if (unlikely(!apic_enabled(apic))) 736 break; 737 738 result = 1; 739 740 if (dest_map) 741 __set_bit(vcpu->vcpu_id, dest_map); 742 743 if (kvm_x86_ops->deliver_posted_interrupt) 744 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector); 745 else { 746 apic_set_irr(vector, apic); 747 748 kvm_make_request(KVM_REQ_EVENT, vcpu); 749 kvm_vcpu_kick(vcpu); 750 } 751 break; 752 753 case APIC_DM_REMRD: 754 result = 1; 755 vcpu->arch.pv.pv_unhalted = 1; 756 kvm_make_request(KVM_REQ_EVENT, vcpu); 757 kvm_vcpu_kick(vcpu); 758 break; 759 760 case APIC_DM_SMI: 761 apic_debug("Ignoring guest SMI\n"); 762 break; 763 764 case APIC_DM_NMI: 765 result = 1; 766 kvm_inject_nmi(vcpu); 767 kvm_vcpu_kick(vcpu); 768 break; 769 770 case APIC_DM_INIT: 771 if (!trig_mode || level) { 772 result = 1; 773 /* assumes that there are only KVM_APIC_INIT/SIPI */ 774 apic->pending_events = (1UL << KVM_APIC_INIT); 775 /* make sure pending_events is visible before sending 776 * the request */ 777 smp_wmb(); 778 kvm_make_request(KVM_REQ_EVENT, vcpu); 779 kvm_vcpu_kick(vcpu); 780 } else { 781 apic_debug("Ignoring de-assert INIT to vcpu %d\n", 782 vcpu->vcpu_id); 783 } 784 break; 785 786 case APIC_DM_STARTUP: 787 apic_debug("SIPI to vcpu %d vector 0x%02x\n", 788 vcpu->vcpu_id, vector); 789 result = 1; 790 apic->sipi_vector = vector; 791 /* make sure sipi_vector is visible for the receiver */ 792 smp_wmb(); 793 set_bit(KVM_APIC_SIPI, &apic->pending_events); 794 kvm_make_request(KVM_REQ_EVENT, vcpu); 795 kvm_vcpu_kick(vcpu); 796 break; 797 798 case APIC_DM_EXTINT: 799 /* 800 * Should only be called by kvm_apic_local_deliver() with LVT0, 801 * before NMI watchdog was enabled. Already handled by 802 * kvm_apic_accept_pic_intr(). 803 */ 804 break; 805 806 default: 807 printk(KERN_ERR "TODO: unsupported delivery mode %x\n", 808 delivery_mode); 809 break; 810 } 811 return result; 812 } 813 814 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2) 815 { 816 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; 817 } 818 819 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) 820 { 821 if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) && 822 kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) { 823 int trigger_mode; 824 if (apic_test_vector(vector, apic->regs + APIC_TMR)) 825 trigger_mode = IOAPIC_LEVEL_TRIG; 826 else 827 trigger_mode = IOAPIC_EDGE_TRIG; 828 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); 829 } 830 } 831 832 static int apic_set_eoi(struct kvm_lapic *apic) 833 { 834 int vector = apic_find_highest_isr(apic); 835 836 trace_kvm_eoi(apic, vector); 837 838 /* 839 * Not every write EOI will has corresponding ISR, 840 * one example is when Kernel check timer on setup_IO_APIC 841 */ 842 if (vector == -1) 843 return vector; 844 845 apic_clear_isr(vector, apic); 846 apic_update_ppr(apic); 847 848 kvm_ioapic_send_eoi(apic, vector); 849 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); 850 return vector; 851 } 852 853 /* 854 * this interface assumes a trap-like exit, which has already finished 855 * desired side effect including vISR and vPPR update. 856 */ 857 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector) 858 { 859 struct kvm_lapic *apic = vcpu->arch.apic; 860 861 trace_kvm_eoi(apic, vector); 862 863 kvm_ioapic_send_eoi(apic, vector); 864 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); 865 } 866 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated); 867 868 static void apic_send_ipi(struct kvm_lapic *apic) 869 { 870 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR); 871 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2); 872 struct kvm_lapic_irq irq; 873 874 irq.vector = icr_low & APIC_VECTOR_MASK; 875 irq.delivery_mode = icr_low & APIC_MODE_MASK; 876 irq.dest_mode = icr_low & APIC_DEST_MASK; 877 irq.level = icr_low & APIC_INT_ASSERT; 878 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG; 879 irq.shorthand = icr_low & APIC_SHORT_MASK; 880 if (apic_x2apic_mode(apic)) 881 irq.dest_id = icr_high; 882 else 883 irq.dest_id = GET_APIC_DEST_FIELD(icr_high); 884 885 trace_kvm_apic_ipi(icr_low, irq.dest_id); 886 887 apic_debug("icr_high 0x%x, icr_low 0x%x, " 888 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " 889 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n", 890 icr_high, icr_low, irq.shorthand, irq.dest_id, 891 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode, 892 irq.vector); 893 894 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); 895 } 896 897 static u32 apic_get_tmcct(struct kvm_lapic *apic) 898 { 899 ktime_t remaining; 900 s64 ns; 901 u32 tmcct; 902 903 ASSERT(apic != NULL); 904 905 /* if initial count is 0, current count should also be 0 */ 906 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 || 907 apic->lapic_timer.period == 0) 908 return 0; 909 910 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer); 911 if (ktime_to_ns(remaining) < 0) 912 remaining = ktime_set(0, 0); 913 914 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); 915 tmcct = div64_u64(ns, 916 (APIC_BUS_CYCLE_NS * apic->divide_count)); 917 918 return tmcct; 919 } 920 921 static void __report_tpr_access(struct kvm_lapic *apic, bool write) 922 { 923 struct kvm_vcpu *vcpu = apic->vcpu; 924 struct kvm_run *run = vcpu->run; 925 926 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu); 927 run->tpr_access.rip = kvm_rip_read(vcpu); 928 run->tpr_access.is_write = write; 929 } 930 931 static inline void report_tpr_access(struct kvm_lapic *apic, bool write) 932 { 933 if (apic->vcpu->arch.tpr_access_reporting) 934 __report_tpr_access(apic, write); 935 } 936 937 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) 938 { 939 u32 val = 0; 940 941 if (offset >= LAPIC_MMIO_LENGTH) 942 return 0; 943 944 switch (offset) { 945 case APIC_ID: 946 if (apic_x2apic_mode(apic)) 947 val = kvm_apic_id(apic); 948 else 949 val = kvm_apic_id(apic) << 24; 950 break; 951 case APIC_ARBPRI: 952 apic_debug("Access APIC ARBPRI register which is for P6\n"); 953 break; 954 955 case APIC_TMCCT: /* Timer CCR */ 956 if (apic_lvtt_tscdeadline(apic)) 957 return 0; 958 959 val = apic_get_tmcct(apic); 960 break; 961 case APIC_PROCPRI: 962 apic_update_ppr(apic); 963 val = kvm_apic_get_reg(apic, offset); 964 break; 965 case APIC_TASKPRI: 966 report_tpr_access(apic, false); 967 /* fall thru */ 968 default: 969 val = kvm_apic_get_reg(apic, offset); 970 break; 971 } 972 973 return val; 974 } 975 976 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) 977 { 978 return container_of(dev, struct kvm_lapic, dev); 979 } 980 981 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len, 982 void *data) 983 { 984 unsigned char alignment = offset & 0xf; 985 u32 result; 986 /* this bitmask has a bit cleared for each reserved register */ 987 static const u64 rmask = 0x43ff01ffffffe70cULL; 988 989 if ((alignment + len) > 4) { 990 apic_debug("KVM_APIC_READ: alignment error %x %d\n", 991 offset, len); 992 return 1; 993 } 994 995 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) { 996 apic_debug("KVM_APIC_READ: read reserved register %x\n", 997 offset); 998 return 1; 999 } 1000 1001 result = __apic_read(apic, offset & ~0xf); 1002 1003 trace_kvm_apic_read(offset, result); 1004 1005 switch (len) { 1006 case 1: 1007 case 2: 1008 case 4: 1009 memcpy(data, (char *)&result + alignment, len); 1010 break; 1011 default: 1012 printk(KERN_ERR "Local APIC read with len = %x, " 1013 "should be 1,2, or 4 instead\n", len); 1014 break; 1015 } 1016 return 0; 1017 } 1018 1019 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) 1020 { 1021 return kvm_apic_hw_enabled(apic) && 1022 addr >= apic->base_address && 1023 addr < apic->base_address + LAPIC_MMIO_LENGTH; 1024 } 1025 1026 static int apic_mmio_read(struct kvm_io_device *this, 1027 gpa_t address, int len, void *data) 1028 { 1029 struct kvm_lapic *apic = to_lapic(this); 1030 u32 offset = address - apic->base_address; 1031 1032 if (!apic_mmio_in_range(apic, address)) 1033 return -EOPNOTSUPP; 1034 1035 apic_reg_read(apic, offset, len, data); 1036 1037 return 0; 1038 } 1039 1040 static void update_divide_count(struct kvm_lapic *apic) 1041 { 1042 u32 tmp1, tmp2, tdcr; 1043 1044 tdcr = kvm_apic_get_reg(apic, APIC_TDCR); 1045 tmp1 = tdcr & 0xf; 1046 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; 1047 apic->divide_count = 0x1 << (tmp2 & 0x7); 1048 1049 apic_debug("timer divide count is 0x%x\n", 1050 apic->divide_count); 1051 } 1052 1053 static void apic_timer_expired(struct kvm_lapic *apic) 1054 { 1055 struct kvm_vcpu *vcpu = apic->vcpu; 1056 wait_queue_head_t *q = &vcpu->wq; 1057 1058 /* 1059 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in 1060 * vcpu_enter_guest. 1061 */ 1062 if (atomic_read(&apic->lapic_timer.pending)) 1063 return; 1064 1065 atomic_inc(&apic->lapic_timer.pending); 1066 /* FIXME: this code should not know anything about vcpus */ 1067 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); 1068 1069 if (waitqueue_active(q)) 1070 wake_up_interruptible(q); 1071 } 1072 1073 static void start_apic_timer(struct kvm_lapic *apic) 1074 { 1075 ktime_t now; 1076 atomic_set(&apic->lapic_timer.pending, 0); 1077 1078 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) { 1079 /* lapic timer in oneshot or periodic mode */ 1080 now = apic->lapic_timer.timer.base->get_time(); 1081 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT) 1082 * APIC_BUS_CYCLE_NS * apic->divide_count; 1083 1084 if (!apic->lapic_timer.period) 1085 return; 1086 /* 1087 * Do not allow the guest to program periodic timers with small 1088 * interval, since the hrtimers are not throttled by the host 1089 * scheduler. 1090 */ 1091 if (apic_lvtt_period(apic)) { 1092 s64 min_period = min_timer_period_us * 1000LL; 1093 1094 if (apic->lapic_timer.period < min_period) { 1095 pr_info_ratelimited( 1096 "kvm: vcpu %i: requested %lld ns " 1097 "lapic timer period limited to %lld ns\n", 1098 apic->vcpu->vcpu_id, 1099 apic->lapic_timer.period, min_period); 1100 apic->lapic_timer.period = min_period; 1101 } 1102 } 1103 1104 hrtimer_start(&apic->lapic_timer.timer, 1105 ktime_add_ns(now, apic->lapic_timer.period), 1106 HRTIMER_MODE_ABS); 1107 1108 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" 1109 PRIx64 ", " 1110 "timer initial count 0x%x, period %lldns, " 1111 "expire @ 0x%016" PRIx64 ".\n", __func__, 1112 APIC_BUS_CYCLE_NS, ktime_to_ns(now), 1113 kvm_apic_get_reg(apic, APIC_TMICT), 1114 apic->lapic_timer.period, 1115 ktime_to_ns(ktime_add_ns(now, 1116 apic->lapic_timer.period))); 1117 } else if (apic_lvtt_tscdeadline(apic)) { 1118 /* lapic timer in tsc deadline mode */ 1119 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline; 1120 u64 ns = 0; 1121 struct kvm_vcpu *vcpu = apic->vcpu; 1122 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; 1123 unsigned long flags; 1124 1125 if (unlikely(!tscdeadline || !this_tsc_khz)) 1126 return; 1127 1128 local_irq_save(flags); 1129 1130 now = apic->lapic_timer.timer.base->get_time(); 1131 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc()); 1132 if (likely(tscdeadline > guest_tsc)) { 1133 ns = (tscdeadline - guest_tsc) * 1000000ULL; 1134 do_div(ns, this_tsc_khz); 1135 hrtimer_start(&apic->lapic_timer.timer, 1136 ktime_add_ns(now, ns), HRTIMER_MODE_ABS); 1137 } else 1138 apic_timer_expired(apic); 1139 1140 local_irq_restore(flags); 1141 } 1142 } 1143 1144 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) 1145 { 1146 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0)); 1147 1148 if (apic_lvt_nmi_mode(lvt0_val)) { 1149 if (!nmi_wd_enabled) { 1150 apic_debug("Receive NMI setting on APIC_LVT0 " 1151 "for cpu %d\n", apic->vcpu->vcpu_id); 1152 apic->vcpu->kvm->arch.vapics_in_nmi_mode++; 1153 } 1154 } else if (nmi_wd_enabled) 1155 apic->vcpu->kvm->arch.vapics_in_nmi_mode--; 1156 } 1157 1158 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) 1159 { 1160 int ret = 0; 1161 1162 trace_kvm_apic_write(reg, val); 1163 1164 switch (reg) { 1165 case APIC_ID: /* Local APIC ID */ 1166 if (!apic_x2apic_mode(apic)) 1167 kvm_apic_set_id(apic, val >> 24); 1168 else 1169 ret = 1; 1170 break; 1171 1172 case APIC_TASKPRI: 1173 report_tpr_access(apic, true); 1174 apic_set_tpr(apic, val & 0xff); 1175 break; 1176 1177 case APIC_EOI: 1178 apic_set_eoi(apic); 1179 break; 1180 1181 case APIC_LDR: 1182 if (!apic_x2apic_mode(apic)) 1183 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); 1184 else 1185 ret = 1; 1186 break; 1187 1188 case APIC_DFR: 1189 if (!apic_x2apic_mode(apic)) { 1190 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); 1191 recalculate_apic_map(apic->vcpu->kvm); 1192 } else 1193 ret = 1; 1194 break; 1195 1196 case APIC_SPIV: { 1197 u32 mask = 0x3ff; 1198 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) 1199 mask |= APIC_SPIV_DIRECTED_EOI; 1200 apic_set_spiv(apic, val & mask); 1201 if (!(val & APIC_SPIV_APIC_ENABLED)) { 1202 int i; 1203 u32 lvt_val; 1204 1205 for (i = 0; i < APIC_LVT_NUM; i++) { 1206 lvt_val = kvm_apic_get_reg(apic, 1207 APIC_LVTT + 0x10 * i); 1208 apic_set_reg(apic, APIC_LVTT + 0x10 * i, 1209 lvt_val | APIC_LVT_MASKED); 1210 } 1211 atomic_set(&apic->lapic_timer.pending, 0); 1212 1213 } 1214 break; 1215 } 1216 case APIC_ICR: 1217 /* No delay here, so we always clear the pending bit */ 1218 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); 1219 apic_send_ipi(apic); 1220 break; 1221 1222 case APIC_ICR2: 1223 if (!apic_x2apic_mode(apic)) 1224 val &= 0xff000000; 1225 apic_set_reg(apic, APIC_ICR2, val); 1226 break; 1227 1228 case APIC_LVT0: 1229 apic_manage_nmi_watchdog(apic, val); 1230 case APIC_LVTTHMR: 1231 case APIC_LVTPC: 1232 case APIC_LVT1: 1233 case APIC_LVTERR: 1234 /* TODO: Check vector */ 1235 if (!kvm_apic_sw_enabled(apic)) 1236 val |= APIC_LVT_MASKED; 1237 1238 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4]; 1239 apic_set_reg(apic, reg, val); 1240 1241 break; 1242 1243 case APIC_LVTT: 1244 if ((kvm_apic_get_reg(apic, APIC_LVTT) & 1245 apic->lapic_timer.timer_mode_mask) != 1246 (val & apic->lapic_timer.timer_mode_mask)) 1247 hrtimer_cancel(&apic->lapic_timer.timer); 1248 1249 if (!kvm_apic_sw_enabled(apic)) 1250 val |= APIC_LVT_MASKED; 1251 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); 1252 apic_set_reg(apic, APIC_LVTT, val); 1253 break; 1254 1255 case APIC_TMICT: 1256 if (apic_lvtt_tscdeadline(apic)) 1257 break; 1258 1259 hrtimer_cancel(&apic->lapic_timer.timer); 1260 apic_set_reg(apic, APIC_TMICT, val); 1261 start_apic_timer(apic); 1262 break; 1263 1264 case APIC_TDCR: 1265 if (val & 4) 1266 apic_debug("KVM_WRITE:TDCR %x\n", val); 1267 apic_set_reg(apic, APIC_TDCR, val); 1268 update_divide_count(apic); 1269 break; 1270 1271 case APIC_ESR: 1272 if (apic_x2apic_mode(apic) && val != 0) { 1273 apic_debug("KVM_WRITE:ESR not zero %x\n", val); 1274 ret = 1; 1275 } 1276 break; 1277 1278 case APIC_SELF_IPI: 1279 if (apic_x2apic_mode(apic)) { 1280 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff)); 1281 } else 1282 ret = 1; 1283 break; 1284 default: 1285 ret = 1; 1286 break; 1287 } 1288 if (ret) 1289 apic_debug("Local APIC Write to read-only register %x\n", reg); 1290 return ret; 1291 } 1292 1293 static int apic_mmio_write(struct kvm_io_device *this, 1294 gpa_t address, int len, const void *data) 1295 { 1296 struct kvm_lapic *apic = to_lapic(this); 1297 unsigned int offset = address - apic->base_address; 1298 u32 val; 1299 1300 if (!apic_mmio_in_range(apic, address)) 1301 return -EOPNOTSUPP; 1302 1303 /* 1304 * APIC register must be aligned on 128-bits boundary. 1305 * 32/64/128 bits registers must be accessed thru 32 bits. 1306 * Refer SDM 8.4.1 1307 */ 1308 if (len != 4 || (offset & 0xf)) { 1309 /* Don't shout loud, $infamous_os would cause only noise. */ 1310 apic_debug("apic write: bad size=%d %lx\n", len, (long)address); 1311 return 0; 1312 } 1313 1314 val = *(u32*)data; 1315 1316 /* too common printing */ 1317 if (offset != APIC_EOI) 1318 apic_debug("%s: offset 0x%x with length 0x%x, and value is " 1319 "0x%x\n", __func__, offset, len, val); 1320 1321 apic_reg_write(apic, offset & 0xff0, val); 1322 1323 return 0; 1324 } 1325 1326 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu) 1327 { 1328 if (kvm_vcpu_has_lapic(vcpu)) 1329 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0); 1330 } 1331 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi); 1332 1333 /* emulate APIC access in a trap manner */ 1334 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) 1335 { 1336 u32 val = 0; 1337 1338 /* hw has done the conditional check and inst decode */ 1339 offset &= 0xff0; 1340 1341 apic_reg_read(vcpu->arch.apic, offset, 4, &val); 1342 1343 /* TODO: optimize to just emulate side effect w/o one more write */ 1344 apic_reg_write(vcpu->arch.apic, offset, val); 1345 } 1346 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode); 1347 1348 void kvm_free_lapic(struct kvm_vcpu *vcpu) 1349 { 1350 struct kvm_lapic *apic = vcpu->arch.apic; 1351 1352 if (!vcpu->arch.apic) 1353 return; 1354 1355 hrtimer_cancel(&apic->lapic_timer.timer); 1356 1357 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) 1358 static_key_slow_dec_deferred(&apic_hw_disabled); 1359 1360 if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED)) 1361 static_key_slow_dec_deferred(&apic_sw_disabled); 1362 1363 if (apic->regs) 1364 free_page((unsigned long)apic->regs); 1365 1366 kfree(apic); 1367 } 1368 1369 /* 1370 *---------------------------------------------------------------------- 1371 * LAPIC interface 1372 *---------------------------------------------------------------------- 1373 */ 1374 1375 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu) 1376 { 1377 struct kvm_lapic *apic = vcpu->arch.apic; 1378 1379 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) || 1380 apic_lvtt_period(apic)) 1381 return 0; 1382 1383 return apic->lapic_timer.tscdeadline; 1384 } 1385 1386 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) 1387 { 1388 struct kvm_lapic *apic = vcpu->arch.apic; 1389 1390 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) || 1391 apic_lvtt_period(apic)) 1392 return; 1393 1394 hrtimer_cancel(&apic->lapic_timer.timer); 1395 apic->lapic_timer.tscdeadline = data; 1396 start_apic_timer(apic); 1397 } 1398 1399 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) 1400 { 1401 struct kvm_lapic *apic = vcpu->arch.apic; 1402 1403 if (!kvm_vcpu_has_lapic(vcpu)) 1404 return; 1405 1406 apic_set_tpr(apic, ((cr8 & 0x0f) << 4) 1407 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4)); 1408 } 1409 1410 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) 1411 { 1412 u64 tpr; 1413 1414 if (!kvm_vcpu_has_lapic(vcpu)) 1415 return 0; 1416 1417 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI); 1418 1419 return (tpr & 0xf0) >> 4; 1420 } 1421 1422 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) 1423 { 1424 u64 old_value = vcpu->arch.apic_base; 1425 struct kvm_lapic *apic = vcpu->arch.apic; 1426 1427 if (!apic) { 1428 value |= MSR_IA32_APICBASE_BSP; 1429 vcpu->arch.apic_base = value; 1430 return; 1431 } 1432 1433 if (!kvm_vcpu_is_bsp(apic->vcpu)) 1434 value &= ~MSR_IA32_APICBASE_BSP; 1435 vcpu->arch.apic_base = value; 1436 1437 /* update jump label if enable bit changes */ 1438 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) { 1439 if (value & MSR_IA32_APICBASE_ENABLE) 1440 static_key_slow_dec_deferred(&apic_hw_disabled); 1441 else 1442 static_key_slow_inc(&apic_hw_disabled.key); 1443 recalculate_apic_map(vcpu->kvm); 1444 } 1445 1446 if ((old_value ^ value) & X2APIC_ENABLE) { 1447 if (value & X2APIC_ENABLE) { 1448 u32 id = kvm_apic_id(apic); 1449 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf)); 1450 kvm_apic_set_ldr(apic, ldr); 1451 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true); 1452 } else 1453 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false); 1454 } 1455 1456 apic->base_address = apic->vcpu->arch.apic_base & 1457 MSR_IA32_APICBASE_BASE; 1458 1459 /* with FSB delivery interrupt, we can restart APIC functionality */ 1460 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " 1461 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); 1462 1463 } 1464 1465 void kvm_lapic_reset(struct kvm_vcpu *vcpu) 1466 { 1467 struct kvm_lapic *apic; 1468 int i; 1469 1470 apic_debug("%s\n", __func__); 1471 1472 ASSERT(vcpu); 1473 apic = vcpu->arch.apic; 1474 ASSERT(apic != NULL); 1475 1476 /* Stop the timer in case it's a reset to an active apic */ 1477 hrtimer_cancel(&apic->lapic_timer.timer); 1478 1479 kvm_apic_set_id(apic, vcpu->vcpu_id); 1480 kvm_apic_set_version(apic->vcpu); 1481 1482 for (i = 0; i < APIC_LVT_NUM; i++) 1483 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); 1484 apic_set_reg(apic, APIC_LVT0, 1485 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); 1486 1487 apic_set_reg(apic, APIC_DFR, 0xffffffffU); 1488 apic_set_spiv(apic, 0xff); 1489 apic_set_reg(apic, APIC_TASKPRI, 0); 1490 kvm_apic_set_ldr(apic, 0); 1491 apic_set_reg(apic, APIC_ESR, 0); 1492 apic_set_reg(apic, APIC_ICR, 0); 1493 apic_set_reg(apic, APIC_ICR2, 0); 1494 apic_set_reg(apic, APIC_TDCR, 0); 1495 apic_set_reg(apic, APIC_TMICT, 0); 1496 for (i = 0; i < 8; i++) { 1497 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0); 1498 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0); 1499 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0); 1500 } 1501 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm); 1502 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm); 1503 apic->highest_isr_cache = -1; 1504 update_divide_count(apic); 1505 atomic_set(&apic->lapic_timer.pending, 0); 1506 if (kvm_vcpu_is_bsp(vcpu)) 1507 kvm_lapic_set_base(vcpu, 1508 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP); 1509 vcpu->arch.pv_eoi.msr_val = 0; 1510 apic_update_ppr(apic); 1511 1512 vcpu->arch.apic_arb_prio = 0; 1513 vcpu->arch.apic_attention = 0; 1514 1515 apic_debug("%s: vcpu=%p, id=%d, base_msr=" 1516 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, 1517 vcpu, kvm_apic_id(apic), 1518 vcpu->arch.apic_base, apic->base_address); 1519 } 1520 1521 /* 1522 *---------------------------------------------------------------------- 1523 * timer interface 1524 *---------------------------------------------------------------------- 1525 */ 1526 1527 static bool lapic_is_periodic(struct kvm_lapic *apic) 1528 { 1529 return apic_lvtt_period(apic); 1530 } 1531 1532 int apic_has_pending_timer(struct kvm_vcpu *vcpu) 1533 { 1534 struct kvm_lapic *apic = vcpu->arch.apic; 1535 1536 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) && 1537 apic_lvt_enabled(apic, APIC_LVTT)) 1538 return atomic_read(&apic->lapic_timer.pending); 1539 1540 return 0; 1541 } 1542 1543 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) 1544 { 1545 u32 reg = kvm_apic_get_reg(apic, lvt_type); 1546 int vector, mode, trig_mode; 1547 1548 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { 1549 vector = reg & APIC_VECTOR_MASK; 1550 mode = reg & APIC_MODE_MASK; 1551 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; 1552 return __apic_accept_irq(apic, mode, vector, 1, trig_mode, 1553 NULL); 1554 } 1555 return 0; 1556 } 1557 1558 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) 1559 { 1560 struct kvm_lapic *apic = vcpu->arch.apic; 1561 1562 if (apic) 1563 kvm_apic_local_deliver(apic, APIC_LVT0); 1564 } 1565 1566 static const struct kvm_io_device_ops apic_mmio_ops = { 1567 .read = apic_mmio_read, 1568 .write = apic_mmio_write, 1569 }; 1570 1571 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data) 1572 { 1573 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer); 1574 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); 1575 1576 apic_timer_expired(apic); 1577 1578 if (lapic_is_periodic(apic)) { 1579 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period); 1580 return HRTIMER_RESTART; 1581 } else 1582 return HRTIMER_NORESTART; 1583 } 1584 1585 int kvm_create_lapic(struct kvm_vcpu *vcpu) 1586 { 1587 struct kvm_lapic *apic; 1588 1589 ASSERT(vcpu != NULL); 1590 apic_debug("apic_init %d\n", vcpu->vcpu_id); 1591 1592 apic = kzalloc(sizeof(*apic), GFP_KERNEL); 1593 if (!apic) 1594 goto nomem; 1595 1596 vcpu->arch.apic = apic; 1597 1598 apic->regs = (void *)get_zeroed_page(GFP_KERNEL); 1599 if (!apic->regs) { 1600 printk(KERN_ERR "malloc apic regs error for vcpu %x\n", 1601 vcpu->vcpu_id); 1602 goto nomem_free_apic; 1603 } 1604 apic->vcpu = vcpu; 1605 1606 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, 1607 HRTIMER_MODE_ABS); 1608 apic->lapic_timer.timer.function = apic_timer_fn; 1609 1610 /* 1611 * APIC is created enabled. This will prevent kvm_lapic_set_base from 1612 * thinking that APIC satet has changed. 1613 */ 1614 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; 1615 kvm_lapic_set_base(vcpu, 1616 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE); 1617 1618 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */ 1619 kvm_lapic_reset(vcpu); 1620 kvm_iodevice_init(&apic->dev, &apic_mmio_ops); 1621 1622 return 0; 1623 nomem_free_apic: 1624 kfree(apic); 1625 nomem: 1626 return -ENOMEM; 1627 } 1628 1629 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) 1630 { 1631 struct kvm_lapic *apic = vcpu->arch.apic; 1632 int highest_irr; 1633 1634 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic)) 1635 return -1; 1636 1637 apic_update_ppr(apic); 1638 highest_irr = apic_find_highest_irr(apic); 1639 if ((highest_irr == -1) || 1640 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI))) 1641 return -1; 1642 return highest_irr; 1643 } 1644 1645 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) 1646 { 1647 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0); 1648 int r = 0; 1649 1650 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) 1651 r = 1; 1652 if ((lvt0 & APIC_LVT_MASKED) == 0 && 1653 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) 1654 r = 1; 1655 return r; 1656 } 1657 1658 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) 1659 { 1660 struct kvm_lapic *apic = vcpu->arch.apic; 1661 1662 if (!kvm_vcpu_has_lapic(vcpu)) 1663 return; 1664 1665 if (atomic_read(&apic->lapic_timer.pending) > 0) { 1666 kvm_apic_local_deliver(apic, APIC_LVTT); 1667 if (apic_lvtt_tscdeadline(apic)) 1668 apic->lapic_timer.tscdeadline = 0; 1669 atomic_set(&apic->lapic_timer.pending, 0); 1670 } 1671 } 1672 1673 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) 1674 { 1675 int vector = kvm_apic_has_interrupt(vcpu); 1676 struct kvm_lapic *apic = vcpu->arch.apic; 1677 1678 if (vector == -1) 1679 return -1; 1680 1681 /* 1682 * We get here even with APIC virtualization enabled, if doing 1683 * nested virtualization and L1 runs with the "acknowledge interrupt 1684 * on exit" mode. Then we cannot inject the interrupt via RVI, 1685 * because the process would deliver it through the IDT. 1686 */ 1687 1688 apic_set_isr(vector, apic); 1689 apic_update_ppr(apic); 1690 apic_clear_irr(vector, apic); 1691 return vector; 1692 } 1693 1694 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, 1695 struct kvm_lapic_state *s) 1696 { 1697 struct kvm_lapic *apic = vcpu->arch.apic; 1698 1699 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); 1700 /* set SPIV separately to get count of SW disabled APICs right */ 1701 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); 1702 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); 1703 /* call kvm_apic_set_id() to put apic into apic_map */ 1704 kvm_apic_set_id(apic, kvm_apic_id(apic)); 1705 kvm_apic_set_version(vcpu); 1706 1707 apic_update_ppr(apic); 1708 hrtimer_cancel(&apic->lapic_timer.timer); 1709 update_divide_count(apic); 1710 start_apic_timer(apic); 1711 apic->irr_pending = true; 1712 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ? 1713 1 : count_vectors(apic->regs + APIC_ISR); 1714 apic->highest_isr_cache = -1; 1715 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic)); 1716 kvm_make_request(KVM_REQ_EVENT, vcpu); 1717 kvm_rtc_eoi_tracking_restore_one(vcpu); 1718 } 1719 1720 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) 1721 { 1722 struct hrtimer *timer; 1723 1724 if (!kvm_vcpu_has_lapic(vcpu)) 1725 return; 1726 1727 timer = &vcpu->arch.apic->lapic_timer.timer; 1728 if (hrtimer_cancel(timer)) 1729 hrtimer_start_expires(timer, HRTIMER_MODE_ABS); 1730 } 1731 1732 /* 1733 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt 1734 * 1735 * Detect whether guest triggered PV EOI since the 1736 * last entry. If yes, set EOI on guests's behalf. 1737 * Clear PV EOI in guest memory in any case. 1738 */ 1739 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu, 1740 struct kvm_lapic *apic) 1741 { 1742 bool pending; 1743 int vector; 1744 /* 1745 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host 1746 * and KVM_PV_EOI_ENABLED in guest memory as follows: 1747 * 1748 * KVM_APIC_PV_EOI_PENDING is unset: 1749 * -> host disabled PV EOI. 1750 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set: 1751 * -> host enabled PV EOI, guest did not execute EOI yet. 1752 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset: 1753 * -> host enabled PV EOI, guest executed EOI. 1754 */ 1755 BUG_ON(!pv_eoi_enabled(vcpu)); 1756 pending = pv_eoi_get_pending(vcpu); 1757 /* 1758 * Clear pending bit in any case: it will be set again on vmentry. 1759 * While this might not be ideal from performance point of view, 1760 * this makes sure pv eoi is only enabled when we know it's safe. 1761 */ 1762 pv_eoi_clr_pending(vcpu); 1763 if (pending) 1764 return; 1765 vector = apic_set_eoi(apic); 1766 trace_kvm_pv_eoi(apic, vector); 1767 } 1768 1769 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) 1770 { 1771 u32 data; 1772 1773 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention)) 1774 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); 1775 1776 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) 1777 return; 1778 1779 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, 1780 sizeof(u32)); 1781 1782 apic_set_tpr(vcpu->arch.apic, data & 0xff); 1783 } 1784 1785 /* 1786 * apic_sync_pv_eoi_to_guest - called before vmentry 1787 * 1788 * Detect whether it's safe to enable PV EOI and 1789 * if yes do so. 1790 */ 1791 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu, 1792 struct kvm_lapic *apic) 1793 { 1794 if (!pv_eoi_enabled(vcpu) || 1795 /* IRR set or many bits in ISR: could be nested. */ 1796 apic->irr_pending || 1797 /* Cache not set: could be safe but we don't bother. */ 1798 apic->highest_isr_cache == -1 || 1799 /* Need EOI to update ioapic. */ 1800 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) { 1801 /* 1802 * PV EOI was disabled by apic_sync_pv_eoi_from_guest 1803 * so we need not do anything here. 1804 */ 1805 return; 1806 } 1807 1808 pv_eoi_set_pending(apic->vcpu); 1809 } 1810 1811 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) 1812 { 1813 u32 data, tpr; 1814 int max_irr, max_isr; 1815 struct kvm_lapic *apic = vcpu->arch.apic; 1816 1817 apic_sync_pv_eoi_to_guest(vcpu, apic); 1818 1819 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) 1820 return; 1821 1822 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff; 1823 max_irr = apic_find_highest_irr(apic); 1824 if (max_irr < 0) 1825 max_irr = 0; 1826 max_isr = apic_find_highest_isr(apic); 1827 if (max_isr < 0) 1828 max_isr = 0; 1829 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); 1830 1831 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, 1832 sizeof(u32)); 1833 } 1834 1835 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) 1836 { 1837 if (vapic_addr) { 1838 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, 1839 &vcpu->arch.apic->vapic_cache, 1840 vapic_addr, sizeof(u32))) 1841 return -EINVAL; 1842 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); 1843 } else { 1844 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); 1845 } 1846 1847 vcpu->arch.apic->vapic_addr = vapic_addr; 1848 return 0; 1849 } 1850 1851 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) 1852 { 1853 struct kvm_lapic *apic = vcpu->arch.apic; 1854 u32 reg = (msr - APIC_BASE_MSR) << 4; 1855 1856 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic)) 1857 return 1; 1858 1859 /* if this is ICR write vector before command */ 1860 if (msr == 0x830) 1861 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); 1862 return apic_reg_write(apic, reg, (u32)data); 1863 } 1864 1865 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) 1866 { 1867 struct kvm_lapic *apic = vcpu->arch.apic; 1868 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0; 1869 1870 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic)) 1871 return 1; 1872 1873 if (apic_reg_read(apic, reg, 4, &low)) 1874 return 1; 1875 if (msr == 0x830) 1876 apic_reg_read(apic, APIC_ICR2, 4, &high); 1877 1878 *data = (((u64)high) << 32) | low; 1879 1880 return 0; 1881 } 1882 1883 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) 1884 { 1885 struct kvm_lapic *apic = vcpu->arch.apic; 1886 1887 if (!kvm_vcpu_has_lapic(vcpu)) 1888 return 1; 1889 1890 /* if this is ICR write vector before command */ 1891 if (reg == APIC_ICR) 1892 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); 1893 return apic_reg_write(apic, reg, (u32)data); 1894 } 1895 1896 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) 1897 { 1898 struct kvm_lapic *apic = vcpu->arch.apic; 1899 u32 low, high = 0; 1900 1901 if (!kvm_vcpu_has_lapic(vcpu)) 1902 return 1; 1903 1904 if (apic_reg_read(apic, reg, 4, &low)) 1905 return 1; 1906 if (reg == APIC_ICR) 1907 apic_reg_read(apic, APIC_ICR2, 4, &high); 1908 1909 *data = (((u64)high) << 32) | low; 1910 1911 return 0; 1912 } 1913 1914 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data) 1915 { 1916 u64 addr = data & ~KVM_MSR_ENABLED; 1917 if (!IS_ALIGNED(addr, 4)) 1918 return 1; 1919 1920 vcpu->arch.pv_eoi.msr_val = data; 1921 if (!pv_eoi_enabled(vcpu)) 1922 return 0; 1923 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data, 1924 addr, sizeof(u8)); 1925 } 1926 1927 void kvm_apic_accept_events(struct kvm_vcpu *vcpu) 1928 { 1929 struct kvm_lapic *apic = vcpu->arch.apic; 1930 unsigned int sipi_vector; 1931 unsigned long pe; 1932 1933 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events) 1934 return; 1935 1936 pe = xchg(&apic->pending_events, 0); 1937 1938 if (test_bit(KVM_APIC_INIT, &pe)) { 1939 kvm_lapic_reset(vcpu); 1940 kvm_vcpu_reset(vcpu); 1941 if (kvm_vcpu_is_bsp(apic->vcpu)) 1942 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 1943 else 1944 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; 1945 } 1946 if (test_bit(KVM_APIC_SIPI, &pe) && 1947 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { 1948 /* evaluate pending_events before reading the vector */ 1949 smp_rmb(); 1950 sipi_vector = apic->sipi_vector; 1951 apic_debug("vcpu %d received sipi with vector # %x\n", 1952 vcpu->vcpu_id, sipi_vector); 1953 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector); 1954 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; 1955 } 1956 } 1957 1958 void kvm_lapic_init(void) 1959 { 1960 /* do not patch jump label more than once per second */ 1961 jump_label_rate_limit(&apic_hw_disabled, HZ); 1962 jump_label_rate_limit(&apic_sw_disabled, HZ); 1963 } 1964