1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong 4 * because MTRRs can span up to 40 bits (36bits on most modern x86) 5 */ 6 7 #include <linux/export.h> 8 #include <linux/init.h> 9 #include <linux/io.h> 10 #include <linux/mm.h> 11 12 #include <asm/processor-flags.h> 13 #include <asm/cacheinfo.h> 14 #include <asm/cpufeature.h> 15 #include <asm/tlbflush.h> 16 #include <asm/mtrr.h> 17 #include <asm/msr.h> 18 #include <asm/memtype.h> 19 20 #include "mtrr.h" 21 22 struct fixed_range_block { 23 int base_msr; /* start address of an MTRR block */ 24 int ranges; /* number of MTRRs in this block */ 25 }; 26 27 static struct fixed_range_block fixed_range_blocks[] = { 28 { MSR_MTRRfix64K_00000, 1 }, /* one 64k MTRR */ 29 { MSR_MTRRfix16K_80000, 2 }, /* two 16k MTRRs */ 30 { MSR_MTRRfix4K_C0000, 8 }, /* eight 4k MTRRs */ 31 {} 32 }; 33 34 static unsigned long smp_changes_mask; 35 static int mtrr_state_set; 36 u64 mtrr_tom2; 37 38 struct mtrr_state_type mtrr_state; 39 EXPORT_SYMBOL_GPL(mtrr_state); 40 41 static u64 size_or_mask, size_and_mask; 42 43 void __init mtrr_set_mask(void) 44 { 45 unsigned int phys_addr = boot_cpu_data.x86_phys_bits; 46 47 size_or_mask = ~GENMASK_ULL(phys_addr - PAGE_SHIFT - 1, 0); 48 size_and_mask = ~size_or_mask & GENMASK_ULL(39, 20); 49 } 50 51 /* 52 * BIOS is expected to clear MtrrFixDramModEn bit, see for example 53 * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD 54 * Opteron Processors" (26094 Rev. 3.30 February 2006), section 55 * "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set 56 * to 1 during BIOS initialization of the fixed MTRRs, then cleared to 57 * 0 for operation." 58 */ 59 static inline void k8_check_syscfg_dram_mod_en(void) 60 { 61 u32 lo, hi; 62 63 if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && 64 (boot_cpu_data.x86 >= 0x0f))) 65 return; 66 67 rdmsr(MSR_AMD64_SYSCFG, lo, hi); 68 if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) { 69 pr_err(FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]" 70 " not cleared by BIOS, clearing this bit\n", 71 smp_processor_id()); 72 lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY; 73 mtrr_wrmsr(MSR_AMD64_SYSCFG, lo, hi); 74 } 75 } 76 77 /* Get the size of contiguous MTRR range */ 78 static u64 get_mtrr_size(u64 mask) 79 { 80 u64 size; 81 82 mask >>= PAGE_SHIFT; 83 mask |= size_or_mask; 84 size = -mask; 85 size <<= PAGE_SHIFT; 86 return size; 87 } 88 89 /* 90 * Check and return the effective type for MTRR-MTRR type overlap. 91 * Returns 1 if the effective type is UNCACHEABLE, else returns 0 92 */ 93 static int check_type_overlap(u8 *prev, u8 *curr) 94 { 95 if (*prev == MTRR_TYPE_UNCACHABLE || *curr == MTRR_TYPE_UNCACHABLE) { 96 *prev = MTRR_TYPE_UNCACHABLE; 97 *curr = MTRR_TYPE_UNCACHABLE; 98 return 1; 99 } 100 101 if ((*prev == MTRR_TYPE_WRBACK && *curr == MTRR_TYPE_WRTHROUGH) || 102 (*prev == MTRR_TYPE_WRTHROUGH && *curr == MTRR_TYPE_WRBACK)) { 103 *prev = MTRR_TYPE_WRTHROUGH; 104 *curr = MTRR_TYPE_WRTHROUGH; 105 } 106 107 if (*prev != *curr) { 108 *prev = MTRR_TYPE_UNCACHABLE; 109 *curr = MTRR_TYPE_UNCACHABLE; 110 return 1; 111 } 112 113 return 0; 114 } 115 116 /** 117 * mtrr_type_lookup_fixed - look up memory type in MTRR fixed entries 118 * 119 * Return the MTRR fixed memory type of 'start'. 120 * 121 * MTRR fixed entries are divided into the following ways: 122 * 0x00000 - 0x7FFFF : This range is divided into eight 64KB sub-ranges 123 * 0x80000 - 0xBFFFF : This range is divided into sixteen 16KB sub-ranges 124 * 0xC0000 - 0xFFFFF : This range is divided into sixty-four 4KB sub-ranges 125 * 126 * Return Values: 127 * MTRR_TYPE_(type) - Matched memory type 128 * MTRR_TYPE_INVALID - Unmatched 129 */ 130 static u8 mtrr_type_lookup_fixed(u64 start, u64 end) 131 { 132 int idx; 133 134 if (start >= 0x100000) 135 return MTRR_TYPE_INVALID; 136 137 /* 0x0 - 0x7FFFF */ 138 if (start < 0x80000) { 139 idx = 0; 140 idx += (start >> 16); 141 return mtrr_state.fixed_ranges[idx]; 142 /* 0x80000 - 0xBFFFF */ 143 } else if (start < 0xC0000) { 144 idx = 1 * 8; 145 idx += ((start - 0x80000) >> 14); 146 return mtrr_state.fixed_ranges[idx]; 147 } 148 149 /* 0xC0000 - 0xFFFFF */ 150 idx = 3 * 8; 151 idx += ((start - 0xC0000) >> 12); 152 return mtrr_state.fixed_ranges[idx]; 153 } 154 155 /** 156 * mtrr_type_lookup_variable - look up memory type in MTRR variable entries 157 * 158 * Return Value: 159 * MTRR_TYPE_(type) - Matched memory type or default memory type (unmatched) 160 * 161 * Output Arguments: 162 * repeat - Set to 1 when [start:end] spanned across MTRR range and type 163 * returned corresponds only to [start:*partial_end]. Caller has 164 * to lookup again for [*partial_end:end]. 165 * 166 * uniform - Set to 1 when an MTRR covers the region uniformly, i.e. the 167 * region is fully covered by a single MTRR entry or the default 168 * type. 169 */ 170 static u8 mtrr_type_lookup_variable(u64 start, u64 end, u64 *partial_end, 171 int *repeat, u8 *uniform) 172 { 173 int i; 174 u64 base, mask; 175 u8 prev_match, curr_match; 176 177 *repeat = 0; 178 *uniform = 1; 179 180 prev_match = MTRR_TYPE_INVALID; 181 for (i = 0; i < num_var_ranges; ++i) { 182 unsigned short start_state, end_state, inclusive; 183 184 if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11))) 185 continue; 186 187 base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) + 188 (mtrr_state.var_ranges[i].base_lo & PAGE_MASK); 189 mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) + 190 (mtrr_state.var_ranges[i].mask_lo & PAGE_MASK); 191 192 start_state = ((start & mask) == (base & mask)); 193 end_state = ((end & mask) == (base & mask)); 194 inclusive = ((start < base) && (end > base)); 195 196 if ((start_state != end_state) || inclusive) { 197 /* 198 * We have start:end spanning across an MTRR. 199 * We split the region into either 200 * 201 * - start_state:1 202 * (start:mtrr_end)(mtrr_end:end) 203 * - end_state:1 204 * (start:mtrr_start)(mtrr_start:end) 205 * - inclusive:1 206 * (start:mtrr_start)(mtrr_start:mtrr_end)(mtrr_end:end) 207 * 208 * depending on kind of overlap. 209 * 210 * Return the type of the first region and a pointer 211 * to the start of next region so that caller will be 212 * advised to lookup again after having adjusted start 213 * and end. 214 * 215 * Note: This way we handle overlaps with multiple 216 * entries and the default type properly. 217 */ 218 if (start_state) 219 *partial_end = base + get_mtrr_size(mask); 220 else 221 *partial_end = base; 222 223 if (unlikely(*partial_end <= start)) { 224 WARN_ON(1); 225 *partial_end = start + PAGE_SIZE; 226 } 227 228 end = *partial_end - 1; /* end is inclusive */ 229 *repeat = 1; 230 *uniform = 0; 231 } 232 233 if ((start & mask) != (base & mask)) 234 continue; 235 236 curr_match = mtrr_state.var_ranges[i].base_lo & 0xff; 237 if (prev_match == MTRR_TYPE_INVALID) { 238 prev_match = curr_match; 239 continue; 240 } 241 242 *uniform = 0; 243 if (check_type_overlap(&prev_match, &curr_match)) 244 return curr_match; 245 } 246 247 if (prev_match != MTRR_TYPE_INVALID) 248 return prev_match; 249 250 return mtrr_state.def_type; 251 } 252 253 /** 254 * mtrr_type_lookup - look up memory type in MTRR 255 * 256 * Return Values: 257 * MTRR_TYPE_(type) - The effective MTRR type for the region 258 * MTRR_TYPE_INVALID - MTRR is disabled 259 * 260 * Output Argument: 261 * uniform - Set to 1 when an MTRR covers the region uniformly, i.e. the 262 * region is fully covered by a single MTRR entry or the default 263 * type. 264 */ 265 u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform) 266 { 267 u8 type, prev_type, is_uniform = 1, dummy; 268 int repeat; 269 u64 partial_end; 270 271 /* Make end inclusive instead of exclusive */ 272 end--; 273 274 if (!mtrr_state_set) 275 return MTRR_TYPE_INVALID; 276 277 if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED)) 278 return MTRR_TYPE_INVALID; 279 280 /* 281 * Look up the fixed ranges first, which take priority over 282 * the variable ranges. 283 */ 284 if ((start < 0x100000) && 285 (mtrr_state.have_fixed) && 286 (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) { 287 is_uniform = 0; 288 type = mtrr_type_lookup_fixed(start, end); 289 goto out; 290 } 291 292 /* 293 * Look up the variable ranges. Look of multiple ranges matching 294 * this address and pick type as per MTRR precedence. 295 */ 296 type = mtrr_type_lookup_variable(start, end, &partial_end, 297 &repeat, &is_uniform); 298 299 /* 300 * Common path is with repeat = 0. 301 * However, we can have cases where [start:end] spans across some 302 * MTRR ranges and/or the default type. Do repeated lookups for 303 * that case here. 304 */ 305 while (repeat) { 306 prev_type = type; 307 start = partial_end; 308 is_uniform = 0; 309 type = mtrr_type_lookup_variable(start, end, &partial_end, 310 &repeat, &dummy); 311 312 if (check_type_overlap(&prev_type, &type)) 313 goto out; 314 } 315 316 if (mtrr_tom2 && (start >= (1ULL<<32)) && (end < mtrr_tom2)) 317 type = MTRR_TYPE_WRBACK; 318 319 out: 320 *uniform = is_uniform; 321 return type; 322 } 323 324 /* Get the MSR pair relating to a var range */ 325 static void 326 get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr) 327 { 328 rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); 329 rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); 330 } 331 332 /* Fill the MSR pair relating to a var range */ 333 void fill_mtrr_var_range(unsigned int index, 334 u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi) 335 { 336 struct mtrr_var_range *vr; 337 338 vr = mtrr_state.var_ranges; 339 340 vr[index].base_lo = base_lo; 341 vr[index].base_hi = base_hi; 342 vr[index].mask_lo = mask_lo; 343 vr[index].mask_hi = mask_hi; 344 } 345 346 static void get_fixed_ranges(mtrr_type *frs) 347 { 348 unsigned int *p = (unsigned int *)frs; 349 int i; 350 351 k8_check_syscfg_dram_mod_en(); 352 353 rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]); 354 355 for (i = 0; i < 2; i++) 356 rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]); 357 for (i = 0; i < 8; i++) 358 rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]); 359 } 360 361 void mtrr_save_fixed_ranges(void *info) 362 { 363 if (boot_cpu_has(X86_FEATURE_MTRR)) 364 get_fixed_ranges(mtrr_state.fixed_ranges); 365 } 366 367 static unsigned __initdata last_fixed_start; 368 static unsigned __initdata last_fixed_end; 369 static mtrr_type __initdata last_fixed_type; 370 371 static void __init print_fixed_last(void) 372 { 373 if (!last_fixed_end) 374 return; 375 376 pr_debug(" %05X-%05X %s\n", last_fixed_start, 377 last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type)); 378 379 last_fixed_end = 0; 380 } 381 382 static void __init update_fixed_last(unsigned base, unsigned end, 383 mtrr_type type) 384 { 385 last_fixed_start = base; 386 last_fixed_end = end; 387 last_fixed_type = type; 388 } 389 390 static void __init 391 print_fixed(unsigned base, unsigned step, const mtrr_type *types) 392 { 393 unsigned i; 394 395 for (i = 0; i < 8; ++i, ++types, base += step) { 396 if (last_fixed_end == 0) { 397 update_fixed_last(base, base + step, *types); 398 continue; 399 } 400 if (last_fixed_end == base && last_fixed_type == *types) { 401 last_fixed_end = base + step; 402 continue; 403 } 404 /* new segments: gap or different type */ 405 print_fixed_last(); 406 update_fixed_last(base, base + step, *types); 407 } 408 } 409 410 static void __init print_mtrr_state(void) 411 { 412 unsigned int i; 413 int high_width; 414 415 pr_debug("MTRR default type: %s\n", 416 mtrr_attrib_to_str(mtrr_state.def_type)); 417 if (mtrr_state.have_fixed) { 418 pr_debug("MTRR fixed ranges %sabled:\n", 419 ((mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED) && 420 (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) ? 421 "en" : "dis"); 422 print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0); 423 for (i = 0; i < 2; ++i) 424 print_fixed(0x80000 + i * 0x20000, 0x04000, 425 mtrr_state.fixed_ranges + (i + 1) * 8); 426 for (i = 0; i < 8; ++i) 427 print_fixed(0xC0000 + i * 0x08000, 0x01000, 428 mtrr_state.fixed_ranges + (i + 3) * 8); 429 430 /* tail */ 431 print_fixed_last(); 432 } 433 pr_debug("MTRR variable ranges %sabled:\n", 434 mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED ? "en" : "dis"); 435 high_width = (boot_cpu_data.x86_phys_bits - (32 - PAGE_SHIFT) + 3) / 4; 436 437 for (i = 0; i < num_var_ranges; ++i) { 438 if (mtrr_state.var_ranges[i].mask_lo & (1 << 11)) 439 pr_debug(" %u base %0*X%05X000 mask %0*X%05X000 %s\n", 440 i, 441 high_width, 442 mtrr_state.var_ranges[i].base_hi, 443 mtrr_state.var_ranges[i].base_lo >> 12, 444 high_width, 445 mtrr_state.var_ranges[i].mask_hi, 446 mtrr_state.var_ranges[i].mask_lo >> 12, 447 mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff)); 448 else 449 pr_debug(" %u disabled\n", i); 450 } 451 if (mtrr_tom2) 452 pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20); 453 } 454 455 /* Grab all of the MTRR state for this CPU into *state */ 456 bool __init get_mtrr_state(void) 457 { 458 struct mtrr_var_range *vrs; 459 unsigned lo, dummy; 460 unsigned int i; 461 462 vrs = mtrr_state.var_ranges; 463 464 rdmsr(MSR_MTRRcap, lo, dummy); 465 mtrr_state.have_fixed = (lo >> 8) & 1; 466 467 for (i = 0; i < num_var_ranges; i++) 468 get_mtrr_var_range(i, &vrs[i]); 469 if (mtrr_state.have_fixed) 470 get_fixed_ranges(mtrr_state.fixed_ranges); 471 472 rdmsr(MSR_MTRRdefType, lo, dummy); 473 mtrr_state.def_type = (lo & 0xff); 474 mtrr_state.enabled = (lo & 0xc00) >> 10; 475 476 if (amd_special_default_mtrr()) { 477 unsigned low, high; 478 479 /* TOP_MEM2 */ 480 rdmsr(MSR_K8_TOP_MEM2, low, high); 481 mtrr_tom2 = high; 482 mtrr_tom2 <<= 32; 483 mtrr_tom2 |= low; 484 mtrr_tom2 &= 0xffffff800000ULL; 485 } 486 487 print_mtrr_state(); 488 489 mtrr_state_set = 1; 490 491 return !!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED); 492 } 493 494 /* Some BIOS's are messed up and don't set all MTRRs the same! */ 495 void __init mtrr_state_warn(void) 496 { 497 unsigned long mask = smp_changes_mask; 498 499 if (!mask) 500 return; 501 if (mask & MTRR_CHANGE_MASK_FIXED) 502 pr_warn("mtrr: your CPUs had inconsistent fixed MTRR settings\n"); 503 if (mask & MTRR_CHANGE_MASK_VARIABLE) 504 pr_warn("mtrr: your CPUs had inconsistent variable MTRR settings\n"); 505 if (mask & MTRR_CHANGE_MASK_DEFTYPE) 506 pr_warn("mtrr: your CPUs had inconsistent MTRRdefType settings\n"); 507 508 pr_info("mtrr: probably your BIOS does not setup all CPUs.\n"); 509 pr_info("mtrr: corrected configuration.\n"); 510 } 511 512 /* 513 * Doesn't attempt to pass an error out to MTRR users 514 * because it's quite complicated in some cases and probably not 515 * worth it because the best error handling is to ignore it. 516 */ 517 void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b) 518 { 519 if (wrmsr_safe(msr, a, b) < 0) { 520 pr_err("MTRR: CPU %u: Writing MSR %x to %x:%x failed\n", 521 smp_processor_id(), msr, a, b); 522 } 523 } 524 525 /** 526 * set_fixed_range - checks & updates a fixed-range MTRR if it 527 * differs from the value it should have 528 * @msr: MSR address of the MTTR which should be checked and updated 529 * @changed: pointer which indicates whether the MTRR needed to be changed 530 * @msrwords: pointer to the MSR values which the MSR should have 531 */ 532 static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords) 533 { 534 unsigned lo, hi; 535 536 rdmsr(msr, lo, hi); 537 538 if (lo != msrwords[0] || hi != msrwords[1]) { 539 mtrr_wrmsr(msr, msrwords[0], msrwords[1]); 540 *changed = true; 541 } 542 } 543 544 /** 545 * generic_get_free_region - Get a free MTRR. 546 * @base: The starting (base) address of the region. 547 * @size: The size (in bytes) of the region. 548 * @replace_reg: mtrr index to be replaced; set to invalid value if none. 549 * 550 * Returns: The index of the region on success, else negative on error. 551 */ 552 int 553 generic_get_free_region(unsigned long base, unsigned long size, int replace_reg) 554 { 555 unsigned long lbase, lsize; 556 mtrr_type ltype; 557 int i, max; 558 559 max = num_var_ranges; 560 if (replace_reg >= 0 && replace_reg < max) 561 return replace_reg; 562 563 for (i = 0; i < max; ++i) { 564 mtrr_if->get(i, &lbase, &lsize, <ype); 565 if (lsize == 0) 566 return i; 567 } 568 569 return -ENOSPC; 570 } 571 572 static void generic_get_mtrr(unsigned int reg, unsigned long *base, 573 unsigned long *size, mtrr_type *type) 574 { 575 u32 mask_lo, mask_hi, base_lo, base_hi; 576 unsigned int hi; 577 u64 tmp, mask; 578 579 /* 580 * get_mtrr doesn't need to update mtrr_state, also it could be called 581 * from any cpu, so try to print it out directly. 582 */ 583 get_cpu(); 584 585 rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); 586 587 if ((mask_lo & 0x800) == 0) { 588 /* Invalid (i.e. free) range */ 589 *base = 0; 590 *size = 0; 591 *type = 0; 592 goto out_put_cpu; 593 } 594 595 rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi); 596 597 /* Work out the shifted address mask: */ 598 tmp = (u64)mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT; 599 mask = size_or_mask | tmp; 600 601 /* Expand tmp with high bits to all 1s: */ 602 hi = fls64(tmp); 603 if (hi > 0) { 604 tmp |= ~((1ULL<<(hi - 1)) - 1); 605 606 if (tmp != mask) { 607 pr_warn("mtrr: your BIOS has configured an incorrect mask, fixing it.\n"); 608 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); 609 mask = tmp; 610 } 611 } 612 613 /* 614 * This works correctly if size is a power of two, i.e. a 615 * contiguous range: 616 */ 617 *size = -mask; 618 *base = (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT; 619 *type = base_lo & 0xff; 620 621 out_put_cpu: 622 put_cpu(); 623 } 624 625 /** 626 * set_fixed_ranges - checks & updates the fixed-range MTRRs if they 627 * differ from the saved set 628 * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges() 629 */ 630 static int set_fixed_ranges(mtrr_type *frs) 631 { 632 unsigned long long *saved = (unsigned long long *)frs; 633 bool changed = false; 634 int block = -1, range; 635 636 k8_check_syscfg_dram_mod_en(); 637 638 while (fixed_range_blocks[++block].ranges) { 639 for (range = 0; range < fixed_range_blocks[block].ranges; range++) 640 set_fixed_range(fixed_range_blocks[block].base_msr + range, 641 &changed, (unsigned int *)saved++); 642 } 643 644 return changed; 645 } 646 647 /* 648 * Set the MSR pair relating to a var range. 649 * Returns true if changes are made. 650 */ 651 static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr) 652 { 653 unsigned int lo, hi; 654 bool changed = false; 655 656 rdmsr(MTRRphysBase_MSR(index), lo, hi); 657 if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL) 658 || (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) != 659 (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) { 660 661 mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); 662 changed = true; 663 } 664 665 rdmsr(MTRRphysMask_MSR(index), lo, hi); 666 667 if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL) 668 || (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) != 669 (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) { 670 mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); 671 changed = true; 672 } 673 return changed; 674 } 675 676 static u32 deftype_lo, deftype_hi; 677 678 /** 679 * set_mtrr_state - Set the MTRR state for this CPU. 680 * 681 * NOTE: The CPU must already be in a safe state for MTRR changes, including 682 * measures that only a single CPU can be active in set_mtrr_state() in 683 * order to not be subject to races for usage of deftype_lo. This is 684 * accomplished by taking cache_disable_lock. 685 * RETURNS: 0 if no changes made, else a mask indicating what was changed. 686 */ 687 static unsigned long set_mtrr_state(void) 688 { 689 unsigned long change_mask = 0; 690 unsigned int i; 691 692 for (i = 0; i < num_var_ranges; i++) { 693 if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i])) 694 change_mask |= MTRR_CHANGE_MASK_VARIABLE; 695 } 696 697 if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges)) 698 change_mask |= MTRR_CHANGE_MASK_FIXED; 699 700 /* 701 * Set_mtrr_restore restores the old value of MTRRdefType, 702 * so to set it we fiddle with the saved value: 703 */ 704 if ((deftype_lo & 0xff) != mtrr_state.def_type 705 || ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) { 706 707 deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type | 708 (mtrr_state.enabled << 10); 709 change_mask |= MTRR_CHANGE_MASK_DEFTYPE; 710 } 711 712 return change_mask; 713 } 714 715 void mtrr_disable(void) 716 { 717 /* Save MTRR state */ 718 rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); 719 720 /* Disable MTRRs, and set the default type to uncached */ 721 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi); 722 } 723 724 void mtrr_enable(void) 725 { 726 /* Intel (P6) standard MTRRs */ 727 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); 728 } 729 730 void mtrr_generic_set_state(void) 731 { 732 unsigned long mask, count; 733 734 /* Actually set the state */ 735 mask = set_mtrr_state(); 736 737 /* Use the atomic bitops to update the global mask */ 738 for (count = 0; count < sizeof(mask) * 8; ++count) { 739 if (mask & 0x01) 740 set_bit(count, &smp_changes_mask); 741 mask >>= 1; 742 } 743 } 744 745 /** 746 * generic_set_mtrr - set variable MTRR register on the local CPU. 747 * 748 * @reg: The register to set. 749 * @base: The base address of the region. 750 * @size: The size of the region. If this is 0 the region is disabled. 751 * @type: The type of the region. 752 * 753 * Returns nothing. 754 */ 755 static void generic_set_mtrr(unsigned int reg, unsigned long base, 756 unsigned long size, mtrr_type type) 757 { 758 unsigned long flags; 759 struct mtrr_var_range *vr; 760 761 vr = &mtrr_state.var_ranges[reg]; 762 763 local_irq_save(flags); 764 cache_disable(); 765 766 if (size == 0) { 767 /* 768 * The invalid bit is kept in the mask, so we simply 769 * clear the relevant mask register to disable a range. 770 */ 771 mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0); 772 memset(vr, 0, sizeof(struct mtrr_var_range)); 773 } else { 774 vr->base_lo = base << PAGE_SHIFT | type; 775 vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT); 776 vr->mask_lo = -size << PAGE_SHIFT | 0x800; 777 vr->mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT); 778 779 mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi); 780 mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi); 781 } 782 783 cache_enable(); 784 local_irq_restore(flags); 785 } 786 787 int generic_validate_add_page(unsigned long base, unsigned long size, 788 unsigned int type) 789 { 790 unsigned long lbase, last; 791 792 /* 793 * For Intel PPro stepping <= 7 794 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF 795 */ 796 if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 && 797 boot_cpu_data.x86_model == 1 && 798 boot_cpu_data.x86_stepping <= 7) { 799 if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) { 800 pr_warn("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base); 801 return -EINVAL; 802 } 803 if (!(base + size < 0x70000 || base > 0x7003F) && 804 (type == MTRR_TYPE_WRCOMB 805 || type == MTRR_TYPE_WRBACK)) { 806 pr_warn("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n"); 807 return -EINVAL; 808 } 809 } 810 811 /* 812 * Check upper bits of base and last are equal and lower bits are 0 813 * for base and 1 for last 814 */ 815 last = base + size - 1; 816 for (lbase = base; !(lbase & 1) && (last & 1); 817 lbase = lbase >> 1, last = last >> 1) 818 ; 819 if (lbase != last) { 820 pr_warn("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size); 821 return -EINVAL; 822 } 823 return 0; 824 } 825 826 static int generic_have_wrcomb(void) 827 { 828 unsigned long config, dummy; 829 rdmsr(MSR_MTRRcap, config, dummy); 830 return config & (1 << 10); 831 } 832 833 int positive_have_wrcomb(void) 834 { 835 return 1; 836 } 837 838 /* 839 * Generic structure... 840 */ 841 const struct mtrr_ops generic_mtrr_ops = { 842 .get = generic_get_mtrr, 843 .get_free_region = generic_get_free_region, 844 .set = generic_set_mtrr, 845 .validate_add_page = generic_validate_add_page, 846 .have_wrcomb = generic_have_wrcomb, 847 }; 848