1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong 4 * because MTRRs can span up to 40 bits (36bits on most modern x86) 5 */ 6 7 #include <linux/export.h> 8 #include <linux/init.h> 9 #include <linux/io.h> 10 #include <linux/mm.h> 11 12 #include <asm/processor-flags.h> 13 #include <asm/cacheinfo.h> 14 #include <asm/cpufeature.h> 15 #include <asm/tlbflush.h> 16 #include <asm/mtrr.h> 17 #include <asm/msr.h> 18 #include <asm/memtype.h> 19 20 #include "mtrr.h" 21 22 struct fixed_range_block { 23 int base_msr; /* start address of an MTRR block */ 24 int ranges; /* number of MTRRs in this block */ 25 }; 26 27 static struct fixed_range_block fixed_range_blocks[] = { 28 { MSR_MTRRfix64K_00000, 1 }, /* one 64k MTRR */ 29 { MSR_MTRRfix16K_80000, 2 }, /* two 16k MTRRs */ 30 { MSR_MTRRfix4K_C0000, 8 }, /* eight 4k MTRRs */ 31 {} 32 }; 33 34 static unsigned long smp_changes_mask; 35 static int mtrr_state_set; 36 u64 mtrr_tom2; 37 38 struct mtrr_state_type mtrr_state; 39 EXPORT_SYMBOL_GPL(mtrr_state); 40 41 /* Reserved bits in the high portion of the MTRRphysBaseN MSR. */ 42 u32 phys_hi_rsvd; 43 44 /* 45 * BIOS is expected to clear MtrrFixDramModEn bit, see for example 46 * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD 47 * Opteron Processors" (26094 Rev. 3.30 February 2006), section 48 * "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set 49 * to 1 during BIOS initialization of the fixed MTRRs, then cleared to 50 * 0 for operation." 51 */ 52 static inline void k8_check_syscfg_dram_mod_en(void) 53 { 54 u32 lo, hi; 55 56 if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && 57 (boot_cpu_data.x86 >= 0x0f))) 58 return; 59 60 rdmsr(MSR_AMD64_SYSCFG, lo, hi); 61 if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) { 62 pr_err(FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]" 63 " not cleared by BIOS, clearing this bit\n", 64 smp_processor_id()); 65 lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY; 66 mtrr_wrmsr(MSR_AMD64_SYSCFG, lo, hi); 67 } 68 } 69 70 /* Get the size of contiguous MTRR range */ 71 static u64 get_mtrr_size(u64 mask) 72 { 73 u64 size; 74 75 mask |= (u64)phys_hi_rsvd << 32; 76 size = -mask; 77 78 return size; 79 } 80 81 /* 82 * Check and return the effective type for MTRR-MTRR type overlap. 83 * Returns 1 if the effective type is UNCACHEABLE, else returns 0 84 */ 85 static int check_type_overlap(u8 *prev, u8 *curr) 86 { 87 if (*prev == MTRR_TYPE_UNCACHABLE || *curr == MTRR_TYPE_UNCACHABLE) { 88 *prev = MTRR_TYPE_UNCACHABLE; 89 *curr = MTRR_TYPE_UNCACHABLE; 90 return 1; 91 } 92 93 if ((*prev == MTRR_TYPE_WRBACK && *curr == MTRR_TYPE_WRTHROUGH) || 94 (*prev == MTRR_TYPE_WRTHROUGH && *curr == MTRR_TYPE_WRBACK)) { 95 *prev = MTRR_TYPE_WRTHROUGH; 96 *curr = MTRR_TYPE_WRTHROUGH; 97 } 98 99 if (*prev != *curr) { 100 *prev = MTRR_TYPE_UNCACHABLE; 101 *curr = MTRR_TYPE_UNCACHABLE; 102 return 1; 103 } 104 105 return 0; 106 } 107 108 /** 109 * mtrr_type_lookup_fixed - look up memory type in MTRR fixed entries 110 * 111 * Return the MTRR fixed memory type of 'start'. 112 * 113 * MTRR fixed entries are divided into the following ways: 114 * 0x00000 - 0x7FFFF : This range is divided into eight 64KB sub-ranges 115 * 0x80000 - 0xBFFFF : This range is divided into sixteen 16KB sub-ranges 116 * 0xC0000 - 0xFFFFF : This range is divided into sixty-four 4KB sub-ranges 117 * 118 * Return Values: 119 * MTRR_TYPE_(type) - Matched memory type 120 * MTRR_TYPE_INVALID - Unmatched 121 */ 122 static u8 mtrr_type_lookup_fixed(u64 start, u64 end) 123 { 124 int idx; 125 126 if (start >= 0x100000) 127 return MTRR_TYPE_INVALID; 128 129 /* 0x0 - 0x7FFFF */ 130 if (start < 0x80000) { 131 idx = 0; 132 idx += (start >> 16); 133 return mtrr_state.fixed_ranges[idx]; 134 /* 0x80000 - 0xBFFFF */ 135 } else if (start < 0xC0000) { 136 idx = 1 * 8; 137 idx += ((start - 0x80000) >> 14); 138 return mtrr_state.fixed_ranges[idx]; 139 } 140 141 /* 0xC0000 - 0xFFFFF */ 142 idx = 3 * 8; 143 idx += ((start - 0xC0000) >> 12); 144 return mtrr_state.fixed_ranges[idx]; 145 } 146 147 /** 148 * mtrr_type_lookup_variable - look up memory type in MTRR variable entries 149 * 150 * Return Value: 151 * MTRR_TYPE_(type) - Matched memory type or default memory type (unmatched) 152 * 153 * Output Arguments: 154 * repeat - Set to 1 when [start:end] spanned across MTRR range and type 155 * returned corresponds only to [start:*partial_end]. Caller has 156 * to lookup again for [*partial_end:end]. 157 * 158 * uniform - Set to 1 when an MTRR covers the region uniformly, i.e. the 159 * region is fully covered by a single MTRR entry or the default 160 * type. 161 */ 162 static u8 mtrr_type_lookup_variable(u64 start, u64 end, u64 *partial_end, 163 int *repeat, u8 *uniform) 164 { 165 int i; 166 u64 base, mask; 167 u8 prev_match, curr_match; 168 169 *repeat = 0; 170 *uniform = 1; 171 172 prev_match = MTRR_TYPE_INVALID; 173 for (i = 0; i < num_var_ranges; ++i) { 174 unsigned short start_state, end_state, inclusive; 175 176 if (!(mtrr_state.var_ranges[i].mask_lo & MTRR_PHYSMASK_V)) 177 continue; 178 179 base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) + 180 (mtrr_state.var_ranges[i].base_lo & PAGE_MASK); 181 mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) + 182 (mtrr_state.var_ranges[i].mask_lo & PAGE_MASK); 183 184 start_state = ((start & mask) == (base & mask)); 185 end_state = ((end & mask) == (base & mask)); 186 inclusive = ((start < base) && (end > base)); 187 188 if ((start_state != end_state) || inclusive) { 189 /* 190 * We have start:end spanning across an MTRR. 191 * We split the region into either 192 * 193 * - start_state:1 194 * (start:mtrr_end)(mtrr_end:end) 195 * - end_state:1 196 * (start:mtrr_start)(mtrr_start:end) 197 * - inclusive:1 198 * (start:mtrr_start)(mtrr_start:mtrr_end)(mtrr_end:end) 199 * 200 * depending on kind of overlap. 201 * 202 * Return the type of the first region and a pointer 203 * to the start of next region so that caller will be 204 * advised to lookup again after having adjusted start 205 * and end. 206 * 207 * Note: This way we handle overlaps with multiple 208 * entries and the default type properly. 209 */ 210 if (start_state) 211 *partial_end = base + get_mtrr_size(mask); 212 else 213 *partial_end = base; 214 215 if (unlikely(*partial_end <= start)) { 216 WARN_ON(1); 217 *partial_end = start + PAGE_SIZE; 218 } 219 220 end = *partial_end - 1; /* end is inclusive */ 221 *repeat = 1; 222 *uniform = 0; 223 } 224 225 if ((start & mask) != (base & mask)) 226 continue; 227 228 curr_match = mtrr_state.var_ranges[i].base_lo & MTRR_PHYSBASE_TYPE; 229 if (prev_match == MTRR_TYPE_INVALID) { 230 prev_match = curr_match; 231 continue; 232 } 233 234 *uniform = 0; 235 if (check_type_overlap(&prev_match, &curr_match)) 236 return curr_match; 237 } 238 239 if (prev_match != MTRR_TYPE_INVALID) 240 return prev_match; 241 242 return mtrr_state.def_type; 243 } 244 245 /** 246 * mtrr_type_lookup - look up memory type in MTRR 247 * 248 * Return Values: 249 * MTRR_TYPE_(type) - The effective MTRR type for the region 250 * MTRR_TYPE_INVALID - MTRR is disabled 251 * 252 * Output Argument: 253 * uniform - Set to 1 when an MTRR covers the region uniformly, i.e. the 254 * region is fully covered by a single MTRR entry or the default 255 * type. 256 */ 257 u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform) 258 { 259 u8 type, prev_type, is_uniform = 1, dummy; 260 int repeat; 261 u64 partial_end; 262 263 /* Make end inclusive instead of exclusive */ 264 end--; 265 266 if (!mtrr_state_set) 267 return MTRR_TYPE_INVALID; 268 269 if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED)) 270 return MTRR_TYPE_INVALID; 271 272 /* 273 * Look up the fixed ranges first, which take priority over 274 * the variable ranges. 275 */ 276 if ((start < 0x100000) && 277 (mtrr_state.have_fixed) && 278 (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) { 279 is_uniform = 0; 280 type = mtrr_type_lookup_fixed(start, end); 281 goto out; 282 } 283 284 /* 285 * Look up the variable ranges. Look of multiple ranges matching 286 * this address and pick type as per MTRR precedence. 287 */ 288 type = mtrr_type_lookup_variable(start, end, &partial_end, 289 &repeat, &is_uniform); 290 291 /* 292 * Common path is with repeat = 0. 293 * However, we can have cases where [start:end] spans across some 294 * MTRR ranges and/or the default type. Do repeated lookups for 295 * that case here. 296 */ 297 while (repeat) { 298 prev_type = type; 299 start = partial_end; 300 is_uniform = 0; 301 type = mtrr_type_lookup_variable(start, end, &partial_end, 302 &repeat, &dummy); 303 304 if (check_type_overlap(&prev_type, &type)) 305 goto out; 306 } 307 308 if (mtrr_tom2 && (start >= (1ULL<<32)) && (end < mtrr_tom2)) 309 type = MTRR_TYPE_WRBACK; 310 311 out: 312 *uniform = is_uniform; 313 return type; 314 } 315 316 /* Get the MSR pair relating to a var range */ 317 static void 318 get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr) 319 { 320 rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); 321 rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); 322 } 323 324 /* Fill the MSR pair relating to a var range */ 325 void fill_mtrr_var_range(unsigned int index, 326 u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi) 327 { 328 struct mtrr_var_range *vr; 329 330 vr = mtrr_state.var_ranges; 331 332 vr[index].base_lo = base_lo; 333 vr[index].base_hi = base_hi; 334 vr[index].mask_lo = mask_lo; 335 vr[index].mask_hi = mask_hi; 336 } 337 338 static void get_fixed_ranges(mtrr_type *frs) 339 { 340 unsigned int *p = (unsigned int *)frs; 341 int i; 342 343 k8_check_syscfg_dram_mod_en(); 344 345 rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]); 346 347 for (i = 0; i < 2; i++) 348 rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]); 349 for (i = 0; i < 8; i++) 350 rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]); 351 } 352 353 void mtrr_save_fixed_ranges(void *info) 354 { 355 if (boot_cpu_has(X86_FEATURE_MTRR)) 356 get_fixed_ranges(mtrr_state.fixed_ranges); 357 } 358 359 static unsigned __initdata last_fixed_start; 360 static unsigned __initdata last_fixed_end; 361 static mtrr_type __initdata last_fixed_type; 362 363 static void __init print_fixed_last(void) 364 { 365 if (!last_fixed_end) 366 return; 367 368 pr_debug(" %05X-%05X %s\n", last_fixed_start, 369 last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type)); 370 371 last_fixed_end = 0; 372 } 373 374 static void __init update_fixed_last(unsigned base, unsigned end, 375 mtrr_type type) 376 { 377 last_fixed_start = base; 378 last_fixed_end = end; 379 last_fixed_type = type; 380 } 381 382 static void __init 383 print_fixed(unsigned base, unsigned step, const mtrr_type *types) 384 { 385 unsigned i; 386 387 for (i = 0; i < 8; ++i, ++types, base += step) { 388 if (last_fixed_end == 0) { 389 update_fixed_last(base, base + step, *types); 390 continue; 391 } 392 if (last_fixed_end == base && last_fixed_type == *types) { 393 last_fixed_end = base + step; 394 continue; 395 } 396 /* new segments: gap or different type */ 397 print_fixed_last(); 398 update_fixed_last(base, base + step, *types); 399 } 400 } 401 402 static void __init print_mtrr_state(void) 403 { 404 unsigned int i; 405 int high_width; 406 407 pr_debug("MTRR default type: %s\n", 408 mtrr_attrib_to_str(mtrr_state.def_type)); 409 if (mtrr_state.have_fixed) { 410 pr_debug("MTRR fixed ranges %sabled:\n", 411 ((mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED) && 412 (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) ? 413 "en" : "dis"); 414 print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0); 415 for (i = 0; i < 2; ++i) 416 print_fixed(0x80000 + i * 0x20000, 0x04000, 417 mtrr_state.fixed_ranges + (i + 1) * 8); 418 for (i = 0; i < 8; ++i) 419 print_fixed(0xC0000 + i * 0x08000, 0x01000, 420 mtrr_state.fixed_ranges + (i + 3) * 8); 421 422 /* tail */ 423 print_fixed_last(); 424 } 425 pr_debug("MTRR variable ranges %sabled:\n", 426 mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED ? "en" : "dis"); 427 high_width = (boot_cpu_data.x86_phys_bits - (32 - PAGE_SHIFT) + 3) / 4; 428 429 for (i = 0; i < num_var_ranges; ++i) { 430 if (mtrr_state.var_ranges[i].mask_lo & MTRR_PHYSMASK_V) 431 pr_debug(" %u base %0*X%05X000 mask %0*X%05X000 %s\n", 432 i, 433 high_width, 434 mtrr_state.var_ranges[i].base_hi, 435 mtrr_state.var_ranges[i].base_lo >> 12, 436 high_width, 437 mtrr_state.var_ranges[i].mask_hi, 438 mtrr_state.var_ranges[i].mask_lo >> 12, 439 mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 440 MTRR_PHYSBASE_TYPE)); 441 else 442 pr_debug(" %u disabled\n", i); 443 } 444 if (mtrr_tom2) 445 pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20); 446 } 447 448 /* Grab all of the MTRR state for this CPU into *state */ 449 bool __init get_mtrr_state(void) 450 { 451 struct mtrr_var_range *vrs; 452 unsigned lo, dummy; 453 unsigned int i; 454 455 vrs = mtrr_state.var_ranges; 456 457 rdmsr(MSR_MTRRcap, lo, dummy); 458 mtrr_state.have_fixed = lo & MTRR_CAP_FIX; 459 460 for (i = 0; i < num_var_ranges; i++) 461 get_mtrr_var_range(i, &vrs[i]); 462 if (mtrr_state.have_fixed) 463 get_fixed_ranges(mtrr_state.fixed_ranges); 464 465 rdmsr(MSR_MTRRdefType, lo, dummy); 466 mtrr_state.def_type = lo & MTRR_DEF_TYPE_TYPE; 467 mtrr_state.enabled = (lo & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT; 468 469 if (amd_special_default_mtrr()) { 470 unsigned low, high; 471 472 /* TOP_MEM2 */ 473 rdmsr(MSR_K8_TOP_MEM2, low, high); 474 mtrr_tom2 = high; 475 mtrr_tom2 <<= 32; 476 mtrr_tom2 |= low; 477 mtrr_tom2 &= 0xffffff800000ULL; 478 } 479 480 print_mtrr_state(); 481 482 mtrr_state_set = 1; 483 484 return !!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED); 485 } 486 487 /* Some BIOS's are messed up and don't set all MTRRs the same! */ 488 void __init mtrr_state_warn(void) 489 { 490 unsigned long mask = smp_changes_mask; 491 492 if (!mask) 493 return; 494 if (mask & MTRR_CHANGE_MASK_FIXED) 495 pr_warn("mtrr: your CPUs had inconsistent fixed MTRR settings\n"); 496 if (mask & MTRR_CHANGE_MASK_VARIABLE) 497 pr_warn("mtrr: your CPUs had inconsistent variable MTRR settings\n"); 498 if (mask & MTRR_CHANGE_MASK_DEFTYPE) 499 pr_warn("mtrr: your CPUs had inconsistent MTRRdefType settings\n"); 500 501 pr_info("mtrr: probably your BIOS does not setup all CPUs.\n"); 502 pr_info("mtrr: corrected configuration.\n"); 503 } 504 505 /* 506 * Doesn't attempt to pass an error out to MTRR users 507 * because it's quite complicated in some cases and probably not 508 * worth it because the best error handling is to ignore it. 509 */ 510 void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b) 511 { 512 if (wrmsr_safe(msr, a, b) < 0) { 513 pr_err("MTRR: CPU %u: Writing MSR %x to %x:%x failed\n", 514 smp_processor_id(), msr, a, b); 515 } 516 } 517 518 /** 519 * set_fixed_range - checks & updates a fixed-range MTRR if it 520 * differs from the value it should have 521 * @msr: MSR address of the MTTR which should be checked and updated 522 * @changed: pointer which indicates whether the MTRR needed to be changed 523 * @msrwords: pointer to the MSR values which the MSR should have 524 */ 525 static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords) 526 { 527 unsigned lo, hi; 528 529 rdmsr(msr, lo, hi); 530 531 if (lo != msrwords[0] || hi != msrwords[1]) { 532 mtrr_wrmsr(msr, msrwords[0], msrwords[1]); 533 *changed = true; 534 } 535 } 536 537 /** 538 * generic_get_free_region - Get a free MTRR. 539 * @base: The starting (base) address of the region. 540 * @size: The size (in bytes) of the region. 541 * @replace_reg: mtrr index to be replaced; set to invalid value if none. 542 * 543 * Returns: The index of the region on success, else negative on error. 544 */ 545 int 546 generic_get_free_region(unsigned long base, unsigned long size, int replace_reg) 547 { 548 unsigned long lbase, lsize; 549 mtrr_type ltype; 550 int i, max; 551 552 max = num_var_ranges; 553 if (replace_reg >= 0 && replace_reg < max) 554 return replace_reg; 555 556 for (i = 0; i < max; ++i) { 557 mtrr_if->get(i, &lbase, &lsize, <ype); 558 if (lsize == 0) 559 return i; 560 } 561 562 return -ENOSPC; 563 } 564 565 static void generic_get_mtrr(unsigned int reg, unsigned long *base, 566 unsigned long *size, mtrr_type *type) 567 { 568 u32 mask_lo, mask_hi, base_lo, base_hi; 569 unsigned int hi; 570 u64 tmp, mask; 571 572 /* 573 * get_mtrr doesn't need to update mtrr_state, also it could be called 574 * from any cpu, so try to print it out directly. 575 */ 576 get_cpu(); 577 578 rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); 579 580 if (!(mask_lo & MTRR_PHYSMASK_V)) { 581 /* Invalid (i.e. free) range */ 582 *base = 0; 583 *size = 0; 584 *type = 0; 585 goto out_put_cpu; 586 } 587 588 rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi); 589 590 /* Work out the shifted address mask: */ 591 tmp = (u64)mask_hi << 32 | (mask_lo & PAGE_MASK); 592 mask = (u64)phys_hi_rsvd << 32 | tmp; 593 594 /* Expand tmp with high bits to all 1s: */ 595 hi = fls64(tmp); 596 if (hi > 0) { 597 tmp |= ~((1ULL<<(hi - 1)) - 1); 598 599 if (tmp != mask) { 600 pr_warn("mtrr: your BIOS has configured an incorrect mask, fixing it.\n"); 601 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); 602 mask = tmp; 603 } 604 } 605 606 /* 607 * This works correctly if size is a power of two, i.e. a 608 * contiguous range: 609 */ 610 *size = -mask >> PAGE_SHIFT; 611 *base = (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT; 612 *type = base_lo & MTRR_PHYSBASE_TYPE; 613 614 out_put_cpu: 615 put_cpu(); 616 } 617 618 /** 619 * set_fixed_ranges - checks & updates the fixed-range MTRRs if they 620 * differ from the saved set 621 * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges() 622 */ 623 static int set_fixed_ranges(mtrr_type *frs) 624 { 625 unsigned long long *saved = (unsigned long long *)frs; 626 bool changed = false; 627 int block = -1, range; 628 629 k8_check_syscfg_dram_mod_en(); 630 631 while (fixed_range_blocks[++block].ranges) { 632 for (range = 0; range < fixed_range_blocks[block].ranges; range++) 633 set_fixed_range(fixed_range_blocks[block].base_msr + range, 634 &changed, (unsigned int *)saved++); 635 } 636 637 return changed; 638 } 639 640 /* 641 * Set the MSR pair relating to a var range. 642 * Returns true if changes are made. 643 */ 644 static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr) 645 { 646 unsigned int lo, hi; 647 bool changed = false; 648 649 rdmsr(MTRRphysBase_MSR(index), lo, hi); 650 if ((vr->base_lo & ~MTRR_PHYSBASE_RSVD) != (lo & ~MTRR_PHYSBASE_RSVD) 651 || (vr->base_hi & ~phys_hi_rsvd) != (hi & ~phys_hi_rsvd)) { 652 653 mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); 654 changed = true; 655 } 656 657 rdmsr(MTRRphysMask_MSR(index), lo, hi); 658 659 if ((vr->mask_lo & ~MTRR_PHYSMASK_RSVD) != (lo & ~MTRR_PHYSMASK_RSVD) 660 || (vr->mask_hi & ~phys_hi_rsvd) != (hi & ~phys_hi_rsvd)) { 661 mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); 662 changed = true; 663 } 664 return changed; 665 } 666 667 static u32 deftype_lo, deftype_hi; 668 669 /** 670 * set_mtrr_state - Set the MTRR state for this CPU. 671 * 672 * NOTE: The CPU must already be in a safe state for MTRR changes, including 673 * measures that only a single CPU can be active in set_mtrr_state() in 674 * order to not be subject to races for usage of deftype_lo. This is 675 * accomplished by taking cache_disable_lock. 676 * RETURNS: 0 if no changes made, else a mask indicating what was changed. 677 */ 678 static unsigned long set_mtrr_state(void) 679 { 680 unsigned long change_mask = 0; 681 unsigned int i; 682 683 for (i = 0; i < num_var_ranges; i++) { 684 if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i])) 685 change_mask |= MTRR_CHANGE_MASK_VARIABLE; 686 } 687 688 if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges)) 689 change_mask |= MTRR_CHANGE_MASK_FIXED; 690 691 /* 692 * Set_mtrr_restore restores the old value of MTRRdefType, 693 * so to set it we fiddle with the saved value: 694 */ 695 if ((deftype_lo & MTRR_DEF_TYPE_TYPE) != mtrr_state.def_type || 696 ((deftype_lo & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT) != mtrr_state.enabled) { 697 698 deftype_lo = (deftype_lo & MTRR_DEF_TYPE_DISABLE) | 699 mtrr_state.def_type | 700 (mtrr_state.enabled << MTRR_STATE_SHIFT); 701 change_mask |= MTRR_CHANGE_MASK_DEFTYPE; 702 } 703 704 return change_mask; 705 } 706 707 void mtrr_disable(void) 708 { 709 /* Save MTRR state */ 710 rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); 711 712 /* Disable MTRRs, and set the default type to uncached */ 713 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & MTRR_DEF_TYPE_DISABLE, deftype_hi); 714 } 715 716 void mtrr_enable(void) 717 { 718 /* Intel (P6) standard MTRRs */ 719 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); 720 } 721 722 void mtrr_generic_set_state(void) 723 { 724 unsigned long mask, count; 725 726 /* Actually set the state */ 727 mask = set_mtrr_state(); 728 729 /* Use the atomic bitops to update the global mask */ 730 for (count = 0; count < sizeof(mask) * 8; ++count) { 731 if (mask & 0x01) 732 set_bit(count, &smp_changes_mask); 733 mask >>= 1; 734 } 735 } 736 737 /** 738 * generic_set_mtrr - set variable MTRR register on the local CPU. 739 * 740 * @reg: The register to set. 741 * @base: The base address of the region. 742 * @size: The size of the region. If this is 0 the region is disabled. 743 * @type: The type of the region. 744 * 745 * Returns nothing. 746 */ 747 static void generic_set_mtrr(unsigned int reg, unsigned long base, 748 unsigned long size, mtrr_type type) 749 { 750 unsigned long flags; 751 struct mtrr_var_range *vr; 752 753 vr = &mtrr_state.var_ranges[reg]; 754 755 local_irq_save(flags); 756 cache_disable(); 757 758 if (size == 0) { 759 /* 760 * The invalid bit is kept in the mask, so we simply 761 * clear the relevant mask register to disable a range. 762 */ 763 mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0); 764 memset(vr, 0, sizeof(struct mtrr_var_range)); 765 } else { 766 vr->base_lo = base << PAGE_SHIFT | type; 767 vr->base_hi = (base >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; 768 vr->mask_lo = -size << PAGE_SHIFT | MTRR_PHYSMASK_V; 769 vr->mask_hi = (-size >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; 770 771 mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi); 772 mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi); 773 } 774 775 cache_enable(); 776 local_irq_restore(flags); 777 } 778 779 int generic_validate_add_page(unsigned long base, unsigned long size, 780 unsigned int type) 781 { 782 unsigned long lbase, last; 783 784 /* 785 * For Intel PPro stepping <= 7 786 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF 787 */ 788 if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 && 789 boot_cpu_data.x86_model == 1 && 790 boot_cpu_data.x86_stepping <= 7) { 791 if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) { 792 pr_warn("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base); 793 return -EINVAL; 794 } 795 if (!(base + size < 0x70000 || base > 0x7003F) && 796 (type == MTRR_TYPE_WRCOMB 797 || type == MTRR_TYPE_WRBACK)) { 798 pr_warn("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n"); 799 return -EINVAL; 800 } 801 } 802 803 /* 804 * Check upper bits of base and last are equal and lower bits are 0 805 * for base and 1 for last 806 */ 807 last = base + size - 1; 808 for (lbase = base; !(lbase & 1) && (last & 1); 809 lbase = lbase >> 1, last = last >> 1) 810 ; 811 if (lbase != last) { 812 pr_warn("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size); 813 return -EINVAL; 814 } 815 return 0; 816 } 817 818 static int generic_have_wrcomb(void) 819 { 820 unsigned long config, dummy; 821 rdmsr(MSR_MTRRcap, config, dummy); 822 return config & MTRR_CAP_WC; 823 } 824 825 int positive_have_wrcomb(void) 826 { 827 return 1; 828 } 829 830 /* 831 * Generic structure... 832 */ 833 const struct mtrr_ops generic_mtrr_ops = { 834 .get = generic_get_mtrr, 835 .get_free_region = generic_get_free_region, 836 .set = generic_set_mtrr, 837 .validate_add_page = generic_validate_add_page, 838 .have_wrcomb = generic_have_wrcomb, 839 }; 840