1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong 4 * because MTRRs can span up to 40 bits (36bits on most modern x86) 5 */ 6 7 #include <linux/export.h> 8 #include <linux/init.h> 9 #include <linux/io.h> 10 #include <linux/mm.h> 11 #include <linux/cc_platform.h> 12 #include <asm/processor-flags.h> 13 #include <asm/cacheinfo.h> 14 #include <asm/cpufeature.h> 15 #include <asm/hypervisor.h> 16 #include <asm/mshyperv.h> 17 #include <asm/tlbflush.h> 18 #include <asm/mtrr.h> 19 #include <asm/msr.h> 20 #include <asm/memtype.h> 21 22 #include "mtrr.h" 23 24 struct fixed_range_block { 25 int base_msr; /* start address of an MTRR block */ 26 int ranges; /* number of MTRRs in this block */ 27 }; 28 29 static struct fixed_range_block fixed_range_blocks[] = { 30 { MSR_MTRRfix64K_00000, 1 }, /* one 64k MTRR */ 31 { MSR_MTRRfix16K_80000, 2 }, /* two 16k MTRRs */ 32 { MSR_MTRRfix4K_C0000, 8 }, /* eight 4k MTRRs */ 33 {} 34 }; 35 36 struct cache_map { 37 u64 start; 38 u64 end; 39 u64 flags; 40 u64 type:8; 41 u64 fixed:1; 42 }; 43 44 static bool mtrr_debug; 45 46 static int __init mtrr_param_setup(char *str) 47 { 48 int rc = 0; 49 50 if (!str) 51 return -EINVAL; 52 if (!strcmp(str, "debug")) 53 mtrr_debug = true; 54 else 55 rc = -EINVAL; 56 57 return rc; 58 } 59 early_param("mtrr", mtrr_param_setup); 60 61 /* 62 * CACHE_MAP_MAX is the maximum number of memory ranges in cache_map, where 63 * no 2 adjacent ranges have the same cache mode (those would be merged). 64 * The number is based on the worst case: 65 * - no two adjacent fixed MTRRs share the same cache mode 66 * - one variable MTRR is spanning a huge area with mode WB 67 * - 255 variable MTRRs with mode UC all overlap with the WB MTRR, creating 2 68 * additional ranges each (result like "ababababa...aba" with a = WB, b = UC), 69 * accounting for MTRR_MAX_VAR_RANGES * 2 - 1 range entries 70 * - a TOP_MEM2 area (even with overlapping an UC MTRR can't add 2 range entries 71 * to the possible maximum, as it always starts at 4GB, thus it can't be in 72 * the middle of that MTRR, unless that MTRR starts at 0, which would remove 73 * the initial "a" from the "abababa" pattern above) 74 * The map won't contain ranges with no matching MTRR (those fall back to the 75 * default cache mode). 76 */ 77 #define CACHE_MAP_MAX (MTRR_NUM_FIXED_RANGES + MTRR_MAX_VAR_RANGES * 2) 78 79 static struct cache_map init_cache_map[CACHE_MAP_MAX] __initdata; 80 static struct cache_map *cache_map __refdata = init_cache_map; 81 static unsigned int cache_map_size = CACHE_MAP_MAX; 82 static unsigned int cache_map_n; 83 static unsigned int cache_map_fixed; 84 85 static unsigned long smp_changes_mask; 86 static int mtrr_state_set; 87 u64 mtrr_tom2; 88 89 struct mtrr_state_type mtrr_state; 90 EXPORT_SYMBOL_GPL(mtrr_state); 91 92 /* Reserved bits in the high portion of the MTRRphysBaseN MSR. */ 93 u32 phys_hi_rsvd; 94 95 /* 96 * BIOS is expected to clear MtrrFixDramModEn bit, see for example 97 * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD 98 * Opteron Processors" (26094 Rev. 3.30 February 2006), section 99 * "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set 100 * to 1 during BIOS initialization of the fixed MTRRs, then cleared to 101 * 0 for operation." 102 */ 103 static inline void k8_check_syscfg_dram_mod_en(void) 104 { 105 u32 lo, hi; 106 107 if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && 108 (boot_cpu_data.x86 >= 0x0f))) 109 return; 110 111 rdmsr(MSR_AMD64_SYSCFG, lo, hi); 112 if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) { 113 pr_err(FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]" 114 " not cleared by BIOS, clearing this bit\n", 115 smp_processor_id()); 116 lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY; 117 mtrr_wrmsr(MSR_AMD64_SYSCFG, lo, hi); 118 } 119 } 120 121 /* Get the size of contiguous MTRR range */ 122 static u64 get_mtrr_size(u64 mask) 123 { 124 u64 size; 125 126 mask |= (u64)phys_hi_rsvd << 32; 127 size = -mask; 128 129 return size; 130 } 131 132 static u8 get_var_mtrr_state(unsigned int reg, u64 *start, u64 *size) 133 { 134 struct mtrr_var_range *mtrr = mtrr_state.var_ranges + reg; 135 136 if (!(mtrr->mask_lo & MTRR_PHYSMASK_V)) 137 return MTRR_TYPE_INVALID; 138 139 *start = (((u64)mtrr->base_hi) << 32) + (mtrr->base_lo & PAGE_MASK); 140 *size = get_mtrr_size((((u64)mtrr->mask_hi) << 32) + 141 (mtrr->mask_lo & PAGE_MASK)); 142 143 return mtrr->base_lo & MTRR_PHYSBASE_TYPE; 144 } 145 146 static u8 get_effective_type(u8 type1, u8 type2) 147 { 148 if (type1 == MTRR_TYPE_UNCACHABLE || type2 == MTRR_TYPE_UNCACHABLE) 149 return MTRR_TYPE_UNCACHABLE; 150 151 if ((type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH) || 152 (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK)) 153 return MTRR_TYPE_WRTHROUGH; 154 155 if (type1 != type2) 156 return MTRR_TYPE_UNCACHABLE; 157 158 return type1; 159 } 160 161 /* 162 * Check and return the effective type for MTRR-MTRR type overlap. 163 * Returns true if the effective type is UNCACHEABLE, else returns false 164 */ 165 static bool check_type_overlap(u8 *prev, u8 *curr) 166 { 167 *prev = *curr = get_effective_type(*curr, *prev); 168 169 return *prev == MTRR_TYPE_UNCACHABLE; 170 } 171 172 /** 173 * mtrr_type_lookup_fixed - look up memory type in MTRR fixed entries 174 * 175 * Return the MTRR fixed memory type of 'start'. 176 * 177 * MTRR fixed entries are divided into the following ways: 178 * 0x00000 - 0x7FFFF : This range is divided into eight 64KB sub-ranges 179 * 0x80000 - 0xBFFFF : This range is divided into sixteen 16KB sub-ranges 180 * 0xC0000 - 0xFFFFF : This range is divided into sixty-four 4KB sub-ranges 181 * 182 * Return Values: 183 * MTRR_TYPE_(type) - Matched memory type 184 * MTRR_TYPE_INVALID - Unmatched 185 */ 186 static u8 mtrr_type_lookup_fixed(u64 start, u64 end) 187 { 188 int idx; 189 190 if (start >= 0x100000) 191 return MTRR_TYPE_INVALID; 192 193 /* 0x0 - 0x7FFFF */ 194 if (start < 0x80000) { 195 idx = 0; 196 idx += (start >> 16); 197 return mtrr_state.fixed_ranges[idx]; 198 /* 0x80000 - 0xBFFFF */ 199 } else if (start < 0xC0000) { 200 idx = 1 * 8; 201 idx += ((start - 0x80000) >> 14); 202 return mtrr_state.fixed_ranges[idx]; 203 } 204 205 /* 0xC0000 - 0xFFFFF */ 206 idx = 3 * 8; 207 idx += ((start - 0xC0000) >> 12); 208 return mtrr_state.fixed_ranges[idx]; 209 } 210 211 /** 212 * mtrr_type_lookup_variable - look up memory type in MTRR variable entries 213 * 214 * Return Value: 215 * MTRR_TYPE_(type) - Matched memory type or default memory type (unmatched) 216 * 217 * Output Arguments: 218 * repeat - Set to 1 when [start:end] spanned across MTRR range and type 219 * returned corresponds only to [start:*partial_end]. Caller has 220 * to lookup again for [*partial_end:end]. 221 * 222 * uniform - Set to 1 when an MTRR covers the region uniformly, i.e. the 223 * region is fully covered by a single MTRR entry or the default 224 * type. 225 */ 226 static u8 mtrr_type_lookup_variable(u64 start, u64 end, u64 *partial_end, 227 int *repeat, u8 *uniform) 228 { 229 int i; 230 u64 base, mask; 231 u8 prev_match, curr_match; 232 233 *repeat = 0; 234 *uniform = 1; 235 236 prev_match = MTRR_TYPE_INVALID; 237 for (i = 0; i < num_var_ranges; ++i) { 238 unsigned short start_state, end_state, inclusive; 239 240 if (!(mtrr_state.var_ranges[i].mask_lo & MTRR_PHYSMASK_V)) 241 continue; 242 243 base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) + 244 (mtrr_state.var_ranges[i].base_lo & PAGE_MASK); 245 mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) + 246 (mtrr_state.var_ranges[i].mask_lo & PAGE_MASK); 247 248 start_state = ((start & mask) == (base & mask)); 249 end_state = ((end & mask) == (base & mask)); 250 inclusive = ((start < base) && (end > base)); 251 252 if ((start_state != end_state) || inclusive) { 253 /* 254 * We have start:end spanning across an MTRR. 255 * We split the region into either 256 * 257 * - start_state:1 258 * (start:mtrr_end)(mtrr_end:end) 259 * - end_state:1 260 * (start:mtrr_start)(mtrr_start:end) 261 * - inclusive:1 262 * (start:mtrr_start)(mtrr_start:mtrr_end)(mtrr_end:end) 263 * 264 * depending on kind of overlap. 265 * 266 * Return the type of the first region and a pointer 267 * to the start of next region so that caller will be 268 * advised to lookup again after having adjusted start 269 * and end. 270 * 271 * Note: This way we handle overlaps with multiple 272 * entries and the default type properly. 273 */ 274 if (start_state) 275 *partial_end = base + get_mtrr_size(mask); 276 else 277 *partial_end = base; 278 279 if (unlikely(*partial_end <= start)) { 280 WARN_ON(1); 281 *partial_end = start + PAGE_SIZE; 282 } 283 284 end = *partial_end - 1; /* end is inclusive */ 285 *repeat = 1; 286 *uniform = 0; 287 } 288 289 if ((start & mask) != (base & mask)) 290 continue; 291 292 curr_match = mtrr_state.var_ranges[i].base_lo & MTRR_PHYSBASE_TYPE; 293 if (prev_match == MTRR_TYPE_INVALID) { 294 prev_match = curr_match; 295 continue; 296 } 297 298 *uniform = 0; 299 if (check_type_overlap(&prev_match, &curr_match)) 300 return curr_match; 301 } 302 303 if (prev_match != MTRR_TYPE_INVALID) 304 return prev_match; 305 306 return mtrr_state.def_type; 307 } 308 309 static void rm_map_entry_at(int idx) 310 { 311 cache_map_n--; 312 if (cache_map_n > idx) { 313 memmove(cache_map + idx, cache_map + idx + 1, 314 sizeof(*cache_map) * (cache_map_n - idx)); 315 } 316 } 317 318 /* 319 * Add an entry into cache_map at a specific index. Merges adjacent entries if 320 * appropriate. Return the number of merges for correcting the scan index 321 * (this is needed as merging will reduce the number of entries, which will 322 * result in skipping entries in future iterations if the scan index isn't 323 * corrected). 324 * Note that the corrected index can never go below -1 (resulting in being 0 in 325 * the next scan iteration), as "2" is returned only if the current index is 326 * larger than zero. 327 */ 328 static int add_map_entry_at(u64 start, u64 end, u8 type, int idx) 329 { 330 bool merge_prev = false, merge_next = false; 331 332 if (start >= end) 333 return 0; 334 335 if (idx > 0) { 336 struct cache_map *prev = cache_map + idx - 1; 337 338 if (!prev->fixed && start == prev->end && type == prev->type) 339 merge_prev = true; 340 } 341 342 if (idx < cache_map_n) { 343 struct cache_map *next = cache_map + idx; 344 345 if (!next->fixed && end == next->start && type == next->type) 346 merge_next = true; 347 } 348 349 if (merge_prev && merge_next) { 350 cache_map[idx - 1].end = cache_map[idx].end; 351 rm_map_entry_at(idx); 352 return 2; 353 } 354 if (merge_prev) { 355 cache_map[idx - 1].end = end; 356 return 1; 357 } 358 if (merge_next) { 359 cache_map[idx].start = start; 360 return 1; 361 } 362 363 /* Sanity check: the array should NEVER be too small! */ 364 if (cache_map_n == cache_map_size) { 365 WARN(1, "MTRR cache mode memory map exhausted!\n"); 366 cache_map_n = cache_map_fixed; 367 return 0; 368 } 369 370 if (cache_map_n > idx) { 371 memmove(cache_map + idx + 1, cache_map + idx, 372 sizeof(*cache_map) * (cache_map_n - idx)); 373 } 374 375 cache_map[idx].start = start; 376 cache_map[idx].end = end; 377 cache_map[idx].type = type; 378 cache_map[idx].fixed = 0; 379 cache_map_n++; 380 381 return 0; 382 } 383 384 /* Clear a part of an entry. Return 1 if start of entry is still valid. */ 385 static int clr_map_range_at(u64 start, u64 end, int idx) 386 { 387 int ret = start != cache_map[idx].start; 388 u64 tmp; 389 390 if (start == cache_map[idx].start && end == cache_map[idx].end) { 391 rm_map_entry_at(idx); 392 } else if (start == cache_map[idx].start) { 393 cache_map[idx].start = end; 394 } else if (end == cache_map[idx].end) { 395 cache_map[idx].end = start; 396 } else { 397 tmp = cache_map[idx].end; 398 cache_map[idx].end = start; 399 add_map_entry_at(end, tmp, cache_map[idx].type, idx + 1); 400 } 401 402 return ret; 403 } 404 405 /* 406 * Add MTRR to the map. The current map is scanned and each part of the MTRR 407 * either overlapping with an existing entry or with a hole in the map is 408 * handled separately. 409 */ 410 static void add_map_entry(u64 start, u64 end, u8 type) 411 { 412 u8 new_type, old_type; 413 u64 tmp; 414 int i; 415 416 for (i = 0; i < cache_map_n && start < end; i++) { 417 if (start >= cache_map[i].end) 418 continue; 419 420 if (start < cache_map[i].start) { 421 /* Region start has no overlap. */ 422 tmp = min(end, cache_map[i].start); 423 i -= add_map_entry_at(start, tmp, type, i); 424 start = tmp; 425 continue; 426 } 427 428 new_type = get_effective_type(type, cache_map[i].type); 429 old_type = cache_map[i].type; 430 431 if (cache_map[i].fixed || new_type == old_type) { 432 /* Cut off start of new entry. */ 433 start = cache_map[i].end; 434 continue; 435 } 436 437 /* Handle only overlapping part of region. */ 438 tmp = min(end, cache_map[i].end); 439 i += clr_map_range_at(start, tmp, i); 440 i -= add_map_entry_at(start, tmp, new_type, i); 441 start = tmp; 442 } 443 444 /* Add rest of region after last map entry (rest might be empty). */ 445 add_map_entry_at(start, end, type, i); 446 } 447 448 /* Add variable MTRRs to cache map. */ 449 static void map_add_var(void) 450 { 451 u64 start, size; 452 unsigned int i; 453 u8 type; 454 455 /* 456 * Add AMD TOP_MEM2 area. Can't be added in mtrr_build_map(), as it 457 * needs to be added again when rebuilding the map due to potentially 458 * having moved as a result of variable MTRRs for memory below 4GB. 459 */ 460 if (mtrr_tom2) { 461 add_map_entry(BIT_ULL(32), mtrr_tom2, MTRR_TYPE_WRBACK); 462 cache_map[cache_map_n - 1].fixed = 1; 463 } 464 465 for (i = 0; i < num_var_ranges; i++) { 466 type = get_var_mtrr_state(i, &start, &size); 467 if (type != MTRR_TYPE_INVALID) 468 add_map_entry(start, start + size, type); 469 } 470 } 471 472 /* 473 * Rebuild map by replacing variable entries. Needs to be called when MTRR 474 * registers are being changed after boot, as such changes could include 475 * removals of registers, which are complicated to handle without rebuild of 476 * the map. 477 */ 478 void generic_rebuild_map(void) 479 { 480 if (mtrr_if != &generic_mtrr_ops) 481 return; 482 483 cache_map_n = cache_map_fixed; 484 485 map_add_var(); 486 } 487 488 static unsigned int __init get_cache_map_size(void) 489 { 490 return cache_map_fixed + 2 * num_var_ranges + (mtrr_tom2 != 0); 491 } 492 493 /* Build the cache_map containing the cache modes per memory range. */ 494 void __init mtrr_build_map(void) 495 { 496 u64 start, end, size; 497 unsigned int i; 498 u8 type; 499 500 /* Add fixed MTRRs, optimize for adjacent entries with same type. */ 501 if (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED) { 502 /* 503 * Start with 64k size fixed entries, preset 1st one (hence the 504 * loop below is starting with index 1). 505 */ 506 start = 0; 507 end = size = 0x10000; 508 type = mtrr_state.fixed_ranges[0]; 509 510 for (i = 1; i < MTRR_NUM_FIXED_RANGES; i++) { 511 /* 8 64k entries, then 16 16k ones, rest 4k. */ 512 if (i == 8 || i == 24) 513 size >>= 2; 514 515 if (mtrr_state.fixed_ranges[i] != type) { 516 add_map_entry(start, end, type); 517 start = end; 518 type = mtrr_state.fixed_ranges[i]; 519 } 520 end += size; 521 } 522 add_map_entry(start, end, type); 523 } 524 525 /* Mark fixed, they take precedence. */ 526 for (i = 0; i < cache_map_n; i++) 527 cache_map[i].fixed = 1; 528 cache_map_fixed = cache_map_n; 529 530 map_add_var(); 531 532 pr_info("MTRR map: %u entries (%u fixed + %u variable; max %u), built from %u variable MTRRs\n", 533 cache_map_n, cache_map_fixed, cache_map_n - cache_map_fixed, 534 get_cache_map_size(), num_var_ranges + (mtrr_tom2 != 0)); 535 536 if (mtrr_debug) { 537 for (i = 0; i < cache_map_n; i++) { 538 pr_info("%3u: %016llx-%016llx %s\n", i, 539 cache_map[i].start, cache_map[i].end - 1, 540 mtrr_attrib_to_str(cache_map[i].type)); 541 } 542 } 543 } 544 545 /* Copy the cache_map from __initdata memory to dynamically allocated one. */ 546 void __init mtrr_copy_map(void) 547 { 548 unsigned int new_size = get_cache_map_size(); 549 550 if (!mtrr_state.enabled || !new_size) { 551 cache_map = NULL; 552 return; 553 } 554 555 mutex_lock(&mtrr_mutex); 556 557 cache_map = kcalloc(new_size, sizeof(*cache_map), GFP_KERNEL); 558 if (cache_map) { 559 memmove(cache_map, init_cache_map, 560 cache_map_n * sizeof(*cache_map)); 561 cache_map_size = new_size; 562 } else { 563 mtrr_state.enabled = 0; 564 pr_err("MTRRs disabled due to allocation failure for lookup map.\n"); 565 } 566 567 mutex_unlock(&mtrr_mutex); 568 } 569 570 /** 571 * mtrr_overwrite_state - set static MTRR state 572 * 573 * Used to set MTRR state via different means (e.g. with data obtained from 574 * a hypervisor). 575 * Is allowed only for special cases when running virtualized. Must be called 576 * from the x86_init.hyper.init_platform() hook. It can be called only once. 577 * The MTRR state can't be changed afterwards. To ensure that, X86_FEATURE_MTRR 578 * is cleared. 579 */ 580 void mtrr_overwrite_state(struct mtrr_var_range *var, unsigned int num_var, 581 mtrr_type def_type) 582 { 583 unsigned int i; 584 585 /* Only allowed to be called once before mtrr_bp_init(). */ 586 if (WARN_ON_ONCE(mtrr_state_set)) 587 return; 588 589 /* Only allowed when running virtualized. */ 590 if (!cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) 591 return; 592 593 /* 594 * Only allowed for special virtualization cases: 595 * - when running as Hyper-V, SEV-SNP guest using vTOM 596 * - when running as Xen PV guest 597 * - when running as SEV-SNP or TDX guest to avoid unnecessary 598 * VMM communication/Virtualization exceptions (#VC, #VE) 599 */ 600 if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP) && 601 !hv_is_isolation_supported() && 602 !cpu_feature_enabled(X86_FEATURE_XENPV) && 603 !cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) 604 return; 605 606 /* Disable MTRR in order to disable MTRR modifications. */ 607 setup_clear_cpu_cap(X86_FEATURE_MTRR); 608 609 if (var) { 610 if (num_var > MTRR_MAX_VAR_RANGES) { 611 pr_warn("Trying to overwrite MTRR state with %u variable entries\n", 612 num_var); 613 num_var = MTRR_MAX_VAR_RANGES; 614 } 615 for (i = 0; i < num_var; i++) 616 mtrr_state.var_ranges[i] = var[i]; 617 num_var_ranges = num_var; 618 } 619 620 mtrr_state.def_type = def_type; 621 mtrr_state.enabled |= MTRR_STATE_MTRR_ENABLED; 622 623 mtrr_state_set = 1; 624 } 625 626 /** 627 * mtrr_type_lookup - look up memory type in MTRR 628 * 629 * Return Values: 630 * MTRR_TYPE_(type) - The effective MTRR type for the region 631 * MTRR_TYPE_INVALID - MTRR is disabled 632 * 633 * Output Argument: 634 * uniform - Set to 1 when an MTRR covers the region uniformly, i.e. the 635 * region is fully covered by a single MTRR entry or the default 636 * type. 637 */ 638 u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform) 639 { 640 u8 type, prev_type, is_uniform = 1, dummy; 641 int repeat; 642 u64 partial_end; 643 644 /* Make end inclusive instead of exclusive */ 645 end--; 646 647 if (!mtrr_state_set) 648 return MTRR_TYPE_INVALID; 649 650 if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED)) 651 return MTRR_TYPE_INVALID; 652 653 /* 654 * Look up the fixed ranges first, which take priority over 655 * the variable ranges. 656 */ 657 if ((start < 0x100000) && 658 (mtrr_state.have_fixed) && 659 (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) { 660 is_uniform = 0; 661 type = mtrr_type_lookup_fixed(start, end); 662 goto out; 663 } 664 665 /* 666 * Look up the variable ranges. Look of multiple ranges matching 667 * this address and pick type as per MTRR precedence. 668 */ 669 type = mtrr_type_lookup_variable(start, end, &partial_end, 670 &repeat, &is_uniform); 671 672 /* 673 * Common path is with repeat = 0. 674 * However, we can have cases where [start:end] spans across some 675 * MTRR ranges and/or the default type. Do repeated lookups for 676 * that case here. 677 */ 678 while (repeat) { 679 prev_type = type; 680 start = partial_end; 681 is_uniform = 0; 682 type = mtrr_type_lookup_variable(start, end, &partial_end, 683 &repeat, &dummy); 684 685 if (check_type_overlap(&prev_type, &type)) 686 goto out; 687 } 688 689 if (mtrr_tom2 && (start >= (1ULL<<32)) && (end < mtrr_tom2)) 690 type = MTRR_TYPE_WRBACK; 691 692 out: 693 *uniform = is_uniform; 694 return type; 695 } 696 697 /* Get the MSR pair relating to a var range */ 698 static void 699 get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr) 700 { 701 rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); 702 rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); 703 } 704 705 /* Fill the MSR pair relating to a var range */ 706 void fill_mtrr_var_range(unsigned int index, 707 u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi) 708 { 709 struct mtrr_var_range *vr; 710 711 vr = mtrr_state.var_ranges; 712 713 vr[index].base_lo = base_lo; 714 vr[index].base_hi = base_hi; 715 vr[index].mask_lo = mask_lo; 716 vr[index].mask_hi = mask_hi; 717 } 718 719 static void get_fixed_ranges(mtrr_type *frs) 720 { 721 unsigned int *p = (unsigned int *)frs; 722 int i; 723 724 k8_check_syscfg_dram_mod_en(); 725 726 rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]); 727 728 for (i = 0; i < 2; i++) 729 rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]); 730 for (i = 0; i < 8; i++) 731 rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]); 732 } 733 734 void mtrr_save_fixed_ranges(void *info) 735 { 736 if (boot_cpu_has(X86_FEATURE_MTRR)) 737 get_fixed_ranges(mtrr_state.fixed_ranges); 738 } 739 740 static unsigned __initdata last_fixed_start; 741 static unsigned __initdata last_fixed_end; 742 static mtrr_type __initdata last_fixed_type; 743 744 static void __init print_fixed_last(void) 745 { 746 if (!last_fixed_end) 747 return; 748 749 pr_info(" %05X-%05X %s\n", last_fixed_start, 750 last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type)); 751 752 last_fixed_end = 0; 753 } 754 755 static void __init update_fixed_last(unsigned base, unsigned end, 756 mtrr_type type) 757 { 758 last_fixed_start = base; 759 last_fixed_end = end; 760 last_fixed_type = type; 761 } 762 763 static void __init 764 print_fixed(unsigned base, unsigned step, const mtrr_type *types) 765 { 766 unsigned i; 767 768 for (i = 0; i < 8; ++i, ++types, base += step) { 769 if (last_fixed_end == 0) { 770 update_fixed_last(base, base + step, *types); 771 continue; 772 } 773 if (last_fixed_end == base && last_fixed_type == *types) { 774 last_fixed_end = base + step; 775 continue; 776 } 777 /* new segments: gap or different type */ 778 print_fixed_last(); 779 update_fixed_last(base, base + step, *types); 780 } 781 } 782 783 static void __init print_mtrr_state(void) 784 { 785 unsigned int i; 786 int high_width; 787 788 pr_info("MTRR default type: %s\n", 789 mtrr_attrib_to_str(mtrr_state.def_type)); 790 if (mtrr_state.have_fixed) { 791 pr_info("MTRR fixed ranges %sabled:\n", 792 ((mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED) && 793 (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) ? 794 "en" : "dis"); 795 print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0); 796 for (i = 0; i < 2; ++i) 797 print_fixed(0x80000 + i * 0x20000, 0x04000, 798 mtrr_state.fixed_ranges + (i + 1) * 8); 799 for (i = 0; i < 8; ++i) 800 print_fixed(0xC0000 + i * 0x08000, 0x01000, 801 mtrr_state.fixed_ranges + (i + 3) * 8); 802 803 /* tail */ 804 print_fixed_last(); 805 } 806 pr_info("MTRR variable ranges %sabled:\n", 807 mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED ? "en" : "dis"); 808 high_width = (boot_cpu_data.x86_phys_bits - (32 - PAGE_SHIFT) + 3) / 4; 809 810 for (i = 0; i < num_var_ranges; ++i) { 811 if (mtrr_state.var_ranges[i].mask_lo & MTRR_PHYSMASK_V) 812 pr_info(" %u base %0*X%05X000 mask %0*X%05X000 %s\n", 813 i, 814 high_width, 815 mtrr_state.var_ranges[i].base_hi, 816 mtrr_state.var_ranges[i].base_lo >> 12, 817 high_width, 818 mtrr_state.var_ranges[i].mask_hi, 819 mtrr_state.var_ranges[i].mask_lo >> 12, 820 mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 821 MTRR_PHYSBASE_TYPE)); 822 else 823 pr_info(" %u disabled\n", i); 824 } 825 if (mtrr_tom2) 826 pr_info("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20); 827 } 828 829 /* Grab all of the MTRR state for this CPU into *state */ 830 bool __init get_mtrr_state(void) 831 { 832 struct mtrr_var_range *vrs; 833 unsigned lo, dummy; 834 unsigned int i; 835 836 vrs = mtrr_state.var_ranges; 837 838 rdmsr(MSR_MTRRcap, lo, dummy); 839 mtrr_state.have_fixed = lo & MTRR_CAP_FIX; 840 841 for (i = 0; i < num_var_ranges; i++) 842 get_mtrr_var_range(i, &vrs[i]); 843 if (mtrr_state.have_fixed) 844 get_fixed_ranges(mtrr_state.fixed_ranges); 845 846 rdmsr(MSR_MTRRdefType, lo, dummy); 847 mtrr_state.def_type = lo & MTRR_DEF_TYPE_TYPE; 848 mtrr_state.enabled = (lo & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT; 849 850 if (amd_special_default_mtrr()) { 851 unsigned low, high; 852 853 /* TOP_MEM2 */ 854 rdmsr(MSR_K8_TOP_MEM2, low, high); 855 mtrr_tom2 = high; 856 mtrr_tom2 <<= 32; 857 mtrr_tom2 |= low; 858 mtrr_tom2 &= 0xffffff800000ULL; 859 } 860 861 if (mtrr_debug) 862 print_mtrr_state(); 863 864 mtrr_state_set = 1; 865 866 return !!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED); 867 } 868 869 /* Some BIOS's are messed up and don't set all MTRRs the same! */ 870 void __init mtrr_state_warn(void) 871 { 872 unsigned long mask = smp_changes_mask; 873 874 if (!mask) 875 return; 876 if (mask & MTRR_CHANGE_MASK_FIXED) 877 pr_warn("mtrr: your CPUs had inconsistent fixed MTRR settings\n"); 878 if (mask & MTRR_CHANGE_MASK_VARIABLE) 879 pr_warn("mtrr: your CPUs had inconsistent variable MTRR settings\n"); 880 if (mask & MTRR_CHANGE_MASK_DEFTYPE) 881 pr_warn("mtrr: your CPUs had inconsistent MTRRdefType settings\n"); 882 883 pr_info("mtrr: probably your BIOS does not setup all CPUs.\n"); 884 pr_info("mtrr: corrected configuration.\n"); 885 } 886 887 /* 888 * Doesn't attempt to pass an error out to MTRR users 889 * because it's quite complicated in some cases and probably not 890 * worth it because the best error handling is to ignore it. 891 */ 892 void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b) 893 { 894 if (wrmsr_safe(msr, a, b) < 0) { 895 pr_err("MTRR: CPU %u: Writing MSR %x to %x:%x failed\n", 896 smp_processor_id(), msr, a, b); 897 } 898 } 899 900 /** 901 * set_fixed_range - checks & updates a fixed-range MTRR if it 902 * differs from the value it should have 903 * @msr: MSR address of the MTTR which should be checked and updated 904 * @changed: pointer which indicates whether the MTRR needed to be changed 905 * @msrwords: pointer to the MSR values which the MSR should have 906 */ 907 static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords) 908 { 909 unsigned lo, hi; 910 911 rdmsr(msr, lo, hi); 912 913 if (lo != msrwords[0] || hi != msrwords[1]) { 914 mtrr_wrmsr(msr, msrwords[0], msrwords[1]); 915 *changed = true; 916 } 917 } 918 919 /** 920 * generic_get_free_region - Get a free MTRR. 921 * @base: The starting (base) address of the region. 922 * @size: The size (in bytes) of the region. 923 * @replace_reg: mtrr index to be replaced; set to invalid value if none. 924 * 925 * Returns: The index of the region on success, else negative on error. 926 */ 927 int 928 generic_get_free_region(unsigned long base, unsigned long size, int replace_reg) 929 { 930 unsigned long lbase, lsize; 931 mtrr_type ltype; 932 int i, max; 933 934 max = num_var_ranges; 935 if (replace_reg >= 0 && replace_reg < max) 936 return replace_reg; 937 938 for (i = 0; i < max; ++i) { 939 mtrr_if->get(i, &lbase, &lsize, <ype); 940 if (lsize == 0) 941 return i; 942 } 943 944 return -ENOSPC; 945 } 946 947 static void generic_get_mtrr(unsigned int reg, unsigned long *base, 948 unsigned long *size, mtrr_type *type) 949 { 950 u32 mask_lo, mask_hi, base_lo, base_hi; 951 unsigned int hi; 952 u64 tmp, mask; 953 954 /* 955 * get_mtrr doesn't need to update mtrr_state, also it could be called 956 * from any cpu, so try to print it out directly. 957 */ 958 get_cpu(); 959 960 rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); 961 962 if (!(mask_lo & MTRR_PHYSMASK_V)) { 963 /* Invalid (i.e. free) range */ 964 *base = 0; 965 *size = 0; 966 *type = 0; 967 goto out_put_cpu; 968 } 969 970 rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi); 971 972 /* Work out the shifted address mask: */ 973 tmp = (u64)mask_hi << 32 | (mask_lo & PAGE_MASK); 974 mask = (u64)phys_hi_rsvd << 32 | tmp; 975 976 /* Expand tmp with high bits to all 1s: */ 977 hi = fls64(tmp); 978 if (hi > 0) { 979 tmp |= ~((1ULL<<(hi - 1)) - 1); 980 981 if (tmp != mask) { 982 pr_warn("mtrr: your BIOS has configured an incorrect mask, fixing it.\n"); 983 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); 984 mask = tmp; 985 } 986 } 987 988 /* 989 * This works correctly if size is a power of two, i.e. a 990 * contiguous range: 991 */ 992 *size = -mask >> PAGE_SHIFT; 993 *base = (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT; 994 *type = base_lo & MTRR_PHYSBASE_TYPE; 995 996 out_put_cpu: 997 put_cpu(); 998 } 999 1000 /** 1001 * set_fixed_ranges - checks & updates the fixed-range MTRRs if they 1002 * differ from the saved set 1003 * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges() 1004 */ 1005 static int set_fixed_ranges(mtrr_type *frs) 1006 { 1007 unsigned long long *saved = (unsigned long long *)frs; 1008 bool changed = false; 1009 int block = -1, range; 1010 1011 k8_check_syscfg_dram_mod_en(); 1012 1013 while (fixed_range_blocks[++block].ranges) { 1014 for (range = 0; range < fixed_range_blocks[block].ranges; range++) 1015 set_fixed_range(fixed_range_blocks[block].base_msr + range, 1016 &changed, (unsigned int *)saved++); 1017 } 1018 1019 return changed; 1020 } 1021 1022 /* 1023 * Set the MSR pair relating to a var range. 1024 * Returns true if changes are made. 1025 */ 1026 static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr) 1027 { 1028 unsigned int lo, hi; 1029 bool changed = false; 1030 1031 rdmsr(MTRRphysBase_MSR(index), lo, hi); 1032 if ((vr->base_lo & ~MTRR_PHYSBASE_RSVD) != (lo & ~MTRR_PHYSBASE_RSVD) 1033 || (vr->base_hi & ~phys_hi_rsvd) != (hi & ~phys_hi_rsvd)) { 1034 1035 mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); 1036 changed = true; 1037 } 1038 1039 rdmsr(MTRRphysMask_MSR(index), lo, hi); 1040 1041 if ((vr->mask_lo & ~MTRR_PHYSMASK_RSVD) != (lo & ~MTRR_PHYSMASK_RSVD) 1042 || (vr->mask_hi & ~phys_hi_rsvd) != (hi & ~phys_hi_rsvd)) { 1043 mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); 1044 changed = true; 1045 } 1046 return changed; 1047 } 1048 1049 static u32 deftype_lo, deftype_hi; 1050 1051 /** 1052 * set_mtrr_state - Set the MTRR state for this CPU. 1053 * 1054 * NOTE: The CPU must already be in a safe state for MTRR changes, including 1055 * measures that only a single CPU can be active in set_mtrr_state() in 1056 * order to not be subject to races for usage of deftype_lo. This is 1057 * accomplished by taking cache_disable_lock. 1058 * RETURNS: 0 if no changes made, else a mask indicating what was changed. 1059 */ 1060 static unsigned long set_mtrr_state(void) 1061 { 1062 unsigned long change_mask = 0; 1063 unsigned int i; 1064 1065 for (i = 0; i < num_var_ranges; i++) { 1066 if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i])) 1067 change_mask |= MTRR_CHANGE_MASK_VARIABLE; 1068 } 1069 1070 if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges)) 1071 change_mask |= MTRR_CHANGE_MASK_FIXED; 1072 1073 /* 1074 * Set_mtrr_restore restores the old value of MTRRdefType, 1075 * so to set it we fiddle with the saved value: 1076 */ 1077 if ((deftype_lo & MTRR_DEF_TYPE_TYPE) != mtrr_state.def_type || 1078 ((deftype_lo & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT) != mtrr_state.enabled) { 1079 1080 deftype_lo = (deftype_lo & MTRR_DEF_TYPE_DISABLE) | 1081 mtrr_state.def_type | 1082 (mtrr_state.enabled << MTRR_STATE_SHIFT); 1083 change_mask |= MTRR_CHANGE_MASK_DEFTYPE; 1084 } 1085 1086 return change_mask; 1087 } 1088 1089 void mtrr_disable(void) 1090 { 1091 /* Save MTRR state */ 1092 rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); 1093 1094 /* Disable MTRRs, and set the default type to uncached */ 1095 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & MTRR_DEF_TYPE_DISABLE, deftype_hi); 1096 } 1097 1098 void mtrr_enable(void) 1099 { 1100 /* Intel (P6) standard MTRRs */ 1101 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); 1102 } 1103 1104 void mtrr_generic_set_state(void) 1105 { 1106 unsigned long mask, count; 1107 1108 /* Actually set the state */ 1109 mask = set_mtrr_state(); 1110 1111 /* Use the atomic bitops to update the global mask */ 1112 for (count = 0; count < sizeof(mask) * 8; ++count) { 1113 if (mask & 0x01) 1114 set_bit(count, &smp_changes_mask); 1115 mask >>= 1; 1116 } 1117 } 1118 1119 /** 1120 * generic_set_mtrr - set variable MTRR register on the local CPU. 1121 * 1122 * @reg: The register to set. 1123 * @base: The base address of the region. 1124 * @size: The size of the region. If this is 0 the region is disabled. 1125 * @type: The type of the region. 1126 * 1127 * Returns nothing. 1128 */ 1129 static void generic_set_mtrr(unsigned int reg, unsigned long base, 1130 unsigned long size, mtrr_type type) 1131 { 1132 unsigned long flags; 1133 struct mtrr_var_range *vr; 1134 1135 vr = &mtrr_state.var_ranges[reg]; 1136 1137 local_irq_save(flags); 1138 cache_disable(); 1139 1140 if (size == 0) { 1141 /* 1142 * The invalid bit is kept in the mask, so we simply 1143 * clear the relevant mask register to disable a range. 1144 */ 1145 mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0); 1146 memset(vr, 0, sizeof(struct mtrr_var_range)); 1147 } else { 1148 vr->base_lo = base << PAGE_SHIFT | type; 1149 vr->base_hi = (base >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; 1150 vr->mask_lo = -size << PAGE_SHIFT | MTRR_PHYSMASK_V; 1151 vr->mask_hi = (-size >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; 1152 1153 mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi); 1154 mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi); 1155 } 1156 1157 cache_enable(); 1158 local_irq_restore(flags); 1159 } 1160 1161 int generic_validate_add_page(unsigned long base, unsigned long size, 1162 unsigned int type) 1163 { 1164 unsigned long lbase, last; 1165 1166 /* 1167 * For Intel PPro stepping <= 7 1168 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF 1169 */ 1170 if (mtrr_if == &generic_mtrr_ops && boot_cpu_data.x86 == 6 && 1171 boot_cpu_data.x86_model == 1 && 1172 boot_cpu_data.x86_stepping <= 7) { 1173 if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) { 1174 pr_warn("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base); 1175 return -EINVAL; 1176 } 1177 if (!(base + size < 0x70000 || base > 0x7003F) && 1178 (type == MTRR_TYPE_WRCOMB 1179 || type == MTRR_TYPE_WRBACK)) { 1180 pr_warn("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n"); 1181 return -EINVAL; 1182 } 1183 } 1184 1185 /* 1186 * Check upper bits of base and last are equal and lower bits are 0 1187 * for base and 1 for last 1188 */ 1189 last = base + size - 1; 1190 for (lbase = base; !(lbase & 1) && (last & 1); 1191 lbase = lbase >> 1, last = last >> 1) 1192 ; 1193 if (lbase != last) { 1194 pr_warn("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size); 1195 return -EINVAL; 1196 } 1197 return 0; 1198 } 1199 1200 static int generic_have_wrcomb(void) 1201 { 1202 unsigned long config, dummy; 1203 rdmsr(MSR_MTRRcap, config, dummy); 1204 return config & MTRR_CAP_WC; 1205 } 1206 1207 int positive_have_wrcomb(void) 1208 { 1209 return 1; 1210 } 1211 1212 /* 1213 * Generic structure... 1214 */ 1215 const struct mtrr_ops generic_mtrr_ops = { 1216 .get = generic_get_mtrr, 1217 .get_free_region = generic_get_free_region, 1218 .set = generic_set_mtrr, 1219 .validate_add_page = generic_validate_add_page, 1220 .have_wrcomb = generic_have_wrcomb, 1221 }; 1222