1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/export.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/ctype.h> 9 #include <linux/delay.h> 10 #include <linux/sched/mm.h> 11 #include <linux/sched/clock.h> 12 #include <linux/sched/task.h> 13 #include <linux/init.h> 14 #include <linux/kprobes.h> 15 #include <linux/kgdb.h> 16 #include <linux/smp.h> 17 #include <linux/io.h> 18 #include <linux/syscore_ops.h> 19 20 #include <asm/stackprotector.h> 21 #include <asm/perf_event.h> 22 #include <asm/mmu_context.h> 23 #include <asm/archrandom.h> 24 #include <asm/hypervisor.h> 25 #include <asm/processor.h> 26 #include <asm/tlbflush.h> 27 #include <asm/debugreg.h> 28 #include <asm/sections.h> 29 #include <asm/vsyscall.h> 30 #include <linux/topology.h> 31 #include <linux/cpumask.h> 32 #include <asm/pgtable.h> 33 #include <linux/atomic.h> 34 #include <asm/proto.h> 35 #include <asm/setup.h> 36 #include <asm/apic.h> 37 #include <asm/desc.h> 38 #include <asm/fpu/internal.h> 39 #include <asm/mtrr.h> 40 #include <asm/hwcap2.h> 41 #include <linux/numa.h> 42 #include <asm/asm.h> 43 #include <asm/bugs.h> 44 #include <asm/cpu.h> 45 #include <asm/mce.h> 46 #include <asm/msr.h> 47 #include <asm/pat.h> 48 #include <asm/microcode.h> 49 #include <asm/microcode_intel.h> 50 51 #ifdef CONFIG_X86_LOCAL_APIC 52 #include <asm/uv/uv.h> 53 #endif 54 55 #include "cpu.h" 56 57 u32 elf_hwcap2 __read_mostly; 58 59 /* all of these masks are initialized in setup_cpu_local_masks() */ 60 cpumask_var_t cpu_initialized_mask; 61 cpumask_var_t cpu_callout_mask; 62 cpumask_var_t cpu_callin_mask; 63 64 /* representing cpus for which sibling maps can be computed */ 65 cpumask_var_t cpu_sibling_setup_mask; 66 67 /* correctly size the local cpu masks */ 68 void __init setup_cpu_local_masks(void) 69 { 70 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 71 alloc_bootmem_cpumask_var(&cpu_callin_mask); 72 alloc_bootmem_cpumask_var(&cpu_callout_mask); 73 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 74 } 75 76 static void default_init(struct cpuinfo_x86 *c) 77 { 78 #ifdef CONFIG_X86_64 79 cpu_detect_cache_sizes(c); 80 #else 81 /* Not much we can do here... */ 82 /* Check if at least it has cpuid */ 83 if (c->cpuid_level == -1) { 84 /* No cpuid. It must be an ancient CPU */ 85 if (c->x86 == 4) 86 strcpy(c->x86_model_id, "486"); 87 else if (c->x86 == 3) 88 strcpy(c->x86_model_id, "386"); 89 } 90 #endif 91 } 92 93 static const struct cpu_dev default_cpu = { 94 .c_init = default_init, 95 .c_vendor = "Unknown", 96 .c_x86_vendor = X86_VENDOR_UNKNOWN, 97 }; 98 99 static const struct cpu_dev *this_cpu = &default_cpu; 100 101 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 102 #ifdef CONFIG_X86_64 103 /* 104 * We need valid kernel segments for data and code in long mode too 105 * IRET will check the segment types kkeil 2000/10/28 106 * Also sysret mandates a special GDT layout 107 * 108 * TLS descriptors are currently at a different place compared to i386. 109 * Hopefully nobody expects them at a fixed place (Wine?) 110 */ 111 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 112 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 113 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 114 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 115 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 116 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 117 #else 118 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 119 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 120 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 121 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 122 /* 123 * Segments used for calling PnP BIOS have byte granularity. 124 * They code segments and data segments have fixed 64k limits, 125 * the transfer segment sizes are set at run time. 126 */ 127 /* 32-bit code */ 128 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 129 /* 16-bit code */ 130 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 131 /* 16-bit data */ 132 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 133 /* 16-bit data */ 134 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 135 /* 16-bit data */ 136 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 137 /* 138 * The APM segments have byte granularity and their bases 139 * are set at run time. All have 64k limits. 140 */ 141 /* 32-bit code */ 142 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 143 /* 16-bit code */ 144 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 145 /* data */ 146 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 147 148 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 149 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 150 GDT_STACK_CANARY_INIT 151 #endif 152 } }; 153 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 154 155 static int __init x86_mpx_setup(char *s) 156 { 157 /* require an exact match without trailing characters */ 158 if (strlen(s)) 159 return 0; 160 161 /* do not emit a message if the feature is not present */ 162 if (!boot_cpu_has(X86_FEATURE_MPX)) 163 return 1; 164 165 setup_clear_cpu_cap(X86_FEATURE_MPX); 166 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 167 return 1; 168 } 169 __setup("nompx", x86_mpx_setup); 170 171 #ifdef CONFIG_X86_64 172 static int __init x86_nopcid_setup(char *s) 173 { 174 /* nopcid doesn't accept parameters */ 175 if (s) 176 return -EINVAL; 177 178 /* do not emit a message if the feature is not present */ 179 if (!boot_cpu_has(X86_FEATURE_PCID)) 180 return 0; 181 182 setup_clear_cpu_cap(X86_FEATURE_PCID); 183 pr_info("nopcid: PCID feature disabled\n"); 184 return 0; 185 } 186 early_param("nopcid", x86_nopcid_setup); 187 #endif 188 189 static int __init x86_noinvpcid_setup(char *s) 190 { 191 /* noinvpcid doesn't accept parameters */ 192 if (s) 193 return -EINVAL; 194 195 /* do not emit a message if the feature is not present */ 196 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 197 return 0; 198 199 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 200 pr_info("noinvpcid: INVPCID feature disabled\n"); 201 return 0; 202 } 203 early_param("noinvpcid", x86_noinvpcid_setup); 204 205 #ifdef CONFIG_X86_32 206 static int cachesize_override = -1; 207 static int disable_x86_serial_nr = 1; 208 209 static int __init cachesize_setup(char *str) 210 { 211 get_option(&str, &cachesize_override); 212 return 1; 213 } 214 __setup("cachesize=", cachesize_setup); 215 216 static int __init x86_sep_setup(char *s) 217 { 218 setup_clear_cpu_cap(X86_FEATURE_SEP); 219 return 1; 220 } 221 __setup("nosep", x86_sep_setup); 222 223 /* Standard macro to see if a specific flag is changeable */ 224 static inline int flag_is_changeable_p(u32 flag) 225 { 226 u32 f1, f2; 227 228 /* 229 * Cyrix and IDT cpus allow disabling of CPUID 230 * so the code below may return different results 231 * when it is executed before and after enabling 232 * the CPUID. Add "volatile" to not allow gcc to 233 * optimize the subsequent calls to this function. 234 */ 235 asm volatile ("pushfl \n\t" 236 "pushfl \n\t" 237 "popl %0 \n\t" 238 "movl %0, %1 \n\t" 239 "xorl %2, %0 \n\t" 240 "pushl %0 \n\t" 241 "popfl \n\t" 242 "pushfl \n\t" 243 "popl %0 \n\t" 244 "popfl \n\t" 245 246 : "=&r" (f1), "=&r" (f2) 247 : "ir" (flag)); 248 249 return ((f1^f2) & flag) != 0; 250 } 251 252 /* Probe for the CPUID instruction */ 253 int have_cpuid_p(void) 254 { 255 return flag_is_changeable_p(X86_EFLAGS_ID); 256 } 257 258 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 259 { 260 unsigned long lo, hi; 261 262 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 263 return; 264 265 /* Disable processor serial number: */ 266 267 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 268 lo |= 0x200000; 269 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 270 271 pr_notice("CPU serial number disabled.\n"); 272 clear_cpu_cap(c, X86_FEATURE_PN); 273 274 /* Disabling the serial number may affect the cpuid level */ 275 c->cpuid_level = cpuid_eax(0); 276 } 277 278 static int __init x86_serial_nr_setup(char *s) 279 { 280 disable_x86_serial_nr = 0; 281 return 1; 282 } 283 __setup("serialnumber", x86_serial_nr_setup); 284 #else 285 static inline int flag_is_changeable_p(u32 flag) 286 { 287 return 1; 288 } 289 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 290 { 291 } 292 #endif 293 294 static __init int setup_disable_smep(char *arg) 295 { 296 setup_clear_cpu_cap(X86_FEATURE_SMEP); 297 /* Check for things that depend on SMEP being enabled: */ 298 check_mpx_erratum(&boot_cpu_data); 299 return 1; 300 } 301 __setup("nosmep", setup_disable_smep); 302 303 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 304 { 305 if (cpu_has(c, X86_FEATURE_SMEP)) 306 cr4_set_bits(X86_CR4_SMEP); 307 } 308 309 static __init int setup_disable_smap(char *arg) 310 { 311 setup_clear_cpu_cap(X86_FEATURE_SMAP); 312 return 1; 313 } 314 __setup("nosmap", setup_disable_smap); 315 316 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 317 { 318 unsigned long eflags = native_save_fl(); 319 320 /* This should have been cleared long ago */ 321 BUG_ON(eflags & X86_EFLAGS_AC); 322 323 if (cpu_has(c, X86_FEATURE_SMAP)) { 324 #ifdef CONFIG_X86_SMAP 325 cr4_set_bits(X86_CR4_SMAP); 326 #else 327 cr4_clear_bits(X86_CR4_SMAP); 328 #endif 329 } 330 } 331 332 /* 333 * Protection Keys are not available in 32-bit mode. 334 */ 335 static bool pku_disabled; 336 337 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 338 { 339 /* check the boot processor, plus compile options for PKU: */ 340 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 341 return; 342 /* checks the actual processor's cpuid bits: */ 343 if (!cpu_has(c, X86_FEATURE_PKU)) 344 return; 345 if (pku_disabled) 346 return; 347 348 cr4_set_bits(X86_CR4_PKE); 349 /* 350 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 351 * cpuid bit to be set. We need to ensure that we 352 * update that bit in this CPU's "cpu_info". 353 */ 354 get_cpu_cap(c); 355 } 356 357 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 358 static __init int setup_disable_pku(char *arg) 359 { 360 /* 361 * Do not clear the X86_FEATURE_PKU bit. All of the 362 * runtime checks are against OSPKE so clearing the 363 * bit does nothing. 364 * 365 * This way, we will see "pku" in cpuinfo, but not 366 * "ospke", which is exactly what we want. It shows 367 * that the CPU has PKU, but the OS has not enabled it. 368 * This happens to be exactly how a system would look 369 * if we disabled the config option. 370 */ 371 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 372 pku_disabled = true; 373 return 1; 374 } 375 __setup("nopku", setup_disable_pku); 376 #endif /* CONFIG_X86_64 */ 377 378 /* 379 * Some CPU features depend on higher CPUID levels, which may not always 380 * be available due to CPUID level capping or broken virtualization 381 * software. Add those features to this table to auto-disable them. 382 */ 383 struct cpuid_dependent_feature { 384 u32 feature; 385 u32 level; 386 }; 387 388 static const struct cpuid_dependent_feature 389 cpuid_dependent_features[] = { 390 { X86_FEATURE_MWAIT, 0x00000005 }, 391 { X86_FEATURE_DCA, 0x00000009 }, 392 { X86_FEATURE_XSAVE, 0x0000000d }, 393 { 0, 0 } 394 }; 395 396 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 397 { 398 const struct cpuid_dependent_feature *df; 399 400 for (df = cpuid_dependent_features; df->feature; df++) { 401 402 if (!cpu_has(c, df->feature)) 403 continue; 404 /* 405 * Note: cpuid_level is set to -1 if unavailable, but 406 * extended_extended_level is set to 0 if unavailable 407 * and the legitimate extended levels are all negative 408 * when signed; hence the weird messing around with 409 * signs here... 410 */ 411 if (!((s32)df->level < 0 ? 412 (u32)df->level > (u32)c->extended_cpuid_level : 413 (s32)df->level > (s32)c->cpuid_level)) 414 continue; 415 416 clear_cpu_cap(c, df->feature); 417 if (!warn) 418 continue; 419 420 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 421 x86_cap_flag(df->feature), df->level); 422 } 423 } 424 425 /* 426 * Naming convention should be: <Name> [(<Codename>)] 427 * This table only is used unless init_<vendor>() below doesn't set it; 428 * in particular, if CPUID levels 0x80000002..4 are supported, this 429 * isn't used 430 */ 431 432 /* Look up CPU names by table lookup. */ 433 static const char *table_lookup_model(struct cpuinfo_x86 *c) 434 { 435 #ifdef CONFIG_X86_32 436 const struct legacy_cpu_model_info *info; 437 438 if (c->x86_model >= 16) 439 return NULL; /* Range check */ 440 441 if (!this_cpu) 442 return NULL; 443 444 info = this_cpu->legacy_models; 445 446 while (info->family) { 447 if (info->family == c->x86) 448 return info->model_names[c->x86_model]; 449 info++; 450 } 451 #endif 452 return NULL; /* Not found */ 453 } 454 455 __u32 cpu_caps_cleared[NCAPINTS]; 456 __u32 cpu_caps_set[NCAPINTS]; 457 458 void load_percpu_segment(int cpu) 459 { 460 #ifdef CONFIG_X86_32 461 loadsegment(fs, __KERNEL_PERCPU); 462 #else 463 __loadsegment_simple(gs, 0); 464 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 465 #endif 466 load_stack_canary_segment(); 467 } 468 469 static void set_percpu_fixmap_pages(int fixmap_index, void *ptr, 470 int pages, pgprot_t prot) 471 { 472 int i; 473 474 for (i = 0; i < pages; i++) { 475 __set_fixmap(fixmap_index - i, 476 per_cpu_ptr_to_phys(ptr + i * PAGE_SIZE), prot); 477 } 478 } 479 480 #ifdef CONFIG_X86_32 481 /* The 32-bit entry code needs to find cpu_entry_area. */ 482 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 483 #endif 484 485 /* Setup the fixmap mappings only once per-processor */ 486 static inline void setup_cpu_entry_area(int cpu) 487 { 488 #ifdef CONFIG_X86_64 489 /* On 64-bit systems, we use a read-only fixmap GDT. */ 490 pgprot_t gdt_prot = PAGE_KERNEL_RO; 491 #else 492 /* 493 * On native 32-bit systems, the GDT cannot be read-only because 494 * our double fault handler uses a task gate, and entering through 495 * a task gate needs to change an available TSS to busy. If the GDT 496 * is read-only, that will triple fault. 497 * 498 * On Xen PV, the GDT must be read-only because the hypervisor requires 499 * it. 500 */ 501 pgprot_t gdt_prot = boot_cpu_has(X86_FEATURE_XENPV) ? 502 PAGE_KERNEL_RO : PAGE_KERNEL; 503 #endif 504 505 __set_fixmap(get_cpu_entry_area_index(cpu, gdt), get_cpu_gdt_paddr(cpu), gdt_prot); 506 507 /* 508 * The Intel SDM says (Volume 3, 7.2.1): 509 * 510 * Avoid placing a page boundary in the part of the TSS that the 511 * processor reads during a task switch (the first 104 bytes). The 512 * processor may not correctly perform address translations if a 513 * boundary occurs in this area. During a task switch, the processor 514 * reads and writes into the first 104 bytes of each TSS (using 515 * contiguous physical addresses beginning with the physical address 516 * of the first byte of the TSS). So, after TSS access begins, if 517 * part of the 104 bytes is not physically contiguous, the processor 518 * will access incorrect information without generating a page-fault 519 * exception. 520 * 521 * There are also a lot of errata involving the TSS spanning a page 522 * boundary. Assert that we're not doing that. 523 */ 524 BUILD_BUG_ON((offsetof(struct tss_struct, x86_tss) ^ 525 offsetofend(struct tss_struct, x86_tss)) & PAGE_MASK); 526 BUILD_BUG_ON(sizeof(struct tss_struct) % PAGE_SIZE != 0); 527 set_percpu_fixmap_pages(get_cpu_entry_area_index(cpu, tss), 528 &per_cpu(cpu_tss, cpu), 529 sizeof(struct tss_struct) / PAGE_SIZE, 530 PAGE_KERNEL); 531 532 #ifdef CONFIG_X86_32 533 this_cpu_write(cpu_entry_area, get_cpu_entry_area(cpu)); 534 #endif 535 } 536 537 /* Load the original GDT from the per-cpu structure */ 538 void load_direct_gdt(int cpu) 539 { 540 struct desc_ptr gdt_descr; 541 542 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 543 gdt_descr.size = GDT_SIZE - 1; 544 load_gdt(&gdt_descr); 545 } 546 EXPORT_SYMBOL_GPL(load_direct_gdt); 547 548 /* Load a fixmap remapping of the per-cpu GDT */ 549 void load_fixmap_gdt(int cpu) 550 { 551 struct desc_ptr gdt_descr; 552 553 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 554 gdt_descr.size = GDT_SIZE - 1; 555 load_gdt(&gdt_descr); 556 } 557 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 558 559 /* 560 * Current gdt points %fs at the "master" per-cpu area: after this, 561 * it's on the real one. 562 */ 563 void switch_to_new_gdt(int cpu) 564 { 565 /* Load the original GDT */ 566 load_direct_gdt(cpu); 567 /* Reload the per-cpu base */ 568 load_percpu_segment(cpu); 569 } 570 571 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 572 573 static void get_model_name(struct cpuinfo_x86 *c) 574 { 575 unsigned int *v; 576 char *p, *q, *s; 577 578 if (c->extended_cpuid_level < 0x80000004) 579 return; 580 581 v = (unsigned int *)c->x86_model_id; 582 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 583 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 584 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 585 c->x86_model_id[48] = 0; 586 587 /* Trim whitespace */ 588 p = q = s = &c->x86_model_id[0]; 589 590 while (*p == ' ') 591 p++; 592 593 while (*p) { 594 /* Note the last non-whitespace index */ 595 if (!isspace(*p)) 596 s = q; 597 598 *q++ = *p++; 599 } 600 601 *(s + 1) = '\0'; 602 } 603 604 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 605 { 606 unsigned int n, dummy, ebx, ecx, edx, l2size; 607 608 n = c->extended_cpuid_level; 609 610 if (n >= 0x80000005) { 611 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 612 c->x86_cache_size = (ecx>>24) + (edx>>24); 613 #ifdef CONFIG_X86_64 614 /* On K8 L1 TLB is inclusive, so don't count it */ 615 c->x86_tlbsize = 0; 616 #endif 617 } 618 619 if (n < 0x80000006) /* Some chips just has a large L1. */ 620 return; 621 622 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 623 l2size = ecx >> 16; 624 625 #ifdef CONFIG_X86_64 626 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 627 #else 628 /* do processor-specific cache resizing */ 629 if (this_cpu->legacy_cache_size) 630 l2size = this_cpu->legacy_cache_size(c, l2size); 631 632 /* Allow user to override all this if necessary. */ 633 if (cachesize_override != -1) 634 l2size = cachesize_override; 635 636 if (l2size == 0) 637 return; /* Again, no L2 cache is possible */ 638 #endif 639 640 c->x86_cache_size = l2size; 641 } 642 643 u16 __read_mostly tlb_lli_4k[NR_INFO]; 644 u16 __read_mostly tlb_lli_2m[NR_INFO]; 645 u16 __read_mostly tlb_lli_4m[NR_INFO]; 646 u16 __read_mostly tlb_lld_4k[NR_INFO]; 647 u16 __read_mostly tlb_lld_2m[NR_INFO]; 648 u16 __read_mostly tlb_lld_4m[NR_INFO]; 649 u16 __read_mostly tlb_lld_1g[NR_INFO]; 650 651 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 652 { 653 if (this_cpu->c_detect_tlb) 654 this_cpu->c_detect_tlb(c); 655 656 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 657 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 658 tlb_lli_4m[ENTRIES]); 659 660 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 661 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 662 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 663 } 664 665 void detect_ht(struct cpuinfo_x86 *c) 666 { 667 #ifdef CONFIG_SMP 668 u32 eax, ebx, ecx, edx; 669 int index_msb, core_bits; 670 static bool printed; 671 672 if (!cpu_has(c, X86_FEATURE_HT)) 673 return; 674 675 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 676 goto out; 677 678 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 679 return; 680 681 cpuid(1, &eax, &ebx, &ecx, &edx); 682 683 smp_num_siblings = (ebx & 0xff0000) >> 16; 684 685 if (smp_num_siblings == 1) { 686 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 687 goto out; 688 } 689 690 if (smp_num_siblings <= 1) 691 goto out; 692 693 index_msb = get_count_order(smp_num_siblings); 694 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 695 696 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 697 698 index_msb = get_count_order(smp_num_siblings); 699 700 core_bits = get_count_order(c->x86_max_cores); 701 702 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 703 ((1 << core_bits) - 1); 704 705 out: 706 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 707 pr_info("CPU: Physical Processor ID: %d\n", 708 c->phys_proc_id); 709 pr_info("CPU: Processor Core ID: %d\n", 710 c->cpu_core_id); 711 printed = 1; 712 } 713 #endif 714 } 715 716 static void get_cpu_vendor(struct cpuinfo_x86 *c) 717 { 718 char *v = c->x86_vendor_id; 719 int i; 720 721 for (i = 0; i < X86_VENDOR_NUM; i++) { 722 if (!cpu_devs[i]) 723 break; 724 725 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 726 (cpu_devs[i]->c_ident[1] && 727 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 728 729 this_cpu = cpu_devs[i]; 730 c->x86_vendor = this_cpu->c_x86_vendor; 731 return; 732 } 733 } 734 735 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 736 "CPU: Your system may be unstable.\n", v); 737 738 c->x86_vendor = X86_VENDOR_UNKNOWN; 739 this_cpu = &default_cpu; 740 } 741 742 void cpu_detect(struct cpuinfo_x86 *c) 743 { 744 /* Get vendor name */ 745 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 746 (unsigned int *)&c->x86_vendor_id[0], 747 (unsigned int *)&c->x86_vendor_id[8], 748 (unsigned int *)&c->x86_vendor_id[4]); 749 750 c->x86 = 4; 751 /* Intel-defined flags: level 0x00000001 */ 752 if (c->cpuid_level >= 0x00000001) { 753 u32 junk, tfms, cap0, misc; 754 755 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 756 c->x86 = x86_family(tfms); 757 c->x86_model = x86_model(tfms); 758 c->x86_mask = x86_stepping(tfms); 759 760 if (cap0 & (1<<19)) { 761 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 762 c->x86_cache_alignment = c->x86_clflush_size; 763 } 764 } 765 } 766 767 static void apply_forced_caps(struct cpuinfo_x86 *c) 768 { 769 int i; 770 771 for (i = 0; i < NCAPINTS; i++) { 772 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 773 c->x86_capability[i] |= cpu_caps_set[i]; 774 } 775 } 776 777 void get_cpu_cap(struct cpuinfo_x86 *c) 778 { 779 u32 eax, ebx, ecx, edx; 780 781 /* Intel-defined flags: level 0x00000001 */ 782 if (c->cpuid_level >= 0x00000001) { 783 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 784 785 c->x86_capability[CPUID_1_ECX] = ecx; 786 c->x86_capability[CPUID_1_EDX] = edx; 787 } 788 789 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 790 if (c->cpuid_level >= 0x00000006) 791 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 792 793 /* Additional Intel-defined flags: level 0x00000007 */ 794 if (c->cpuid_level >= 0x00000007) { 795 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 796 c->x86_capability[CPUID_7_0_EBX] = ebx; 797 c->x86_capability[CPUID_7_ECX] = ecx; 798 } 799 800 /* Extended state features: level 0x0000000d */ 801 if (c->cpuid_level >= 0x0000000d) { 802 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 803 804 c->x86_capability[CPUID_D_1_EAX] = eax; 805 } 806 807 /* Additional Intel-defined flags: level 0x0000000F */ 808 if (c->cpuid_level >= 0x0000000F) { 809 810 /* QoS sub-leaf, EAX=0Fh, ECX=0 */ 811 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); 812 c->x86_capability[CPUID_F_0_EDX] = edx; 813 814 if (cpu_has(c, X86_FEATURE_CQM_LLC)) { 815 /* will be overridden if occupancy monitoring exists */ 816 c->x86_cache_max_rmid = ebx; 817 818 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 819 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); 820 c->x86_capability[CPUID_F_1_EDX] = edx; 821 822 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || 823 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || 824 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { 825 c->x86_cache_max_rmid = ecx; 826 c->x86_cache_occ_scale = ebx; 827 } 828 } else { 829 c->x86_cache_max_rmid = -1; 830 c->x86_cache_occ_scale = -1; 831 } 832 } 833 834 /* AMD-defined flags: level 0x80000001 */ 835 eax = cpuid_eax(0x80000000); 836 c->extended_cpuid_level = eax; 837 838 if ((eax & 0xffff0000) == 0x80000000) { 839 if (eax >= 0x80000001) { 840 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 841 842 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 843 c->x86_capability[CPUID_8000_0001_EDX] = edx; 844 } 845 } 846 847 if (c->extended_cpuid_level >= 0x80000007) { 848 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 849 850 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 851 c->x86_power = edx; 852 } 853 854 if (c->extended_cpuid_level >= 0x80000008) { 855 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 856 857 c->x86_virt_bits = (eax >> 8) & 0xff; 858 c->x86_phys_bits = eax & 0xff; 859 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 860 } 861 #ifdef CONFIG_X86_32 862 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 863 c->x86_phys_bits = 36; 864 #endif 865 866 if (c->extended_cpuid_level >= 0x8000000a) 867 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 868 869 init_scattered_cpuid_features(c); 870 871 /* 872 * Clear/Set all flags overridden by options, after probe. 873 * This needs to happen each time we re-probe, which may happen 874 * several times during CPU initialization. 875 */ 876 apply_forced_caps(c); 877 } 878 879 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 880 { 881 #ifdef CONFIG_X86_32 882 int i; 883 884 /* 885 * First of all, decide if this is a 486 or higher 886 * It's a 486 if we can modify the AC flag 887 */ 888 if (flag_is_changeable_p(X86_EFLAGS_AC)) 889 c->x86 = 4; 890 else 891 c->x86 = 3; 892 893 for (i = 0; i < X86_VENDOR_NUM; i++) 894 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 895 c->x86_vendor_id[0] = 0; 896 cpu_devs[i]->c_identify(c); 897 if (c->x86_vendor_id[0]) { 898 get_cpu_vendor(c); 899 break; 900 } 901 } 902 #endif 903 } 904 905 /* 906 * Do minimum CPU detection early. 907 * Fields really needed: vendor, cpuid_level, family, model, mask, 908 * cache alignment. 909 * The others are not touched to avoid unwanted side effects. 910 * 911 * WARNING: this function is only called on the BP. Don't add code here 912 * that is supposed to run on all CPUs. 913 */ 914 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 915 { 916 #ifdef CONFIG_X86_64 917 c->x86_clflush_size = 64; 918 c->x86_phys_bits = 36; 919 c->x86_virt_bits = 48; 920 #else 921 c->x86_clflush_size = 32; 922 c->x86_phys_bits = 32; 923 c->x86_virt_bits = 32; 924 #endif 925 c->x86_cache_alignment = c->x86_clflush_size; 926 927 memset(&c->x86_capability, 0, sizeof c->x86_capability); 928 c->extended_cpuid_level = 0; 929 930 /* cyrix could have cpuid enabled via c_identify()*/ 931 if (have_cpuid_p()) { 932 cpu_detect(c); 933 get_cpu_vendor(c); 934 get_cpu_cap(c); 935 setup_force_cpu_cap(X86_FEATURE_CPUID); 936 937 if (this_cpu->c_early_init) 938 this_cpu->c_early_init(c); 939 940 c->cpu_index = 0; 941 filter_cpuid_features(c, false); 942 943 if (this_cpu->c_bsp_init) 944 this_cpu->c_bsp_init(c); 945 } else { 946 identify_cpu_without_cpuid(c); 947 setup_clear_cpu_cap(X86_FEATURE_CPUID); 948 } 949 950 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 951 fpu__init_system(c); 952 953 #ifdef CONFIG_X86_32 954 /* 955 * Regardless of whether PCID is enumerated, the SDM says 956 * that it can't be enabled in 32-bit mode. 957 */ 958 setup_clear_cpu_cap(X86_FEATURE_PCID); 959 #endif 960 } 961 962 void __init early_cpu_init(void) 963 { 964 const struct cpu_dev *const *cdev; 965 int count = 0; 966 967 #ifdef CONFIG_PROCESSOR_SELECT 968 pr_info("KERNEL supported cpus:\n"); 969 #endif 970 971 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 972 const struct cpu_dev *cpudev = *cdev; 973 974 if (count >= X86_VENDOR_NUM) 975 break; 976 cpu_devs[count] = cpudev; 977 count++; 978 979 #ifdef CONFIG_PROCESSOR_SELECT 980 { 981 unsigned int j; 982 983 for (j = 0; j < 2; j++) { 984 if (!cpudev->c_ident[j]) 985 continue; 986 pr_info(" %s %s\n", cpudev->c_vendor, 987 cpudev->c_ident[j]); 988 } 989 } 990 #endif 991 } 992 early_identify_cpu(&boot_cpu_data); 993 } 994 995 /* 996 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 997 * unfortunately, that's not true in practice because of early VIA 998 * chips and (more importantly) broken virtualizers that are not easy 999 * to detect. In the latter case it doesn't even *fail* reliably, so 1000 * probing for it doesn't even work. Disable it completely on 32-bit 1001 * unless we can find a reliable way to detect all the broken cases. 1002 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1003 */ 1004 static void detect_nopl(struct cpuinfo_x86 *c) 1005 { 1006 #ifdef CONFIG_X86_32 1007 clear_cpu_cap(c, X86_FEATURE_NOPL); 1008 #else 1009 set_cpu_cap(c, X86_FEATURE_NOPL); 1010 #endif 1011 } 1012 1013 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 1014 { 1015 #ifdef CONFIG_X86_64 1016 /* 1017 * Empirically, writing zero to a segment selector on AMD does 1018 * not clear the base, whereas writing zero to a segment 1019 * selector on Intel does clear the base. Intel's behavior 1020 * allows slightly faster context switches in the common case 1021 * where GS is unused by the prev and next threads. 1022 * 1023 * Since neither vendor documents this anywhere that I can see, 1024 * detect it directly instead of hardcoding the choice by 1025 * vendor. 1026 * 1027 * I've designated AMD's behavior as the "bug" because it's 1028 * counterintuitive and less friendly. 1029 */ 1030 1031 unsigned long old_base, tmp; 1032 rdmsrl(MSR_FS_BASE, old_base); 1033 wrmsrl(MSR_FS_BASE, 1); 1034 loadsegment(fs, 0); 1035 rdmsrl(MSR_FS_BASE, tmp); 1036 if (tmp != 0) 1037 set_cpu_bug(c, X86_BUG_NULL_SEG); 1038 wrmsrl(MSR_FS_BASE, old_base); 1039 #endif 1040 } 1041 1042 static void generic_identify(struct cpuinfo_x86 *c) 1043 { 1044 c->extended_cpuid_level = 0; 1045 1046 if (!have_cpuid_p()) 1047 identify_cpu_without_cpuid(c); 1048 1049 /* cyrix could have cpuid enabled via c_identify()*/ 1050 if (!have_cpuid_p()) 1051 return; 1052 1053 cpu_detect(c); 1054 1055 get_cpu_vendor(c); 1056 1057 get_cpu_cap(c); 1058 1059 if (c->cpuid_level >= 0x00000001) { 1060 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1061 #ifdef CONFIG_X86_32 1062 # ifdef CONFIG_SMP 1063 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1064 # else 1065 c->apicid = c->initial_apicid; 1066 # endif 1067 #endif 1068 c->phys_proc_id = c->initial_apicid; 1069 } 1070 1071 get_model_name(c); /* Default name */ 1072 1073 detect_nopl(c); 1074 1075 detect_null_seg_behavior(c); 1076 1077 /* 1078 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1079 * systems that run Linux at CPL > 0 may or may not have the 1080 * issue, but, even if they have the issue, there's absolutely 1081 * nothing we can do about it because we can't use the real IRET 1082 * instruction. 1083 * 1084 * NB: For the time being, only 32-bit kernels support 1085 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1086 * whether to apply espfix using paravirt hooks. If any 1087 * non-paravirt system ever shows up that does *not* have the 1088 * ESPFIX issue, we can change this. 1089 */ 1090 #ifdef CONFIG_X86_32 1091 # ifdef CONFIG_PARAVIRT 1092 do { 1093 extern void native_iret(void); 1094 if (pv_cpu_ops.iret == native_iret) 1095 set_cpu_bug(c, X86_BUG_ESPFIX); 1096 } while (0); 1097 # else 1098 set_cpu_bug(c, X86_BUG_ESPFIX); 1099 # endif 1100 #endif 1101 } 1102 1103 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 1104 { 1105 /* 1106 * The heavy lifting of max_rmid and cache_occ_scale are handled 1107 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 1108 * in case CQM bits really aren't there in this CPU. 1109 */ 1110 if (c != &boot_cpu_data) { 1111 boot_cpu_data.x86_cache_max_rmid = 1112 min(boot_cpu_data.x86_cache_max_rmid, 1113 c->x86_cache_max_rmid); 1114 } 1115 } 1116 1117 /* 1118 * Validate that ACPI/mptables have the same information about the 1119 * effective APIC id and update the package map. 1120 */ 1121 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1122 { 1123 #ifdef CONFIG_SMP 1124 unsigned int apicid, cpu = smp_processor_id(); 1125 1126 apicid = apic->cpu_present_to_apicid(cpu); 1127 1128 if (apicid != c->apicid) { 1129 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1130 cpu, apicid, c->initial_apicid); 1131 } 1132 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1133 #else 1134 c->logical_proc_id = 0; 1135 #endif 1136 } 1137 1138 /* 1139 * This does the hard work of actually picking apart the CPU stuff... 1140 */ 1141 static void identify_cpu(struct cpuinfo_x86 *c) 1142 { 1143 int i; 1144 1145 c->loops_per_jiffy = loops_per_jiffy; 1146 c->x86_cache_size = -1; 1147 c->x86_vendor = X86_VENDOR_UNKNOWN; 1148 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 1149 c->x86_vendor_id[0] = '\0'; /* Unset */ 1150 c->x86_model_id[0] = '\0'; /* Unset */ 1151 c->x86_max_cores = 1; 1152 c->x86_coreid_bits = 0; 1153 c->cu_id = 0xff; 1154 #ifdef CONFIG_X86_64 1155 c->x86_clflush_size = 64; 1156 c->x86_phys_bits = 36; 1157 c->x86_virt_bits = 48; 1158 #else 1159 c->cpuid_level = -1; /* CPUID not detected */ 1160 c->x86_clflush_size = 32; 1161 c->x86_phys_bits = 32; 1162 c->x86_virt_bits = 32; 1163 #endif 1164 c->x86_cache_alignment = c->x86_clflush_size; 1165 memset(&c->x86_capability, 0, sizeof c->x86_capability); 1166 1167 generic_identify(c); 1168 1169 if (this_cpu->c_identify) 1170 this_cpu->c_identify(c); 1171 1172 /* Clear/Set all flags overridden by options, after probe */ 1173 apply_forced_caps(c); 1174 1175 #ifdef CONFIG_X86_64 1176 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1177 #endif 1178 1179 /* 1180 * Vendor-specific initialization. In this section we 1181 * canonicalize the feature flags, meaning if there are 1182 * features a certain CPU supports which CPUID doesn't 1183 * tell us, CPUID claiming incorrect flags, or other bugs, 1184 * we handle them here. 1185 * 1186 * At the end of this section, c->x86_capability better 1187 * indicate the features this CPU genuinely supports! 1188 */ 1189 if (this_cpu->c_init) 1190 this_cpu->c_init(c); 1191 1192 /* Disable the PN if appropriate */ 1193 squash_the_stupid_serial_number(c); 1194 1195 /* Set up SMEP/SMAP */ 1196 setup_smep(c); 1197 setup_smap(c); 1198 1199 /* 1200 * The vendor-specific functions might have changed features. 1201 * Now we do "generic changes." 1202 */ 1203 1204 /* Filter out anything that depends on CPUID levels we don't have */ 1205 filter_cpuid_features(c, true); 1206 1207 /* If the model name is still unset, do table lookup. */ 1208 if (!c->x86_model_id[0]) { 1209 const char *p; 1210 p = table_lookup_model(c); 1211 if (p) 1212 strcpy(c->x86_model_id, p); 1213 else 1214 /* Last resort... */ 1215 sprintf(c->x86_model_id, "%02x/%02x", 1216 c->x86, c->x86_model); 1217 } 1218 1219 #ifdef CONFIG_X86_64 1220 detect_ht(c); 1221 #endif 1222 1223 x86_init_rdrand(c); 1224 x86_init_cache_qos(c); 1225 setup_pku(c); 1226 1227 /* 1228 * Clear/Set all flags overridden by options, need do it 1229 * before following smp all cpus cap AND. 1230 */ 1231 apply_forced_caps(c); 1232 1233 /* 1234 * On SMP, boot_cpu_data holds the common feature set between 1235 * all CPUs; so make sure that we indicate which features are 1236 * common between the CPUs. The first time this routine gets 1237 * executed, c == &boot_cpu_data. 1238 */ 1239 if (c != &boot_cpu_data) { 1240 /* AND the already accumulated flags with these */ 1241 for (i = 0; i < NCAPINTS; i++) 1242 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1243 1244 /* OR, i.e. replicate the bug flags */ 1245 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1246 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1247 } 1248 1249 /* Init Machine Check Exception if available. */ 1250 mcheck_cpu_init(c); 1251 1252 select_idle_routine(c); 1253 1254 #ifdef CONFIG_NUMA 1255 numa_add_cpu(smp_processor_id()); 1256 #endif 1257 } 1258 1259 /* 1260 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1261 * on 32-bit kernels: 1262 */ 1263 #ifdef CONFIG_X86_32 1264 void enable_sep_cpu(void) 1265 { 1266 struct tss_struct *tss; 1267 int cpu; 1268 1269 if (!boot_cpu_has(X86_FEATURE_SEP)) 1270 return; 1271 1272 cpu = get_cpu(); 1273 tss = &per_cpu(cpu_tss, cpu); 1274 1275 /* 1276 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1277 * see the big comment in struct x86_hw_tss's definition. 1278 */ 1279 1280 tss->x86_tss.ss1 = __KERNEL_CS; 1281 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1282 1283 wrmsr(MSR_IA32_SYSENTER_ESP, 1284 (unsigned long)&get_cpu_entry_area(cpu)->tss + 1285 offsetofend(struct tss_struct, SYSENTER_stack), 1286 0); 1287 1288 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1289 1290 put_cpu(); 1291 } 1292 #endif 1293 1294 void __init identify_boot_cpu(void) 1295 { 1296 identify_cpu(&boot_cpu_data); 1297 #ifdef CONFIG_X86_32 1298 sysenter_setup(); 1299 enable_sep_cpu(); 1300 #endif 1301 cpu_detect_tlb(&boot_cpu_data); 1302 } 1303 1304 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1305 { 1306 BUG_ON(c == &boot_cpu_data); 1307 identify_cpu(c); 1308 #ifdef CONFIG_X86_32 1309 enable_sep_cpu(); 1310 #endif 1311 mtrr_ap_init(); 1312 validate_apic_and_package_id(c); 1313 } 1314 1315 static __init int setup_noclflush(char *arg) 1316 { 1317 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1318 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1319 return 1; 1320 } 1321 __setup("noclflush", setup_noclflush); 1322 1323 void print_cpu_info(struct cpuinfo_x86 *c) 1324 { 1325 const char *vendor = NULL; 1326 1327 if (c->x86_vendor < X86_VENDOR_NUM) { 1328 vendor = this_cpu->c_vendor; 1329 } else { 1330 if (c->cpuid_level >= 0) 1331 vendor = c->x86_vendor_id; 1332 } 1333 1334 if (vendor && !strstr(c->x86_model_id, vendor)) 1335 pr_cont("%s ", vendor); 1336 1337 if (c->x86_model_id[0]) 1338 pr_cont("%s", c->x86_model_id); 1339 else 1340 pr_cont("%d86", c->x86); 1341 1342 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1343 1344 if (c->x86_mask || c->cpuid_level >= 0) 1345 pr_cont(", stepping: 0x%x)\n", c->x86_mask); 1346 else 1347 pr_cont(")\n"); 1348 } 1349 1350 /* 1351 * clearcpuid= was already parsed in fpu__init_parse_early_param. 1352 * But we need to keep a dummy __setup around otherwise it would 1353 * show up as an environment variable for init. 1354 */ 1355 static __init int setup_clearcpuid(char *arg) 1356 { 1357 return 1; 1358 } 1359 __setup("clearcpuid=", setup_clearcpuid); 1360 1361 #ifdef CONFIG_X86_64 1362 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1363 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1364 1365 /* 1366 * The following percpu variables are hot. Align current_task to 1367 * cacheline size such that they fall in the same cacheline. 1368 */ 1369 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1370 &init_task; 1371 EXPORT_PER_CPU_SYMBOL(current_task); 1372 1373 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1374 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; 1375 1376 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1377 1378 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1379 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1380 1381 /* 1382 * Special IST stacks which the CPU switches to when it calls 1383 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1384 * limit), all of them are 4K, except the debug stack which 1385 * is 8K. 1386 */ 1387 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1388 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1389 [DEBUG_STACK - 1] = DEBUG_STKSZ 1390 }; 1391 1392 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1393 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1394 1395 /* May not be marked __init: used by software suspend */ 1396 void syscall_init(void) 1397 { 1398 int cpu = smp_processor_id(); 1399 1400 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1401 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1402 1403 #ifdef CONFIG_IA32_EMULATION 1404 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1405 /* 1406 * This only works on Intel CPUs. 1407 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1408 * This does not cause SYSENTER to jump to the wrong location, because 1409 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1410 */ 1411 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1412 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 1413 (unsigned long)&get_cpu_entry_area(cpu)->tss + 1414 offsetofend(struct tss_struct, SYSENTER_stack)); 1415 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1416 #else 1417 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1418 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1419 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1420 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1421 #endif 1422 1423 /* Flags to clear on syscall */ 1424 wrmsrl(MSR_SYSCALL_MASK, 1425 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1426 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1427 } 1428 1429 /* 1430 * Copies of the original ist values from the tss are only accessed during 1431 * debugging, no special alignment required. 1432 */ 1433 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1434 1435 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1436 DEFINE_PER_CPU(int, debug_stack_usage); 1437 1438 int is_debug_stack(unsigned long addr) 1439 { 1440 return __this_cpu_read(debug_stack_usage) || 1441 (addr <= __this_cpu_read(debug_stack_addr) && 1442 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); 1443 } 1444 NOKPROBE_SYMBOL(is_debug_stack); 1445 1446 DEFINE_PER_CPU(u32, debug_idt_ctr); 1447 1448 void debug_stack_set_zero(void) 1449 { 1450 this_cpu_inc(debug_idt_ctr); 1451 load_current_idt(); 1452 } 1453 NOKPROBE_SYMBOL(debug_stack_set_zero); 1454 1455 void debug_stack_reset(void) 1456 { 1457 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1458 return; 1459 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1460 load_current_idt(); 1461 } 1462 NOKPROBE_SYMBOL(debug_stack_reset); 1463 1464 #else /* CONFIG_X86_64 */ 1465 1466 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1467 EXPORT_PER_CPU_SYMBOL(current_task); 1468 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1469 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1470 1471 /* 1472 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1473 * the top of the kernel stack. Use an extra percpu variable to track the 1474 * top of the kernel stack directly. 1475 */ 1476 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1477 (unsigned long)&init_thread_union + THREAD_SIZE; 1478 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1479 1480 #ifdef CONFIG_CC_STACKPROTECTOR 1481 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1482 #endif 1483 1484 #endif /* CONFIG_X86_64 */ 1485 1486 /* 1487 * Clear all 6 debug registers: 1488 */ 1489 static void clear_all_debug_regs(void) 1490 { 1491 int i; 1492 1493 for (i = 0; i < 8; i++) { 1494 /* Ignore db4, db5 */ 1495 if ((i == 4) || (i == 5)) 1496 continue; 1497 1498 set_debugreg(0, i); 1499 } 1500 } 1501 1502 #ifdef CONFIG_KGDB 1503 /* 1504 * Restore debug regs if using kgdbwait and you have a kernel debugger 1505 * connection established. 1506 */ 1507 static void dbg_restore_debug_regs(void) 1508 { 1509 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1510 arch_kgdb_ops.correct_hw_break(); 1511 } 1512 #else /* ! CONFIG_KGDB */ 1513 #define dbg_restore_debug_regs() 1514 #endif /* ! CONFIG_KGDB */ 1515 1516 static void wait_for_master_cpu(int cpu) 1517 { 1518 #ifdef CONFIG_SMP 1519 /* 1520 * wait for ACK from master CPU before continuing 1521 * with AP initialization 1522 */ 1523 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1524 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1525 cpu_relax(); 1526 #endif 1527 } 1528 1529 /* 1530 * cpu_init() initializes state that is per-CPU. Some data is already 1531 * initialized (naturally) in the bootstrap process, such as the GDT 1532 * and IDT. We reload them nevertheless, this function acts as a 1533 * 'CPU state barrier', nothing should get across. 1534 * A lot of state is already set up in PDA init for 64 bit 1535 */ 1536 #ifdef CONFIG_X86_64 1537 1538 void cpu_init(void) 1539 { 1540 struct orig_ist *oist; 1541 struct task_struct *me; 1542 struct tss_struct *t; 1543 unsigned long v; 1544 int cpu = raw_smp_processor_id(); 1545 int i; 1546 1547 wait_for_master_cpu(cpu); 1548 1549 /* 1550 * Initialize the CR4 shadow before doing anything that could 1551 * try to read it. 1552 */ 1553 cr4_init_shadow(); 1554 1555 if (cpu) 1556 load_ucode_ap(); 1557 1558 t = &per_cpu(cpu_tss, cpu); 1559 oist = &per_cpu(orig_ist, cpu); 1560 1561 #ifdef CONFIG_NUMA 1562 if (this_cpu_read(numa_node) == 0 && 1563 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1564 set_numa_node(early_cpu_to_node(cpu)); 1565 #endif 1566 1567 me = current; 1568 1569 pr_debug("Initializing CPU#%d\n", cpu); 1570 1571 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1572 1573 /* 1574 * Initialize the per-CPU GDT with the boot GDT, 1575 * and set up the GDT descriptor: 1576 */ 1577 1578 switch_to_new_gdt(cpu); 1579 loadsegment(fs, 0); 1580 1581 load_current_idt(); 1582 1583 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1584 syscall_init(); 1585 1586 wrmsrl(MSR_FS_BASE, 0); 1587 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1588 barrier(); 1589 1590 x86_configure_nx(); 1591 x2apic_setup(); 1592 1593 /* 1594 * set up and load the per-CPU TSS 1595 */ 1596 if (!oist->ist[0]) { 1597 char *estacks = per_cpu(exception_stacks, cpu); 1598 1599 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1600 estacks += exception_stack_sizes[v]; 1601 oist->ist[v] = t->x86_tss.ist[v] = 1602 (unsigned long)estacks; 1603 if (v == DEBUG_STACK-1) 1604 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1605 } 1606 } 1607 1608 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; 1609 1610 /* 1611 * <= is required because the CPU will access up to 1612 * 8 bits beyond the end of the IO permission bitmap. 1613 */ 1614 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1615 t->io_bitmap[i] = ~0UL; 1616 1617 mmgrab(&init_mm); 1618 me->active_mm = &init_mm; 1619 BUG_ON(me->mm); 1620 initialize_tlbstate_and_flush(); 1621 enter_lazy_tlb(&init_mm, me); 1622 1623 setup_cpu_entry_area(cpu); 1624 1625 /* 1626 * Initialize the TSS. sp0 points to the entry trampoline stack 1627 * regardless of what task is running. 1628 */ 1629 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1630 load_TR_desc(); 1631 load_sp0((unsigned long)&get_cpu_entry_area(cpu)->tss + 1632 offsetofend(struct tss_struct, SYSENTER_stack)); 1633 1634 load_mm_ldt(&init_mm); 1635 1636 clear_all_debug_regs(); 1637 dbg_restore_debug_regs(); 1638 1639 fpu__init_cpu(); 1640 1641 if (is_uv_system()) 1642 uv_cpu_init(); 1643 1644 load_fixmap_gdt(cpu); 1645 } 1646 1647 #else 1648 1649 void cpu_init(void) 1650 { 1651 int cpu = smp_processor_id(); 1652 struct task_struct *curr = current; 1653 struct tss_struct *t = &per_cpu(cpu_tss, cpu); 1654 1655 wait_for_master_cpu(cpu); 1656 1657 /* 1658 * Initialize the CR4 shadow before doing anything that could 1659 * try to read it. 1660 */ 1661 cr4_init_shadow(); 1662 1663 show_ucode_info_early(); 1664 1665 pr_info("Initializing CPU#%d\n", cpu); 1666 1667 if (cpu_feature_enabled(X86_FEATURE_VME) || 1668 boot_cpu_has(X86_FEATURE_TSC) || 1669 boot_cpu_has(X86_FEATURE_DE)) 1670 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1671 1672 load_current_idt(); 1673 switch_to_new_gdt(cpu); 1674 1675 /* 1676 * Set up and load the per-CPU TSS and LDT 1677 */ 1678 mmgrab(&init_mm); 1679 curr->active_mm = &init_mm; 1680 BUG_ON(curr->mm); 1681 initialize_tlbstate_and_flush(); 1682 enter_lazy_tlb(&init_mm, curr); 1683 1684 setup_cpu_entry_area(cpu); 1685 1686 /* 1687 * Initialize the TSS. Don't bother initializing sp0, as the initial 1688 * task never enters user mode. 1689 */ 1690 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1691 load_TR_desc(); 1692 1693 load_mm_ldt(&init_mm); 1694 1695 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; 1696 1697 #ifdef CONFIG_DOUBLEFAULT 1698 /* Set up doublefault TSS pointer in the GDT */ 1699 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1700 #endif 1701 1702 clear_all_debug_regs(); 1703 dbg_restore_debug_regs(); 1704 1705 fpu__init_cpu(); 1706 1707 load_fixmap_gdt(cpu); 1708 } 1709 #endif 1710 1711 static void bsp_resume(void) 1712 { 1713 if (this_cpu->c_bsp_resume) 1714 this_cpu->c_bsp_resume(&boot_cpu_data); 1715 } 1716 1717 static struct syscore_ops cpu_syscore_ops = { 1718 .resume = bsp_resume, 1719 }; 1720 1721 static int __init init_cpu_syscore(void) 1722 { 1723 register_syscore_ops(&cpu_syscore_ops); 1724 return 0; 1725 } 1726 core_initcall(init_cpu_syscore); 1727