1 /* 2 * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. 3 * 4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo 5 * Moved from arch/x86/kernel/apic/io_apic.c. 6 * Jiang Liu <jiang.liu@linux.intel.com> 7 * Enable support of hierarchical irqdomains 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #include <linux/interrupt.h> 14 #include <linux/init.h> 15 #include <linux/compiler.h> 16 #include <linux/slab.h> 17 #include <asm/irqdomain.h> 18 #include <asm/hw_irq.h> 19 #include <asm/apic.h> 20 #include <asm/i8259.h> 21 #include <asm/desc.h> 22 #include <asm/irq_remapping.h> 23 24 struct apic_chip_data { 25 struct irq_cfg cfg; 26 cpumask_var_t domain; 27 cpumask_var_t old_domain; 28 u8 move_in_progress : 1; 29 }; 30 31 struct irq_domain *x86_vector_domain; 32 EXPORT_SYMBOL_GPL(x86_vector_domain); 33 static DEFINE_RAW_SPINLOCK(vector_lock); 34 static cpumask_var_t vector_cpumask, vector_searchmask, searched_cpumask; 35 static struct irq_chip lapic_controller; 36 #ifdef CONFIG_X86_IO_APIC 37 static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY]; 38 #endif 39 40 void lock_vector_lock(void) 41 { 42 /* Used to the online set of cpus does not change 43 * during assign_irq_vector. 44 */ 45 raw_spin_lock(&vector_lock); 46 } 47 48 void unlock_vector_lock(void) 49 { 50 raw_spin_unlock(&vector_lock); 51 } 52 53 static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data) 54 { 55 if (!irq_data) 56 return NULL; 57 58 while (irq_data->parent_data) 59 irq_data = irq_data->parent_data; 60 61 return irq_data->chip_data; 62 } 63 64 struct irq_cfg *irqd_cfg(struct irq_data *irq_data) 65 { 66 struct apic_chip_data *data = apic_chip_data(irq_data); 67 68 return data ? &data->cfg : NULL; 69 } 70 EXPORT_SYMBOL_GPL(irqd_cfg); 71 72 struct irq_cfg *irq_cfg(unsigned int irq) 73 { 74 return irqd_cfg(irq_get_irq_data(irq)); 75 } 76 77 static struct apic_chip_data *alloc_apic_chip_data(int node) 78 { 79 struct apic_chip_data *data; 80 81 data = kzalloc_node(sizeof(*data), GFP_KERNEL, node); 82 if (!data) 83 return NULL; 84 if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node)) 85 goto out_data; 86 if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node)) 87 goto out_domain; 88 return data; 89 out_domain: 90 free_cpumask_var(data->domain); 91 out_data: 92 kfree(data); 93 return NULL; 94 } 95 96 static void free_apic_chip_data(struct apic_chip_data *data) 97 { 98 if (data) { 99 free_cpumask_var(data->domain); 100 free_cpumask_var(data->old_domain); 101 kfree(data); 102 } 103 } 104 105 static int __assign_irq_vector(int irq, struct apic_chip_data *d, 106 const struct cpumask *mask) 107 { 108 /* 109 * NOTE! The local APIC isn't very good at handling 110 * multiple interrupts at the same interrupt level. 111 * As the interrupt level is determined by taking the 112 * vector number and shifting that right by 4, we 113 * want to spread these out a bit so that they don't 114 * all fall in the same interrupt level. 115 * 116 * Also, we've got to be careful not to trash gate 117 * 0x80, because int 0x80 is hm, kind of importantish. ;) 118 */ 119 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; 120 static int current_offset = VECTOR_OFFSET_START % 16; 121 int cpu, vector; 122 123 /* 124 * If there is still a move in progress or the previous move has not 125 * been cleaned up completely, tell the caller to come back later. 126 */ 127 if (d->move_in_progress || 128 cpumask_intersects(d->old_domain, cpu_online_mask)) 129 return -EBUSY; 130 131 /* Only try and allocate irqs on cpus that are present */ 132 cpumask_clear(d->old_domain); 133 cpumask_clear(searched_cpumask); 134 cpu = cpumask_first_and(mask, cpu_online_mask); 135 while (cpu < nr_cpu_ids) { 136 int new_cpu, offset; 137 138 /* Get the possible target cpus for @mask/@cpu from the apic */ 139 apic->vector_allocation_domain(cpu, vector_cpumask, mask); 140 141 /* 142 * Clear the offline cpus from @vector_cpumask for searching 143 * and verify whether the result overlaps with @mask. If true, 144 * then the call to apic->cpu_mask_to_apicid() will 145 * succeed as well. If not, no point in trying to find a 146 * vector in this mask. 147 */ 148 cpumask_and(vector_searchmask, vector_cpumask, cpu_online_mask); 149 if (!cpumask_intersects(vector_searchmask, mask)) 150 goto next_cpu; 151 152 if (cpumask_subset(vector_cpumask, d->domain)) { 153 if (cpumask_equal(vector_cpumask, d->domain)) 154 goto success; 155 /* 156 * Mark the cpus which are not longer in the mask for 157 * cleanup. 158 */ 159 cpumask_andnot(d->old_domain, d->domain, vector_cpumask); 160 vector = d->cfg.vector; 161 goto update; 162 } 163 164 vector = current_vector; 165 offset = current_offset; 166 next: 167 vector += 16; 168 if (vector >= first_system_vector) { 169 offset = (offset + 1) % 16; 170 vector = FIRST_EXTERNAL_VECTOR + offset; 171 } 172 173 /* If the search wrapped around, try the next cpu */ 174 if (unlikely(current_vector == vector)) 175 goto next_cpu; 176 177 if (test_bit(vector, used_vectors)) 178 goto next; 179 180 for_each_cpu(new_cpu, vector_searchmask) { 181 if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector])) 182 goto next; 183 } 184 /* Found one! */ 185 current_vector = vector; 186 current_offset = offset; 187 /* Schedule the old vector for cleanup on all cpus */ 188 if (d->cfg.vector) 189 cpumask_copy(d->old_domain, d->domain); 190 for_each_cpu(new_cpu, vector_searchmask) 191 per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq); 192 goto update; 193 194 next_cpu: 195 /* 196 * We exclude the current @vector_cpumask from the requested 197 * @mask and try again with the next online cpu in the 198 * result. We cannot modify @mask, so we use @vector_cpumask 199 * as a temporary buffer here as it will be reassigned when 200 * calling apic->vector_allocation_domain() above. 201 */ 202 cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask); 203 cpumask_andnot(vector_cpumask, mask, searched_cpumask); 204 cpu = cpumask_first_and(vector_cpumask, cpu_online_mask); 205 continue; 206 } 207 return -ENOSPC; 208 209 update: 210 /* 211 * Exclude offline cpus from the cleanup mask and set the 212 * move_in_progress flag when the result is not empty. 213 */ 214 cpumask_and(d->old_domain, d->old_domain, cpu_online_mask); 215 d->move_in_progress = !cpumask_empty(d->old_domain); 216 d->cfg.old_vector = d->move_in_progress ? d->cfg.vector : 0; 217 d->cfg.vector = vector; 218 cpumask_copy(d->domain, vector_cpumask); 219 success: 220 /* 221 * Cache destination APIC IDs into cfg->dest_apicid. This cannot fail 222 * as we already established, that mask & d->domain & cpu_online_mask 223 * is not empty. 224 * 225 * vector_searchmask is a subset of d->domain and has the offline 226 * cpus masked out. 227 */ 228 cpumask_and(vector_searchmask, vector_searchmask, mask); 229 BUG_ON(apic->cpu_mask_to_apicid(vector_searchmask, &d->cfg.dest_apicid)); 230 return 0; 231 } 232 233 static int assign_irq_vector(int irq, struct apic_chip_data *data, 234 const struct cpumask *mask) 235 { 236 int err; 237 unsigned long flags; 238 239 raw_spin_lock_irqsave(&vector_lock, flags); 240 err = __assign_irq_vector(irq, data, mask); 241 raw_spin_unlock_irqrestore(&vector_lock, flags); 242 return err; 243 } 244 245 static int assign_irq_vector_policy(int irq, int node, 246 struct apic_chip_data *data, 247 struct irq_alloc_info *info) 248 { 249 if (info && info->mask) 250 return assign_irq_vector(irq, data, info->mask); 251 if (node != NUMA_NO_NODE && 252 assign_irq_vector(irq, data, cpumask_of_node(node)) == 0) 253 return 0; 254 return assign_irq_vector(irq, data, apic->target_cpus()); 255 } 256 257 static void clear_irq_vector(int irq, struct apic_chip_data *data) 258 { 259 struct irq_desc *desc; 260 int cpu, vector; 261 262 if (!data->cfg.vector) 263 return; 264 265 vector = data->cfg.vector; 266 for_each_cpu_and(cpu, data->domain, cpu_online_mask) 267 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; 268 269 data->cfg.vector = 0; 270 cpumask_clear(data->domain); 271 272 /* 273 * If move is in progress or the old_domain mask is not empty, 274 * i.e. the cleanup IPI has not been processed yet, we need to remove 275 * the old references to desc from all cpus vector tables. 276 */ 277 if (!data->move_in_progress && cpumask_empty(data->old_domain)) 278 return; 279 280 desc = irq_to_desc(irq); 281 for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) { 282 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; 283 vector++) { 284 if (per_cpu(vector_irq, cpu)[vector] != desc) 285 continue; 286 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; 287 break; 288 } 289 } 290 data->move_in_progress = 0; 291 } 292 293 void init_irq_alloc_info(struct irq_alloc_info *info, 294 const struct cpumask *mask) 295 { 296 memset(info, 0, sizeof(*info)); 297 info->mask = mask; 298 } 299 300 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) 301 { 302 if (src) 303 *dst = *src; 304 else 305 memset(dst, 0, sizeof(*dst)); 306 } 307 308 static void x86_vector_free_irqs(struct irq_domain *domain, 309 unsigned int virq, unsigned int nr_irqs) 310 { 311 struct apic_chip_data *apic_data; 312 struct irq_data *irq_data; 313 unsigned long flags; 314 int i; 315 316 for (i = 0; i < nr_irqs; i++) { 317 irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i); 318 if (irq_data && irq_data->chip_data) { 319 raw_spin_lock_irqsave(&vector_lock, flags); 320 clear_irq_vector(virq + i, irq_data->chip_data); 321 apic_data = irq_data->chip_data; 322 irq_domain_reset_irq_data(irq_data); 323 raw_spin_unlock_irqrestore(&vector_lock, flags); 324 free_apic_chip_data(apic_data); 325 #ifdef CONFIG_X86_IO_APIC 326 if (virq + i < nr_legacy_irqs()) 327 legacy_irq_data[virq + i] = NULL; 328 #endif 329 } 330 } 331 } 332 333 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, 334 unsigned int nr_irqs, void *arg) 335 { 336 struct irq_alloc_info *info = arg; 337 struct apic_chip_data *data; 338 struct irq_data *irq_data; 339 int i, err, node; 340 341 if (disable_apic) 342 return -ENXIO; 343 344 /* Currently vector allocator can't guarantee contiguous allocations */ 345 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) 346 return -ENOSYS; 347 348 for (i = 0; i < nr_irqs; i++) { 349 irq_data = irq_domain_get_irq_data(domain, virq + i); 350 BUG_ON(!irq_data); 351 node = irq_data_get_node(irq_data); 352 #ifdef CONFIG_X86_IO_APIC 353 if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i]) 354 data = legacy_irq_data[virq + i]; 355 else 356 #endif 357 data = alloc_apic_chip_data(node); 358 if (!data) { 359 err = -ENOMEM; 360 goto error; 361 } 362 363 irq_data->chip = &lapic_controller; 364 irq_data->chip_data = data; 365 irq_data->hwirq = virq + i; 366 err = assign_irq_vector_policy(virq + i, node, data, info); 367 if (err) 368 goto error; 369 } 370 371 return 0; 372 373 error: 374 x86_vector_free_irqs(domain, virq, i + 1); 375 return err; 376 } 377 378 static const struct irq_domain_ops x86_vector_domain_ops = { 379 .alloc = x86_vector_alloc_irqs, 380 .free = x86_vector_free_irqs, 381 }; 382 383 int __init arch_probe_nr_irqs(void) 384 { 385 int nr; 386 387 if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) 388 nr_irqs = NR_VECTORS * nr_cpu_ids; 389 390 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; 391 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) 392 /* 393 * for MSI and HT dyn irq 394 */ 395 if (gsi_top <= NR_IRQS_LEGACY) 396 nr += 8 * nr_cpu_ids; 397 else 398 nr += gsi_top * 16; 399 #endif 400 if (nr < nr_irqs) 401 nr_irqs = nr; 402 403 /* 404 * We don't know if PIC is present at this point so we need to do 405 * probe() to get the right number of legacy IRQs. 406 */ 407 return legacy_pic->probe(); 408 } 409 410 #ifdef CONFIG_X86_IO_APIC 411 static void init_legacy_irqs(void) 412 { 413 int i, node = cpu_to_node(0); 414 struct apic_chip_data *data; 415 416 /* 417 * For legacy IRQ's, start with assigning irq0 to irq15 to 418 * ISA_IRQ_VECTOR(i) for all cpu's. 419 */ 420 for (i = 0; i < nr_legacy_irqs(); i++) { 421 data = legacy_irq_data[i] = alloc_apic_chip_data(node); 422 BUG_ON(!data); 423 424 data->cfg.vector = ISA_IRQ_VECTOR(i); 425 cpumask_setall(data->domain); 426 irq_set_chip_data(i, data); 427 } 428 } 429 #else 430 static void init_legacy_irqs(void) { } 431 #endif 432 433 int __init arch_early_irq_init(void) 434 { 435 struct fwnode_handle *fn; 436 437 init_legacy_irqs(); 438 439 fn = irq_domain_alloc_named_fwnode("VECTOR"); 440 BUG_ON(!fn); 441 x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops, 442 NULL); 443 BUG_ON(x86_vector_domain == NULL); 444 irq_domain_free_fwnode(fn); 445 irq_set_default_host(x86_vector_domain); 446 447 arch_init_msi_domain(x86_vector_domain); 448 arch_init_htirq_domain(x86_vector_domain); 449 450 BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL)); 451 BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL)); 452 BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL)); 453 454 return arch_early_ioapic_init(); 455 } 456 457 /* Initialize vector_irq on a new cpu */ 458 static void __setup_vector_irq(int cpu) 459 { 460 struct apic_chip_data *data; 461 struct irq_desc *desc; 462 int irq, vector; 463 464 /* Mark the inuse vectors */ 465 for_each_irq_desc(irq, desc) { 466 struct irq_data *idata = irq_desc_get_irq_data(desc); 467 468 data = apic_chip_data(idata); 469 if (!data || !cpumask_test_cpu(cpu, data->domain)) 470 continue; 471 vector = data->cfg.vector; 472 per_cpu(vector_irq, cpu)[vector] = desc; 473 } 474 /* Mark the free vectors */ 475 for (vector = 0; vector < NR_VECTORS; ++vector) { 476 desc = per_cpu(vector_irq, cpu)[vector]; 477 if (IS_ERR_OR_NULL(desc)) 478 continue; 479 480 data = apic_chip_data(irq_desc_get_irq_data(desc)); 481 if (!cpumask_test_cpu(cpu, data->domain)) 482 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; 483 } 484 } 485 486 /* 487 * Setup the vector to irq mappings. Must be called with vector_lock held. 488 */ 489 void setup_vector_irq(int cpu) 490 { 491 int irq; 492 493 lockdep_assert_held(&vector_lock); 494 /* 495 * On most of the platforms, legacy PIC delivers the interrupts on the 496 * boot cpu. But there are certain platforms where PIC interrupts are 497 * delivered to multiple cpu's. If the legacy IRQ is handled by the 498 * legacy PIC, for the new cpu that is coming online, setup the static 499 * legacy vector to irq mapping: 500 */ 501 for (irq = 0; irq < nr_legacy_irqs(); irq++) 502 per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq); 503 504 __setup_vector_irq(cpu); 505 } 506 507 static int apic_retrigger_irq(struct irq_data *irq_data) 508 { 509 struct apic_chip_data *data = apic_chip_data(irq_data); 510 unsigned long flags; 511 int cpu; 512 513 raw_spin_lock_irqsave(&vector_lock, flags); 514 cpu = cpumask_first_and(data->domain, cpu_online_mask); 515 apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector); 516 raw_spin_unlock_irqrestore(&vector_lock, flags); 517 518 return 1; 519 } 520 521 void apic_ack_edge(struct irq_data *data) 522 { 523 irq_complete_move(irqd_cfg(data)); 524 irq_move_irq(data); 525 ack_APIC_irq(); 526 } 527 528 static int apic_set_affinity(struct irq_data *irq_data, 529 const struct cpumask *dest, bool force) 530 { 531 struct apic_chip_data *data = irq_data->chip_data; 532 int err, irq = irq_data->irq; 533 534 if (!IS_ENABLED(CONFIG_SMP)) 535 return -EPERM; 536 537 if (!cpumask_intersects(dest, cpu_online_mask)) 538 return -EINVAL; 539 540 err = assign_irq_vector(irq, data, dest); 541 return err ? err : IRQ_SET_MASK_OK; 542 } 543 544 static struct irq_chip lapic_controller = { 545 .name = "APIC", 546 .irq_ack = apic_ack_edge, 547 .irq_set_affinity = apic_set_affinity, 548 .irq_retrigger = apic_retrigger_irq, 549 }; 550 551 #ifdef CONFIG_SMP 552 static void __send_cleanup_vector(struct apic_chip_data *data) 553 { 554 raw_spin_lock(&vector_lock); 555 cpumask_and(data->old_domain, data->old_domain, cpu_online_mask); 556 data->move_in_progress = 0; 557 if (!cpumask_empty(data->old_domain)) 558 apic->send_IPI_mask(data->old_domain, IRQ_MOVE_CLEANUP_VECTOR); 559 raw_spin_unlock(&vector_lock); 560 } 561 562 void send_cleanup_vector(struct irq_cfg *cfg) 563 { 564 struct apic_chip_data *data; 565 566 data = container_of(cfg, struct apic_chip_data, cfg); 567 if (data->move_in_progress) 568 __send_cleanup_vector(data); 569 } 570 571 asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void) 572 { 573 unsigned vector, me; 574 575 entering_ack_irq(); 576 577 /* Prevent vectors vanishing under us */ 578 raw_spin_lock(&vector_lock); 579 580 me = smp_processor_id(); 581 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { 582 struct apic_chip_data *data; 583 struct irq_desc *desc; 584 unsigned int irr; 585 586 retry: 587 desc = __this_cpu_read(vector_irq[vector]); 588 if (IS_ERR_OR_NULL(desc)) 589 continue; 590 591 if (!raw_spin_trylock(&desc->lock)) { 592 raw_spin_unlock(&vector_lock); 593 cpu_relax(); 594 raw_spin_lock(&vector_lock); 595 goto retry; 596 } 597 598 data = apic_chip_data(irq_desc_get_irq_data(desc)); 599 if (!data) 600 goto unlock; 601 602 /* 603 * Nothing to cleanup if irq migration is in progress 604 * or this cpu is not set in the cleanup mask. 605 */ 606 if (data->move_in_progress || 607 !cpumask_test_cpu(me, data->old_domain)) 608 goto unlock; 609 610 /* 611 * We have two cases to handle here: 612 * 1) vector is unchanged but the target mask got reduced 613 * 2) vector and the target mask has changed 614 * 615 * #1 is obvious, but in #2 we have two vectors with the same 616 * irq descriptor: the old and the new vector. So we need to 617 * make sure that we only cleanup the old vector. The new 618 * vector has the current @vector number in the config and 619 * this cpu is part of the target mask. We better leave that 620 * one alone. 621 */ 622 if (vector == data->cfg.vector && 623 cpumask_test_cpu(me, data->domain)) 624 goto unlock; 625 626 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 627 /* 628 * Check if the vector that needs to be cleanedup is 629 * registered at the cpu's IRR. If so, then this is not 630 * the best time to clean it up. Lets clean it up in the 631 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR 632 * to myself. 633 */ 634 if (irr & (1 << (vector % 32))) { 635 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); 636 goto unlock; 637 } 638 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); 639 cpumask_clear_cpu(me, data->old_domain); 640 unlock: 641 raw_spin_unlock(&desc->lock); 642 } 643 644 raw_spin_unlock(&vector_lock); 645 646 exiting_irq(); 647 } 648 649 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) 650 { 651 unsigned me; 652 struct apic_chip_data *data; 653 654 data = container_of(cfg, struct apic_chip_data, cfg); 655 if (likely(!data->move_in_progress)) 656 return; 657 658 me = smp_processor_id(); 659 if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain)) 660 __send_cleanup_vector(data); 661 } 662 663 void irq_complete_move(struct irq_cfg *cfg) 664 { 665 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); 666 } 667 668 /* 669 * Called from fixup_irqs() with @desc->lock held and interrupts disabled. 670 */ 671 void irq_force_complete_move(struct irq_desc *desc) 672 { 673 struct irq_data *irqdata; 674 struct apic_chip_data *data; 675 struct irq_cfg *cfg; 676 unsigned int cpu; 677 678 /* 679 * The function is called for all descriptors regardless of which 680 * irqdomain they belong to. For example if an IRQ is provided by 681 * an irq_chip as part of a GPIO driver, the chip data for that 682 * descriptor is specific to the irq_chip in question. 683 * 684 * Check first that the chip_data is what we expect 685 * (apic_chip_data) before touching it any further. 686 */ 687 irqdata = irq_domain_get_irq_data(x86_vector_domain, 688 irq_desc_get_irq(desc)); 689 if (!irqdata) 690 return; 691 692 data = apic_chip_data(irqdata); 693 cfg = data ? &data->cfg : NULL; 694 695 if (!cfg) 696 return; 697 698 /* 699 * This is tricky. If the cleanup of @data->old_domain has not been 700 * done yet, then the following setaffinity call will fail with 701 * -EBUSY. This can leave the interrupt in a stale state. 702 * 703 * All CPUs are stuck in stop machine with interrupts disabled so 704 * calling __irq_complete_move() would be completely pointless. 705 */ 706 raw_spin_lock(&vector_lock); 707 /* 708 * Clean out all offline cpus (including the outgoing one) from the 709 * old_domain mask. 710 */ 711 cpumask_and(data->old_domain, data->old_domain, cpu_online_mask); 712 713 /* 714 * If move_in_progress is cleared and the old_domain mask is empty, 715 * then there is nothing to cleanup. fixup_irqs() will take care of 716 * the stale vectors on the outgoing cpu. 717 */ 718 if (!data->move_in_progress && cpumask_empty(data->old_domain)) { 719 raw_spin_unlock(&vector_lock); 720 return; 721 } 722 723 /* 724 * 1) The interrupt is in move_in_progress state. That means that we 725 * have not seen an interrupt since the io_apic was reprogrammed to 726 * the new vector. 727 * 728 * 2) The interrupt has fired on the new vector, but the cleanup IPIs 729 * have not been processed yet. 730 */ 731 if (data->move_in_progress) { 732 /* 733 * In theory there is a race: 734 * 735 * set_ioapic(new_vector) <-- Interrupt is raised before update 736 * is effective, i.e. it's raised on 737 * the old vector. 738 * 739 * So if the target cpu cannot handle that interrupt before 740 * the old vector is cleaned up, we get a spurious interrupt 741 * and in the worst case the ioapic irq line becomes stale. 742 * 743 * But in case of cpu hotplug this should be a non issue 744 * because if the affinity update happens right before all 745 * cpus rendevouz in stop machine, there is no way that the 746 * interrupt can be blocked on the target cpu because all cpus 747 * loops first with interrupts enabled in stop machine, so the 748 * old vector is not yet cleaned up when the interrupt fires. 749 * 750 * So the only way to run into this issue is if the delivery 751 * of the interrupt on the apic/system bus would be delayed 752 * beyond the point where the target cpu disables interrupts 753 * in stop machine. I doubt that it can happen, but at least 754 * there is a theroretical chance. Virtualization might be 755 * able to expose this, but AFAICT the IOAPIC emulation is not 756 * as stupid as the real hardware. 757 * 758 * Anyway, there is nothing we can do about that at this point 759 * w/o refactoring the whole fixup_irq() business completely. 760 * We print at least the irq number and the old vector number, 761 * so we have the necessary information when a problem in that 762 * area arises. 763 */ 764 pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n", 765 irqdata->irq, cfg->old_vector); 766 } 767 /* 768 * If old_domain is not empty, then other cpus still have the irq 769 * descriptor set in their vector array. Clean it up. 770 */ 771 for_each_cpu(cpu, data->old_domain) 772 per_cpu(vector_irq, cpu)[cfg->old_vector] = VECTOR_UNUSED; 773 774 /* Cleanup the left overs of the (half finished) move */ 775 cpumask_clear(data->old_domain); 776 data->move_in_progress = 0; 777 raw_spin_unlock(&vector_lock); 778 } 779 #endif 780 781 static void __init print_APIC_field(int base) 782 { 783 int i; 784 785 printk(KERN_DEBUG); 786 787 for (i = 0; i < 8; i++) 788 pr_cont("%08x", apic_read(base + i*0x10)); 789 790 pr_cont("\n"); 791 } 792 793 static void __init print_local_APIC(void *dummy) 794 { 795 unsigned int i, v, ver, maxlvt; 796 u64 icr; 797 798 pr_debug("printing local APIC contents on CPU#%d/%d:\n", 799 smp_processor_id(), hard_smp_processor_id()); 800 v = apic_read(APIC_ID); 801 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); 802 v = apic_read(APIC_LVR); 803 pr_info("... APIC VERSION: %08x\n", v); 804 ver = GET_APIC_VERSION(v); 805 maxlvt = lapic_get_maxlvt(); 806 807 v = apic_read(APIC_TASKPRI); 808 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); 809 810 /* !82489DX */ 811 if (APIC_INTEGRATED(ver)) { 812 if (!APIC_XAPIC(ver)) { 813 v = apic_read(APIC_ARBPRI); 814 pr_debug("... APIC ARBPRI: %08x (%02x)\n", 815 v, v & APIC_ARBPRI_MASK); 816 } 817 v = apic_read(APIC_PROCPRI); 818 pr_debug("... APIC PROCPRI: %08x\n", v); 819 } 820 821 /* 822 * Remote read supported only in the 82489DX and local APIC for 823 * Pentium processors. 824 */ 825 if (!APIC_INTEGRATED(ver) || maxlvt == 3) { 826 v = apic_read(APIC_RRR); 827 pr_debug("... APIC RRR: %08x\n", v); 828 } 829 830 v = apic_read(APIC_LDR); 831 pr_debug("... APIC LDR: %08x\n", v); 832 if (!x2apic_enabled()) { 833 v = apic_read(APIC_DFR); 834 pr_debug("... APIC DFR: %08x\n", v); 835 } 836 v = apic_read(APIC_SPIV); 837 pr_debug("... APIC SPIV: %08x\n", v); 838 839 pr_debug("... APIC ISR field:\n"); 840 print_APIC_field(APIC_ISR); 841 pr_debug("... APIC TMR field:\n"); 842 print_APIC_field(APIC_TMR); 843 pr_debug("... APIC IRR field:\n"); 844 print_APIC_field(APIC_IRR); 845 846 /* !82489DX */ 847 if (APIC_INTEGRATED(ver)) { 848 /* Due to the Pentium erratum 3AP. */ 849 if (maxlvt > 3) 850 apic_write(APIC_ESR, 0); 851 852 v = apic_read(APIC_ESR); 853 pr_debug("... APIC ESR: %08x\n", v); 854 } 855 856 icr = apic_icr_read(); 857 pr_debug("... APIC ICR: %08x\n", (u32)icr); 858 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); 859 860 v = apic_read(APIC_LVTT); 861 pr_debug("... APIC LVTT: %08x\n", v); 862 863 if (maxlvt > 3) { 864 /* PC is LVT#4. */ 865 v = apic_read(APIC_LVTPC); 866 pr_debug("... APIC LVTPC: %08x\n", v); 867 } 868 v = apic_read(APIC_LVT0); 869 pr_debug("... APIC LVT0: %08x\n", v); 870 v = apic_read(APIC_LVT1); 871 pr_debug("... APIC LVT1: %08x\n", v); 872 873 if (maxlvt > 2) { 874 /* ERR is LVT#3. */ 875 v = apic_read(APIC_LVTERR); 876 pr_debug("... APIC LVTERR: %08x\n", v); 877 } 878 879 v = apic_read(APIC_TMICT); 880 pr_debug("... APIC TMICT: %08x\n", v); 881 v = apic_read(APIC_TMCCT); 882 pr_debug("... APIC TMCCT: %08x\n", v); 883 v = apic_read(APIC_TDCR); 884 pr_debug("... APIC TDCR: %08x\n", v); 885 886 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { 887 v = apic_read(APIC_EFEAT); 888 maxlvt = (v >> 16) & 0xff; 889 pr_debug("... APIC EFEAT: %08x\n", v); 890 v = apic_read(APIC_ECTRL); 891 pr_debug("... APIC ECTRL: %08x\n", v); 892 for (i = 0; i < maxlvt; i++) { 893 v = apic_read(APIC_EILVTn(i)); 894 pr_debug("... APIC EILVT%d: %08x\n", i, v); 895 } 896 } 897 pr_cont("\n"); 898 } 899 900 static void __init print_local_APICs(int maxcpu) 901 { 902 int cpu; 903 904 if (!maxcpu) 905 return; 906 907 preempt_disable(); 908 for_each_online_cpu(cpu) { 909 if (cpu >= maxcpu) 910 break; 911 smp_call_function_single(cpu, print_local_APIC, NULL, 1); 912 } 913 preempt_enable(); 914 } 915 916 static void __init print_PIC(void) 917 { 918 unsigned int v; 919 unsigned long flags; 920 921 if (!nr_legacy_irqs()) 922 return; 923 924 pr_debug("\nprinting PIC contents\n"); 925 926 raw_spin_lock_irqsave(&i8259A_lock, flags); 927 928 v = inb(0xa1) << 8 | inb(0x21); 929 pr_debug("... PIC IMR: %04x\n", v); 930 931 v = inb(0xa0) << 8 | inb(0x20); 932 pr_debug("... PIC IRR: %04x\n", v); 933 934 outb(0x0b, 0xa0); 935 outb(0x0b, 0x20); 936 v = inb(0xa0) << 8 | inb(0x20); 937 outb(0x0a, 0xa0); 938 outb(0x0a, 0x20); 939 940 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 941 942 pr_debug("... PIC ISR: %04x\n", v); 943 944 v = inb(0x4d1) << 8 | inb(0x4d0); 945 pr_debug("... PIC ELCR: %04x\n", v); 946 } 947 948 static int show_lapic __initdata = 1; 949 static __init int setup_show_lapic(char *arg) 950 { 951 int num = -1; 952 953 if (strcmp(arg, "all") == 0) { 954 show_lapic = CONFIG_NR_CPUS; 955 } else { 956 get_option(&arg, &num); 957 if (num >= 0) 958 show_lapic = num; 959 } 960 961 return 1; 962 } 963 __setup("show_lapic=", setup_show_lapic); 964 965 static int __init print_ICs(void) 966 { 967 if (apic_verbosity == APIC_QUIET) 968 return 0; 969 970 print_PIC(); 971 972 /* don't print out if apic is not there */ 973 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 974 return 0; 975 976 print_local_APICs(show_lapic); 977 print_IO_APICs(); 978 979 return 0; 980 } 981 982 late_initcall(print_ICs); 983