1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Numascale NumaConnect-Specific APIC Code 7 * 8 * Copyright (C) 2011 Numascale AS. All rights reserved. 9 * 10 * Send feedback to <support@numascale.com> 11 * 12 */ 13 #include <linux/types.h> 14 #include <linux/init.h> 15 #include <linux/pgtable.h> 16 17 #include <asm/numachip/numachip.h> 18 #include <asm/numachip/numachip_csr.h> 19 20 21 #include "local.h" 22 23 u8 numachip_system __read_mostly; 24 static const struct apic apic_numachip1; 25 static const struct apic apic_numachip2; 26 static void (*numachip_apic_icr_write)(int apicid, unsigned int val) __read_mostly; 27 28 static unsigned int numachip1_get_apic_id(unsigned long x) 29 { 30 unsigned long value; 31 unsigned int id = (x >> 24) & 0xff; 32 33 if (static_cpu_has(X86_FEATURE_NODEID_MSR)) { 34 rdmsrl(MSR_FAM10H_NODE_ID, value); 35 id |= (value << 2) & 0xff00; 36 } 37 38 return id; 39 } 40 41 static u32 numachip1_set_apic_id(unsigned int id) 42 { 43 return (id & 0xff) << 24; 44 } 45 46 static unsigned int numachip2_get_apic_id(unsigned long x) 47 { 48 u64 mcfg; 49 50 rdmsrl(MSR_FAM10H_MMIO_CONF_BASE, mcfg); 51 return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24); 52 } 53 54 static u32 numachip2_set_apic_id(unsigned int id) 55 { 56 return id << 24; 57 } 58 59 static int numachip_apic_id_valid(u32 apicid) 60 { 61 /* Trust what bootloader passes in MADT */ 62 return 1; 63 } 64 65 static int numachip_phys_pkg_id(int initial_apic_id, int index_msb) 66 { 67 return initial_apic_id >> index_msb; 68 } 69 70 static void numachip1_apic_icr_write(int apicid, unsigned int val) 71 { 72 write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val); 73 } 74 75 static void numachip2_apic_icr_write(int apicid, unsigned int val) 76 { 77 numachip2_write32_lcsr(NUMACHIP2_APIC_ICR, (apicid << 12) | val); 78 } 79 80 static int numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip) 81 { 82 numachip_apic_icr_write(phys_apicid, APIC_DM_INIT); 83 numachip_apic_icr_write(phys_apicid, APIC_DM_STARTUP | 84 (start_rip >> 12)); 85 86 return 0; 87 } 88 89 static void numachip_send_IPI_one(int cpu, int vector) 90 { 91 int local_apicid, apicid = per_cpu(x86_cpu_to_apicid, cpu); 92 unsigned int dmode; 93 94 preempt_disable(); 95 local_apicid = __this_cpu_read(x86_cpu_to_apicid); 96 97 /* Send via local APIC where non-local part matches */ 98 if (!((apicid ^ local_apicid) >> NUMACHIP_LAPIC_BITS)) { 99 unsigned long flags; 100 101 local_irq_save(flags); 102 __default_send_IPI_dest_field(apicid, vector, 103 APIC_DEST_PHYSICAL); 104 local_irq_restore(flags); 105 preempt_enable(); 106 return; 107 } 108 preempt_enable(); 109 110 dmode = (vector == NMI_VECTOR) ? APIC_DM_NMI : APIC_DM_FIXED; 111 numachip_apic_icr_write(apicid, dmode | vector); 112 } 113 114 static void numachip_send_IPI_mask(const struct cpumask *mask, int vector) 115 { 116 unsigned int cpu; 117 118 for_each_cpu(cpu, mask) 119 numachip_send_IPI_one(cpu, vector); 120 } 121 122 static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask, 123 int vector) 124 { 125 unsigned int this_cpu = smp_processor_id(); 126 unsigned int cpu; 127 128 for_each_cpu(cpu, mask) { 129 if (cpu != this_cpu) 130 numachip_send_IPI_one(cpu, vector); 131 } 132 } 133 134 static void numachip_send_IPI_allbutself(int vector) 135 { 136 unsigned int this_cpu = smp_processor_id(); 137 unsigned int cpu; 138 139 for_each_online_cpu(cpu) { 140 if (cpu != this_cpu) 141 numachip_send_IPI_one(cpu, vector); 142 } 143 } 144 145 static void numachip_send_IPI_all(int vector) 146 { 147 numachip_send_IPI_mask(cpu_online_mask, vector); 148 } 149 150 static void numachip_send_IPI_self(int vector) 151 { 152 apic_write(APIC_SELF_IPI, vector); 153 } 154 155 static int __init numachip1_probe(void) 156 { 157 return apic == &apic_numachip1; 158 } 159 160 static int __init numachip2_probe(void) 161 { 162 return apic == &apic_numachip2; 163 } 164 165 static void fixup_cpu_id(struct cpuinfo_x86 *c, int node) 166 { 167 u64 val; 168 u32 nodes = 1; 169 170 this_cpu_write(cpu_llc_id, node); 171 172 /* Account for nodes per socket in multi-core-module processors */ 173 if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 174 rdmsrl(MSR_FAM10H_NODE_ID, val); 175 nodes = ((val >> 3) & 7) + 1; 176 } 177 178 c->phys_proc_id = node / nodes; 179 } 180 181 static int __init numachip_system_init(void) 182 { 183 /* Map the LCSR area and set up the apic_icr_write function */ 184 switch (numachip_system) { 185 case 1: 186 init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE); 187 numachip_apic_icr_write = numachip1_apic_icr_write; 188 break; 189 case 2: 190 init_extra_mapping_uc(NUMACHIP2_LCSR_BASE, NUMACHIP2_LCSR_SIZE); 191 numachip_apic_icr_write = numachip2_apic_icr_write; 192 break; 193 default: 194 return 0; 195 } 196 197 x86_cpuinit.fixup_cpu_id = fixup_cpu_id; 198 x86_init.pci.arch_init = pci_numachip_init; 199 200 return 0; 201 } 202 early_initcall(numachip_system_init); 203 204 static int numachip1_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 205 { 206 if ((strncmp(oem_id, "NUMASC", 6) != 0) || 207 (strncmp(oem_table_id, "NCONNECT", 8) != 0)) 208 return 0; 209 210 numachip_system = 1; 211 212 return 1; 213 } 214 215 static int numachip2_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 216 { 217 if ((strncmp(oem_id, "NUMASC", 6) != 0) || 218 (strncmp(oem_table_id, "NCONECT2", 8) != 0)) 219 return 0; 220 221 numachip_system = 2; 222 223 return 1; 224 } 225 226 static const struct apic apic_numachip1 __refconst = { 227 .name = "NumaConnect system", 228 .probe = numachip1_probe, 229 .acpi_madt_oem_check = numachip1_acpi_madt_oem_check, 230 .apic_id_valid = numachip_apic_id_valid, 231 232 .delivery_mode = APIC_DELIVERY_MODE_FIXED, 233 .dest_mode_logical = false, 234 235 .disable_esr = 0, 236 237 .check_apicid_used = NULL, 238 .ioapic_phys_id_map = NULL, 239 .cpu_present_to_apicid = default_cpu_present_to_apicid, 240 .phys_pkg_id = numachip_phys_pkg_id, 241 242 .max_apic_id = UINT_MAX, 243 .get_apic_id = numachip1_get_apic_id, 244 .set_apic_id = numachip1_set_apic_id, 245 246 .calc_dest_apicid = apic_default_calc_apicid, 247 248 .send_IPI = numachip_send_IPI_one, 249 .send_IPI_mask = numachip_send_IPI_mask, 250 .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself, 251 .send_IPI_allbutself = numachip_send_IPI_allbutself, 252 .send_IPI_all = numachip_send_IPI_all, 253 .send_IPI_self = numachip_send_IPI_self, 254 255 .wakeup_secondary_cpu = numachip_wakeup_secondary, 256 257 .read = native_apic_mem_read, 258 .write = native_apic_mem_write, 259 .eoi_write = native_apic_mem_write, 260 .icr_read = native_apic_icr_read, 261 .icr_write = native_apic_icr_write, 262 }; 263 264 apic_driver(apic_numachip1); 265 266 static const struct apic apic_numachip2 __refconst = { 267 .name = "NumaConnect2 system", 268 .probe = numachip2_probe, 269 .acpi_madt_oem_check = numachip2_acpi_madt_oem_check, 270 .apic_id_valid = numachip_apic_id_valid, 271 272 .delivery_mode = APIC_DELIVERY_MODE_FIXED, 273 .dest_mode_logical = false, 274 275 .disable_esr = 0, 276 277 .check_apicid_used = NULL, 278 .ioapic_phys_id_map = NULL, 279 .cpu_present_to_apicid = default_cpu_present_to_apicid, 280 .phys_pkg_id = numachip_phys_pkg_id, 281 282 .max_apic_id = UINT_MAX, 283 .get_apic_id = numachip2_get_apic_id, 284 .set_apic_id = numachip2_set_apic_id, 285 286 .calc_dest_apicid = apic_default_calc_apicid, 287 288 .send_IPI = numachip_send_IPI_one, 289 .send_IPI_mask = numachip_send_IPI_mask, 290 .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself, 291 .send_IPI_allbutself = numachip_send_IPI_allbutself, 292 .send_IPI_all = numachip_send_IPI_all, 293 .send_IPI_self = numachip_send_IPI_self, 294 295 .wakeup_secondary_cpu = numachip_wakeup_secondary, 296 297 .read = native_apic_mem_read, 298 .write = native_apic_mem_write, 299 .eoi_write = native_apic_mem_write, 300 .icr_read = native_apic_icr_read, 301 .icr_write = native_apic_icr_write, 302 }; 303 304 apic_driver(apic_numachip2); 305