191f410aaSSuma Hegde /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 291f410aaSSuma Hegde 391f410aaSSuma Hegde #ifndef _UAPI_ASM_X86_AMD_HSMP_H_ 491f410aaSSuma Hegde #define _UAPI_ASM_X86_AMD_HSMP_H_ 591f410aaSSuma Hegde 691f410aaSSuma Hegde #include <linux/types.h> 791f410aaSSuma Hegde 891f410aaSSuma Hegde #pragma pack(4) 991f410aaSSuma Hegde 1091f410aaSSuma Hegde #define HSMP_MAX_MSG_LEN 8 1191f410aaSSuma Hegde 1291f410aaSSuma Hegde /* 1391f410aaSSuma Hegde * HSMP Messages supported 1491f410aaSSuma Hegde */ 1591f410aaSSuma Hegde enum hsmp_message_ids { 1691f410aaSSuma Hegde HSMP_TEST = 1, /* 01h Increments input value by 1 */ 1791f410aaSSuma Hegde HSMP_GET_SMU_VER, /* 02h SMU FW version */ 1891f410aaSSuma Hegde HSMP_GET_PROTO_VER, /* 03h HSMP interface version */ 1991f410aaSSuma Hegde HSMP_GET_SOCKET_POWER, /* 04h average package power consumption */ 2091f410aaSSuma Hegde HSMP_SET_SOCKET_POWER_LIMIT, /* 05h Set the socket power limit */ 2191f410aaSSuma Hegde HSMP_GET_SOCKET_POWER_LIMIT, /* 06h Get current socket power limit */ 2291f410aaSSuma Hegde HSMP_GET_SOCKET_POWER_LIMIT_MAX,/* 07h Get maximum socket power value */ 2391f410aaSSuma Hegde HSMP_SET_BOOST_LIMIT, /* 08h Set a core maximum frequency limit */ 2491f410aaSSuma Hegde HSMP_SET_BOOST_LIMIT_SOCKET, /* 09h Set socket maximum frequency level */ 2591f410aaSSuma Hegde HSMP_GET_BOOST_LIMIT, /* 0Ah Get current frequency limit */ 2691f410aaSSuma Hegde HSMP_GET_PROC_HOT, /* 0Bh Get PROCHOT status */ 2791f410aaSSuma Hegde HSMP_SET_XGMI_LINK_WIDTH, /* 0Ch Set max and min width of xGMI Link */ 2891f410aaSSuma Hegde HSMP_SET_DF_PSTATE, /* 0Dh Alter APEnable/Disable messages behavior */ 2991f410aaSSuma Hegde HSMP_SET_AUTO_DF_PSTATE, /* 0Eh Enable DF P-State Performance Boost algorithm */ 3091f410aaSSuma Hegde HSMP_GET_FCLK_MCLK, /* 0Fh Get FCLK and MEMCLK for current socket */ 3191f410aaSSuma Hegde HSMP_GET_CCLK_THROTTLE_LIMIT, /* 10h Get CCLK frequency limit in socket */ 3291f410aaSSuma Hegde HSMP_GET_C0_PERCENT, /* 11h Get average C0 residency in socket */ 3391f410aaSSuma Hegde HSMP_SET_NBIO_DPM_LEVEL, /* 12h Set max/min LCLK DPM Level for a given NBIO */ 34*830fe3c3SSuma Hegde HSMP_GET_NBIO_DPM_LEVEL, /* 13h Get LCLK DPM level min and max for a given NBIO */ 35*830fe3c3SSuma Hegde HSMP_GET_DDR_BANDWIDTH, /* 14h Get theoretical maximum and current DDR Bandwidth */ 36*830fe3c3SSuma Hegde HSMP_GET_TEMP_MONITOR, /* 15h Get socket temperature */ 37*830fe3c3SSuma Hegde HSMP_GET_DIMM_TEMP_RANGE, /* 16h Get per-DIMM temperature range and refresh rate */ 38*830fe3c3SSuma Hegde HSMP_GET_DIMM_POWER, /* 17h Get per-DIMM power consumption */ 39*830fe3c3SSuma Hegde HSMP_GET_DIMM_THERMAL, /* 18h Get per-DIMM thermal sensors */ 40*830fe3c3SSuma Hegde HSMP_GET_SOCKET_FREQ_LIMIT, /* 19h Get current active frequency per socket */ 41*830fe3c3SSuma Hegde HSMP_GET_CCLK_CORE_LIMIT, /* 1Ah Get CCLK frequency limit per core */ 42*830fe3c3SSuma Hegde HSMP_GET_RAILS_SVI, /* 1Bh Get SVI-based Telemetry for all rails */ 43*830fe3c3SSuma Hegde HSMP_GET_SOCKET_FMAX_FMIN, /* 1Ch Get Fmax and Fmin per socket */ 44*830fe3c3SSuma Hegde HSMP_GET_IOLINK_BANDWITH, /* 1Dh Get current bandwidth on IO Link */ 45*830fe3c3SSuma Hegde HSMP_GET_XGMI_BANDWITH, /* 1Eh Get current bandwidth on xGMI Link */ 46*830fe3c3SSuma Hegde HSMP_SET_GMI3_WIDTH, /* 1Fh Set max and min GMI3 Link width */ 47*830fe3c3SSuma Hegde HSMP_SET_PCI_RATE, /* 20h Control link rate on PCIe devices */ 48*830fe3c3SSuma Hegde HSMP_SET_POWER_MODE, /* 21h Select power efficiency profile policy */ 49*830fe3c3SSuma Hegde HSMP_SET_PSTATE_MAX_MIN, /* 22h Set the max and min DF P-State */ 5091f410aaSSuma Hegde HSMP_MSG_ID_MAX, 5191f410aaSSuma Hegde }; 5291f410aaSSuma Hegde 5391f410aaSSuma Hegde struct hsmp_message { 5491f410aaSSuma Hegde __u32 msg_id; /* Message ID */ 5591f410aaSSuma Hegde __u16 num_args; /* Number of input argument words in message */ 5691f410aaSSuma Hegde __u16 response_sz; /* Number of expected output/response words */ 5791f410aaSSuma Hegde __u32 args[HSMP_MAX_MSG_LEN]; /* argument/response buffer */ 5891f410aaSSuma Hegde __u16 sock_ind; /* socket number */ 5991f410aaSSuma Hegde }; 6091f410aaSSuma Hegde 6191f410aaSSuma Hegde enum hsmp_msg_type { 6291f410aaSSuma Hegde HSMP_RSVD = -1, 6391f410aaSSuma Hegde HSMP_SET = 0, 6491f410aaSSuma Hegde HSMP_GET = 1, 6591f410aaSSuma Hegde }; 6691f410aaSSuma Hegde 6791f410aaSSuma Hegde struct hsmp_msg_desc { 6891f410aaSSuma Hegde int num_args; 6991f410aaSSuma Hegde int response_sz; 7091f410aaSSuma Hegde enum hsmp_msg_type type; 7191f410aaSSuma Hegde }; 7291f410aaSSuma Hegde 7391f410aaSSuma Hegde /* 7491f410aaSSuma Hegde * User may use these comments as reference, please find the 7591f410aaSSuma Hegde * supported list of messages and message definition in the 7691f410aaSSuma Hegde * HSMP chapter of respective family/model PPR. 7791f410aaSSuma Hegde * 7891f410aaSSuma Hegde * Not supported messages would return -ENOMSG. 7991f410aaSSuma Hegde */ 8091f410aaSSuma Hegde static const struct hsmp_msg_desc hsmp_msg_desc_table[] = { 8191f410aaSSuma Hegde /* RESERVED */ 8291f410aaSSuma Hegde {0, 0, HSMP_RSVD}, 8391f410aaSSuma Hegde 8491f410aaSSuma Hegde /* 8591f410aaSSuma Hegde * HSMP_TEST, num_args = 1, response_sz = 1 8691f410aaSSuma Hegde * input: args[0] = xx 8791f410aaSSuma Hegde * output: args[0] = xx + 1 8891f410aaSSuma Hegde */ 8991f410aaSSuma Hegde {1, 1, HSMP_GET}, 9091f410aaSSuma Hegde 9191f410aaSSuma Hegde /* 9291f410aaSSuma Hegde * HSMP_GET_SMU_VER, num_args = 0, response_sz = 1 9391f410aaSSuma Hegde * output: args[0] = smu fw ver 9491f410aaSSuma Hegde */ 9591f410aaSSuma Hegde {0, 1, HSMP_GET}, 9691f410aaSSuma Hegde 9791f410aaSSuma Hegde /* 9891f410aaSSuma Hegde * HSMP_GET_PROTO_VER, num_args = 0, response_sz = 1 9991f410aaSSuma Hegde * output: args[0] = proto version 10091f410aaSSuma Hegde */ 10191f410aaSSuma Hegde {0, 1, HSMP_GET}, 10291f410aaSSuma Hegde 10391f410aaSSuma Hegde /* 10491f410aaSSuma Hegde * HSMP_GET_SOCKET_POWER, num_args = 0, response_sz = 1 10591f410aaSSuma Hegde * output: args[0] = socket power in mWatts 10691f410aaSSuma Hegde */ 10791f410aaSSuma Hegde {0, 1, HSMP_GET}, 10891f410aaSSuma Hegde 10991f410aaSSuma Hegde /* 11091f410aaSSuma Hegde * HSMP_SET_SOCKET_POWER_LIMIT, num_args = 1, response_sz = 0 11191f410aaSSuma Hegde * input: args[0] = power limit value in mWatts 11291f410aaSSuma Hegde */ 11391f410aaSSuma Hegde {1, 0, HSMP_SET}, 11491f410aaSSuma Hegde 11591f410aaSSuma Hegde /* 11691f410aaSSuma Hegde * HSMP_GET_SOCKET_POWER_LIMIT, num_args = 0, response_sz = 1 11791f410aaSSuma Hegde * output: args[0] = socket power limit value in mWatts 11891f410aaSSuma Hegde */ 11991f410aaSSuma Hegde {0, 1, HSMP_GET}, 12091f410aaSSuma Hegde 12191f410aaSSuma Hegde /* 12291f410aaSSuma Hegde * HSMP_GET_SOCKET_POWER_LIMIT_MAX, num_args = 0, response_sz = 1 12391f410aaSSuma Hegde * output: args[0] = maximuam socket power limit in mWatts 12491f410aaSSuma Hegde */ 12591f410aaSSuma Hegde {0, 1, HSMP_GET}, 12691f410aaSSuma Hegde 12791f410aaSSuma Hegde /* 12891f410aaSSuma Hegde * HSMP_SET_BOOST_LIMIT, num_args = 1, response_sz = 0 12991f410aaSSuma Hegde * input: args[0] = apic id[31:16] + boost limit value in MHz[15:0] 13091f410aaSSuma Hegde */ 13191f410aaSSuma Hegde {1, 0, HSMP_SET}, 13291f410aaSSuma Hegde 13391f410aaSSuma Hegde /* 13491f410aaSSuma Hegde * HSMP_SET_BOOST_LIMIT_SOCKET, num_args = 1, response_sz = 0 13591f410aaSSuma Hegde * input: args[0] = boost limit value in MHz 13691f410aaSSuma Hegde */ 13791f410aaSSuma Hegde {1, 0, HSMP_SET}, 13891f410aaSSuma Hegde 13991f410aaSSuma Hegde /* 14091f410aaSSuma Hegde * HSMP_GET_BOOST_LIMIT, num_args = 1, response_sz = 1 14191f410aaSSuma Hegde * input: args[0] = apic id 14291f410aaSSuma Hegde * output: args[0] = boost limit value in MHz 14391f410aaSSuma Hegde */ 14491f410aaSSuma Hegde {1, 1, HSMP_GET}, 14591f410aaSSuma Hegde 14691f410aaSSuma Hegde /* 14791f410aaSSuma Hegde * HSMP_GET_PROC_HOT, num_args = 0, response_sz = 1 14891f410aaSSuma Hegde * output: args[0] = proc hot status 14991f410aaSSuma Hegde */ 15091f410aaSSuma Hegde {0, 1, HSMP_GET}, 15191f410aaSSuma Hegde 15291f410aaSSuma Hegde /* 15391f410aaSSuma Hegde * HSMP_SET_XGMI_LINK_WIDTH, num_args = 1, response_sz = 0 15491f410aaSSuma Hegde * input: args[0] = min link width[15:8] + max link width[7:0] 15591f410aaSSuma Hegde */ 15691f410aaSSuma Hegde {1, 0, HSMP_SET}, 15791f410aaSSuma Hegde 15891f410aaSSuma Hegde /* 15991f410aaSSuma Hegde * HSMP_SET_DF_PSTATE, num_args = 1, response_sz = 0 16091f410aaSSuma Hegde * input: args[0] = df pstate[7:0] 16191f410aaSSuma Hegde */ 16291f410aaSSuma Hegde {1, 0, HSMP_SET}, 16391f410aaSSuma Hegde 16491f410aaSSuma Hegde /* HSMP_SET_AUTO_DF_PSTATE, num_args = 0, response_sz = 0 */ 16591f410aaSSuma Hegde {0, 0, HSMP_SET}, 16691f410aaSSuma Hegde 16791f410aaSSuma Hegde /* 16891f410aaSSuma Hegde * HSMP_GET_FCLK_MCLK, num_args = 0, response_sz = 2 16991f410aaSSuma Hegde * output: args[0] = fclk in MHz, args[1] = mclk in MHz 17091f410aaSSuma Hegde */ 17191f410aaSSuma Hegde {0, 2, HSMP_GET}, 17291f410aaSSuma Hegde 17391f410aaSSuma Hegde /* 17491f410aaSSuma Hegde * HSMP_GET_CCLK_THROTTLE_LIMIT, num_args = 0, response_sz = 1 17591f410aaSSuma Hegde * output: args[0] = core clock in MHz 17691f410aaSSuma Hegde */ 17791f410aaSSuma Hegde {0, 1, HSMP_GET}, 17891f410aaSSuma Hegde 17991f410aaSSuma Hegde /* 18091f410aaSSuma Hegde * HSMP_GET_C0_PERCENT, num_args = 0, response_sz = 1 18191f410aaSSuma Hegde * output: args[0] = average c0 residency 18291f410aaSSuma Hegde */ 18391f410aaSSuma Hegde {0, 1, HSMP_GET}, 18491f410aaSSuma Hegde 18591f410aaSSuma Hegde /* 18691f410aaSSuma Hegde * HSMP_SET_NBIO_DPM_LEVEL, num_args = 1, response_sz = 0 18791f410aaSSuma Hegde * input: args[0] = nbioid[23:16] + max dpm level[15:8] + min dpm level[7:0] 18891f410aaSSuma Hegde */ 18991f410aaSSuma Hegde {1, 0, HSMP_SET}, 19091f410aaSSuma Hegde 191*830fe3c3SSuma Hegde /* 192*830fe3c3SSuma Hegde * HSMP_GET_NBIO_DPM_LEVEL, num_args = 1, response_sz = 1 193*830fe3c3SSuma Hegde * input: args[0] = nbioid[23:16] 194*830fe3c3SSuma Hegde * output: args[0] = max dpm level[15:8] + min dpm level[7:0] 195*830fe3c3SSuma Hegde */ 196*830fe3c3SSuma Hegde {1, 1, HSMP_GET}, 19791f410aaSSuma Hegde 19891f410aaSSuma Hegde /* 19991f410aaSSuma Hegde * HSMP_GET_DDR_BANDWIDTH, num_args = 0, response_sz = 1 20091f410aaSSuma Hegde * output: args[0] = max bw in Gbps[31:20] + utilised bw in Gbps[19:8] + 20191f410aaSSuma Hegde * bw in percentage[7:0] 20291f410aaSSuma Hegde */ 20391f410aaSSuma Hegde {0, 1, HSMP_GET}, 20491f410aaSSuma Hegde 20591f410aaSSuma Hegde /* 20691f410aaSSuma Hegde * HSMP_GET_TEMP_MONITOR, num_args = 0, response_sz = 1 20791f410aaSSuma Hegde * output: args[0] = temperature in degree celsius. [15:8] integer part + 20891f410aaSSuma Hegde * [7:5] fractional part 20991f410aaSSuma Hegde */ 21091f410aaSSuma Hegde {0, 1, HSMP_GET}, 211*830fe3c3SSuma Hegde 212*830fe3c3SSuma Hegde /* 213*830fe3c3SSuma Hegde * HSMP_GET_DIMM_TEMP_RANGE, num_args = 1, response_sz = 1 214*830fe3c3SSuma Hegde * input: args[0] = DIMM address[7:0] 215*830fe3c3SSuma Hegde * output: args[0] = refresh rate[3] + temperature range[2:0] 216*830fe3c3SSuma Hegde */ 217*830fe3c3SSuma Hegde {1, 1, HSMP_GET}, 218*830fe3c3SSuma Hegde 219*830fe3c3SSuma Hegde /* 220*830fe3c3SSuma Hegde * HSMP_GET_DIMM_POWER, num_args = 1, response_sz = 1 221*830fe3c3SSuma Hegde * input: args[0] = DIMM address[7:0] 222*830fe3c3SSuma Hegde * output: args[0] = DIMM power in mW[31:17] + update rate in ms[16:8] + 223*830fe3c3SSuma Hegde * DIMM address[7:0] 224*830fe3c3SSuma Hegde */ 225*830fe3c3SSuma Hegde {1, 1, HSMP_GET}, 226*830fe3c3SSuma Hegde 227*830fe3c3SSuma Hegde /* 228*830fe3c3SSuma Hegde * HSMP_GET_DIMM_THERMAL, num_args = 1, response_sz = 1 229*830fe3c3SSuma Hegde * input: args[0] = DIMM address[7:0] 230*830fe3c3SSuma Hegde * output: args[0] = temperature in degree celcius[31:21] + update rate in ms[16:8] + 231*830fe3c3SSuma Hegde * DIMM address[7:0] 232*830fe3c3SSuma Hegde */ 233*830fe3c3SSuma Hegde {1, 1, HSMP_GET}, 234*830fe3c3SSuma Hegde 235*830fe3c3SSuma Hegde /* 236*830fe3c3SSuma Hegde * HSMP_GET_SOCKET_FREQ_LIMIT, num_args = 0, response_sz = 1 237*830fe3c3SSuma Hegde * output: args[0] = frequency in MHz[31:16] + frequency source[15:0] 238*830fe3c3SSuma Hegde */ 239*830fe3c3SSuma Hegde {0, 1, HSMP_GET}, 240*830fe3c3SSuma Hegde 241*830fe3c3SSuma Hegde /* 242*830fe3c3SSuma Hegde * HSMP_GET_CCLK_CORE_LIMIT, num_args = 1, response_sz = 1 243*830fe3c3SSuma Hegde * input: args[0] = apic id [31:0] 244*830fe3c3SSuma Hegde * output: args[0] = frequency in MHz[31:0] 245*830fe3c3SSuma Hegde */ 246*830fe3c3SSuma Hegde {1, 1, HSMP_GET}, 247*830fe3c3SSuma Hegde 248*830fe3c3SSuma Hegde /* 249*830fe3c3SSuma Hegde * HSMP_GET_RAILS_SVI, num_args = 0, response_sz = 1 250*830fe3c3SSuma Hegde * output: args[0] = power in mW[31:0] 251*830fe3c3SSuma Hegde */ 252*830fe3c3SSuma Hegde {0, 1, HSMP_GET}, 253*830fe3c3SSuma Hegde 254*830fe3c3SSuma Hegde /* 255*830fe3c3SSuma Hegde * HSMP_GET_SOCKET_FMAX_FMIN, num_args = 0, response_sz = 1 256*830fe3c3SSuma Hegde * output: args[0] = fmax in MHz[31:16] + fmin in MHz[15:0] 257*830fe3c3SSuma Hegde */ 258*830fe3c3SSuma Hegde {0, 1, HSMP_GET}, 259*830fe3c3SSuma Hegde 260*830fe3c3SSuma Hegde /* 261*830fe3c3SSuma Hegde * HSMP_GET_IOLINK_BANDWITH, num_args = 1, response_sz = 1 262*830fe3c3SSuma Hegde * input: args[0] = link id[15:8] + bw type[2:0] 263*830fe3c3SSuma Hegde * output: args[0] = io bandwidth in Mbps[31:0] 264*830fe3c3SSuma Hegde */ 265*830fe3c3SSuma Hegde {1, 1, HSMP_GET}, 266*830fe3c3SSuma Hegde 267*830fe3c3SSuma Hegde /* 268*830fe3c3SSuma Hegde * HSMP_GET_XGMI_BANDWITH, num_args = 1, response_sz = 1 269*830fe3c3SSuma Hegde * input: args[0] = link id[15:8] + bw type[2:0] 270*830fe3c3SSuma Hegde * output: args[0] = xgmi bandwidth in Mbps[31:0] 271*830fe3c3SSuma Hegde */ 272*830fe3c3SSuma Hegde {1, 1, HSMP_GET}, 273*830fe3c3SSuma Hegde 274*830fe3c3SSuma Hegde /* 275*830fe3c3SSuma Hegde * HSMP_SET_GMI3_WIDTH, num_args = 1, response_sz = 0 276*830fe3c3SSuma Hegde * input: args[0] = min link width[15:8] + max link width[7:0] 277*830fe3c3SSuma Hegde */ 278*830fe3c3SSuma Hegde {1, 0, HSMP_SET}, 279*830fe3c3SSuma Hegde 280*830fe3c3SSuma Hegde /* 281*830fe3c3SSuma Hegde * HSMP_SET_PCI_RATE, num_args = 1, response_sz = 1 282*830fe3c3SSuma Hegde * input: args[0] = link rate control value 283*830fe3c3SSuma Hegde * output: args[0] = previous link rate control value 284*830fe3c3SSuma Hegde */ 285*830fe3c3SSuma Hegde {1, 1, HSMP_SET}, 286*830fe3c3SSuma Hegde 287*830fe3c3SSuma Hegde /* 288*830fe3c3SSuma Hegde * HSMP_SET_POWER_MODE, num_args = 1, response_sz = 0 289*830fe3c3SSuma Hegde * input: args[0] = power efficiency mode[2:0] 290*830fe3c3SSuma Hegde */ 291*830fe3c3SSuma Hegde {1, 0, HSMP_SET}, 292*830fe3c3SSuma Hegde 293*830fe3c3SSuma Hegde /* 294*830fe3c3SSuma Hegde * HSMP_SET_PSTATE_MAX_MIN, num_args = 1, response_sz = 0 295*830fe3c3SSuma Hegde * input: args[0] = min df pstate[15:8] + max df pstate[7:0] 296*830fe3c3SSuma Hegde */ 297*830fe3c3SSuma Hegde {1, 0, HSMP_SET}, 29891f410aaSSuma Hegde }; 29991f410aaSSuma Hegde 30091f410aaSSuma Hegde /* Reset to default packing */ 30191f410aaSSuma Hegde #pragma pack() 30291f410aaSSuma Hegde 30391f410aaSSuma Hegde /* Define unique ioctl command for hsmp msgs using generic _IOWR */ 30491f410aaSSuma Hegde #define HSMP_BASE_IOCTL_NR 0xF8 30591f410aaSSuma Hegde #define HSMP_IOCTL_CMD _IOWR(HSMP_BASE_IOCTL_NR, 0, struct hsmp_message) 30691f410aaSSuma Hegde 30791f410aaSSuma Hegde #endif /*_ASM_X86_AMD_HSMP_H_*/ 308