1 #ifndef _ASM_X86_PROCESSOR_H 2 #define _ASM_X86_PROCESSOR_H 3 4 #include <asm/processor-flags.h> 5 6 /* Forward declaration, a strange C thing */ 7 struct task_struct; 8 struct mm_struct; 9 10 #include <asm/vm86.h> 11 #include <asm/math_emu.h> 12 #include <asm/segment.h> 13 #include <asm/types.h> 14 #include <asm/sigcontext.h> 15 #include <asm/current.h> 16 #include <asm/cpufeature.h> 17 #include <asm/system.h> 18 #include <asm/page.h> 19 #include <asm/pgtable_types.h> 20 #include <asm/percpu.h> 21 #include <asm/msr.h> 22 #include <asm/desc_defs.h> 23 #include <asm/nops.h> 24 #include <asm/ds.h> 25 26 #include <linux/personality.h> 27 #include <linux/cpumask.h> 28 #include <linux/cache.h> 29 #include <linux/threads.h> 30 #include <linux/math64.h> 31 #include <linux/init.h> 32 33 #define HBP_NUM 4 34 /* 35 * Default implementation of macro that returns current 36 * instruction pointer ("program counter"). 37 */ 38 static inline void *current_text_addr(void) 39 { 40 void *pc; 41 42 asm volatile("mov $1f, %0; 1:":"=r" (pc)); 43 44 return pc; 45 } 46 47 #ifdef CONFIG_X86_VSMP 48 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 49 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 50 #else 51 # define ARCH_MIN_TASKALIGN 16 52 # define ARCH_MIN_MMSTRUCT_ALIGN 0 53 #endif 54 55 /* 56 * CPU type and hardware bug flags. Kept separately for each CPU. 57 * Members of this structure are referenced in head.S, so think twice 58 * before touching them. [mj] 59 */ 60 61 struct cpuinfo_x86 { 62 __u8 x86; /* CPU family */ 63 __u8 x86_vendor; /* CPU vendor */ 64 __u8 x86_model; 65 __u8 x86_mask; 66 #ifdef CONFIG_X86_32 67 char wp_works_ok; /* It doesn't on 386's */ 68 69 /* Problems on some 486Dx4's and old 386's: */ 70 char hlt_works_ok; 71 char hard_math; 72 char rfu; 73 char fdiv_bug; 74 char f00f_bug; 75 char coma_bug; 76 char pad0; 77 #else 78 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 79 int x86_tlbsize; 80 #endif 81 __u8 x86_virt_bits; 82 __u8 x86_phys_bits; 83 /* CPUID returned core id bits: */ 84 __u8 x86_coreid_bits; 85 /* Max extended CPUID function supported: */ 86 __u32 extended_cpuid_level; 87 /* Maximum supported CPUID level, -1=no CPUID: */ 88 int cpuid_level; 89 __u32 x86_capability[NCAPINTS]; 90 char x86_vendor_id[16]; 91 char x86_model_id[64]; 92 /* in KB - valid for CPUS which support this call: */ 93 int x86_cache_size; 94 int x86_cache_alignment; /* In bytes */ 95 int x86_power; 96 unsigned long loops_per_jiffy; 97 #ifdef CONFIG_SMP 98 /* cpus sharing the last level cache: */ 99 cpumask_var_t llc_shared_map; 100 #endif 101 /* cpuid returned max cores value: */ 102 u16 x86_max_cores; 103 u16 apicid; 104 u16 initial_apicid; 105 u16 x86_clflush_size; 106 #ifdef CONFIG_SMP 107 /* number of cores as seen by the OS: */ 108 u16 booted_cores; 109 /* Physical processor id: */ 110 u16 phys_proc_id; 111 /* Core id: */ 112 u16 cpu_core_id; 113 /* Index into per_cpu list: */ 114 u16 cpu_index; 115 #endif 116 unsigned int x86_hyper_vendor; 117 /* The layout of this field is hypervisor specific */ 118 unsigned int x86_hyper_features; 119 } __attribute__((__aligned__(SMP_CACHE_BYTES))); 120 121 #define X86_VENDOR_INTEL 0 122 #define X86_VENDOR_CYRIX 1 123 #define X86_VENDOR_AMD 2 124 #define X86_VENDOR_UMC 3 125 #define X86_VENDOR_CENTAUR 5 126 #define X86_VENDOR_TRANSMETA 7 127 #define X86_VENDOR_NSC 8 128 #define X86_VENDOR_NUM 9 129 130 #define X86_VENDOR_UNKNOWN 0xff 131 132 #define X86_HYPER_VENDOR_NONE 0 133 #define X86_HYPER_VENDOR_VMWARE 1 134 #define X86_HYPER_VENDOR_MSFT 2 135 136 /* 137 * capabilities of CPUs 138 */ 139 extern struct cpuinfo_x86 boot_cpu_data; 140 extern struct cpuinfo_x86 new_cpu_data; 141 142 extern struct tss_struct doublefault_tss; 143 extern __u32 cpu_caps_cleared[NCAPINTS]; 144 extern __u32 cpu_caps_set[NCAPINTS]; 145 146 #ifdef CONFIG_SMP 147 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 148 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 149 #define current_cpu_data __get_cpu_var(cpu_info) 150 #else 151 #define cpu_data(cpu) boot_cpu_data 152 #define current_cpu_data boot_cpu_data 153 #endif 154 155 extern const struct seq_operations cpuinfo_op; 156 157 static inline int hlt_works(int cpu) 158 { 159 #ifdef CONFIG_X86_32 160 return cpu_data(cpu).hlt_works_ok; 161 #else 162 return 1; 163 #endif 164 } 165 166 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 167 168 extern void cpu_detect(struct cpuinfo_x86 *c); 169 170 extern struct pt_regs *idle_regs(struct pt_regs *); 171 172 extern void early_cpu_init(void); 173 extern void identify_boot_cpu(void); 174 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 175 extern void print_cpu_info(struct cpuinfo_x86 *); 176 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 177 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 178 extern unsigned short num_cache_leaves; 179 180 extern void detect_extended_topology(struct cpuinfo_x86 *c); 181 extern void detect_ht(struct cpuinfo_x86 *c); 182 183 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 184 unsigned int *ecx, unsigned int *edx) 185 { 186 /* ecx is often an input as well as an output. */ 187 asm volatile("cpuid" 188 : "=a" (*eax), 189 "=b" (*ebx), 190 "=c" (*ecx), 191 "=d" (*edx) 192 : "0" (*eax), "2" (*ecx)); 193 } 194 195 static inline void load_cr3(pgd_t *pgdir) 196 { 197 write_cr3(__pa(pgdir)); 198 } 199 200 #ifdef CONFIG_X86_32 201 /* This is the TSS defined by the hardware. */ 202 struct x86_hw_tss { 203 unsigned short back_link, __blh; 204 unsigned long sp0; 205 unsigned short ss0, __ss0h; 206 unsigned long sp1; 207 /* ss1 caches MSR_IA32_SYSENTER_CS: */ 208 unsigned short ss1, __ss1h; 209 unsigned long sp2; 210 unsigned short ss2, __ss2h; 211 unsigned long __cr3; 212 unsigned long ip; 213 unsigned long flags; 214 unsigned long ax; 215 unsigned long cx; 216 unsigned long dx; 217 unsigned long bx; 218 unsigned long sp; 219 unsigned long bp; 220 unsigned long si; 221 unsigned long di; 222 unsigned short es, __esh; 223 unsigned short cs, __csh; 224 unsigned short ss, __ssh; 225 unsigned short ds, __dsh; 226 unsigned short fs, __fsh; 227 unsigned short gs, __gsh; 228 unsigned short ldt, __ldth; 229 unsigned short trace; 230 unsigned short io_bitmap_base; 231 232 } __attribute__((packed)); 233 #else 234 struct x86_hw_tss { 235 u32 reserved1; 236 u64 sp0; 237 u64 sp1; 238 u64 sp2; 239 u64 reserved2; 240 u64 ist[7]; 241 u32 reserved3; 242 u32 reserved4; 243 u16 reserved5; 244 u16 io_bitmap_base; 245 246 } __attribute__((packed)) ____cacheline_aligned; 247 #endif 248 249 /* 250 * IO-bitmap sizes: 251 */ 252 #define IO_BITMAP_BITS 65536 253 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 254 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 255 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) 256 #define INVALID_IO_BITMAP_OFFSET 0x8000 257 258 struct tss_struct { 259 /* 260 * The hardware state: 261 */ 262 struct x86_hw_tss x86_tss; 263 264 /* 265 * The extra 1 is there because the CPU will access an 266 * additional byte beyond the end of the IO permission 267 * bitmap. The extra byte must be all 1 bits, and must 268 * be within the limit. 269 */ 270 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 271 272 /* 273 * .. and then another 0x100 bytes for the emergency kernel stack: 274 */ 275 unsigned long stack[64]; 276 277 } ____cacheline_aligned; 278 279 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss); 280 281 /* 282 * Save the original ist values for checking stack pointers during debugging 283 */ 284 struct orig_ist { 285 unsigned long ist[7]; 286 }; 287 288 #define MXCSR_DEFAULT 0x1f80 289 290 struct i387_fsave_struct { 291 u32 cwd; /* FPU Control Word */ 292 u32 swd; /* FPU Status Word */ 293 u32 twd; /* FPU Tag Word */ 294 u32 fip; /* FPU IP Offset */ 295 u32 fcs; /* FPU IP Selector */ 296 u32 foo; /* FPU Operand Pointer Offset */ 297 u32 fos; /* FPU Operand Pointer Selector */ 298 299 /* 8*10 bytes for each FP-reg = 80 bytes: */ 300 u32 st_space[20]; 301 302 /* Software status information [not touched by FSAVE ]: */ 303 u32 status; 304 }; 305 306 struct i387_fxsave_struct { 307 u16 cwd; /* Control Word */ 308 u16 swd; /* Status Word */ 309 u16 twd; /* Tag Word */ 310 u16 fop; /* Last Instruction Opcode */ 311 union { 312 struct { 313 u64 rip; /* Instruction Pointer */ 314 u64 rdp; /* Data Pointer */ 315 }; 316 struct { 317 u32 fip; /* FPU IP Offset */ 318 u32 fcs; /* FPU IP Selector */ 319 u32 foo; /* FPU Operand Offset */ 320 u32 fos; /* FPU Operand Selector */ 321 }; 322 }; 323 u32 mxcsr; /* MXCSR Register State */ 324 u32 mxcsr_mask; /* MXCSR Mask */ 325 326 /* 8*16 bytes for each FP-reg = 128 bytes: */ 327 u32 st_space[32]; 328 329 /* 16*16 bytes for each XMM-reg = 256 bytes: */ 330 u32 xmm_space[64]; 331 332 u32 padding[12]; 333 334 union { 335 u32 padding1[12]; 336 u32 sw_reserved[12]; 337 }; 338 339 } __attribute__((aligned(16))); 340 341 struct i387_soft_struct { 342 u32 cwd; 343 u32 swd; 344 u32 twd; 345 u32 fip; 346 u32 fcs; 347 u32 foo; 348 u32 fos; 349 /* 8*10 bytes for each FP-reg = 80 bytes: */ 350 u32 st_space[20]; 351 u8 ftop; 352 u8 changed; 353 u8 lookahead; 354 u8 no_update; 355 u8 rm; 356 u8 alimit; 357 struct math_emu_info *info; 358 u32 entry_eip; 359 }; 360 361 struct ymmh_struct { 362 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */ 363 u32 ymmh_space[64]; 364 }; 365 366 struct xsave_hdr_struct { 367 u64 xstate_bv; 368 u64 reserved1[2]; 369 u64 reserved2[5]; 370 } __attribute__((packed)); 371 372 struct xsave_struct { 373 struct i387_fxsave_struct i387; 374 struct xsave_hdr_struct xsave_hdr; 375 struct ymmh_struct ymmh; 376 /* new processor state extensions will go here */ 377 } __attribute__ ((packed, aligned (64))); 378 379 union thread_xstate { 380 struct i387_fsave_struct fsave; 381 struct i387_fxsave_struct fxsave; 382 struct i387_soft_struct soft; 383 struct xsave_struct xsave; 384 }; 385 386 #ifdef CONFIG_X86_64 387 DECLARE_PER_CPU(struct orig_ist, orig_ist); 388 389 union irq_stack_union { 390 char irq_stack[IRQ_STACK_SIZE]; 391 /* 392 * GCC hardcodes the stack canary as %gs:40. Since the 393 * irq_stack is the object at %gs:0, we reserve the bottom 394 * 48 bytes of the irq stack for the canary. 395 */ 396 struct { 397 char gs_base[40]; 398 unsigned long stack_canary; 399 }; 400 }; 401 402 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union); 403 DECLARE_INIT_PER_CPU(irq_stack_union); 404 405 DECLARE_PER_CPU(char *, irq_stack_ptr); 406 DECLARE_PER_CPU(unsigned int, irq_count); 407 extern unsigned long kernel_eflags; 408 extern asmlinkage void ignore_sysret(void); 409 #else /* X86_64 */ 410 #ifdef CONFIG_CC_STACKPROTECTOR 411 /* 412 * Make sure stack canary segment base is cached-aligned: 413 * "For Intel Atom processors, avoid non zero segment base address 414 * that is not aligned to cache line boundary at all cost." 415 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 416 */ 417 struct stack_canary { 418 char __pad[20]; /* canary at %gs:20 */ 419 unsigned long canary; 420 }; 421 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 422 #endif 423 #endif /* X86_64 */ 424 425 extern unsigned int xstate_size; 426 extern void free_thread_xstate(struct task_struct *); 427 extern struct kmem_cache *task_xstate_cachep; 428 429 struct perf_event; 430 431 struct thread_struct { 432 /* Cached TLS descriptors: */ 433 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 434 unsigned long sp0; 435 unsigned long sp; 436 #ifdef CONFIG_X86_32 437 unsigned long sysenter_cs; 438 #else 439 unsigned long usersp; /* Copy from PDA */ 440 unsigned short es; 441 unsigned short ds; 442 unsigned short fsindex; 443 unsigned short gsindex; 444 #endif 445 #ifdef CONFIG_X86_32 446 unsigned long ip; 447 #endif 448 #ifdef CONFIG_X86_64 449 unsigned long fs; 450 #endif 451 unsigned long gs; 452 /* Save middle states of ptrace breakpoints */ 453 struct perf_event *ptrace_bps[HBP_NUM]; 454 /* Debug status used for traps, single steps, etc... */ 455 unsigned long debugreg6; 456 /* Keep track of the exact dr7 value set by the user */ 457 unsigned long ptrace_dr7; 458 /* Fault info: */ 459 unsigned long cr2; 460 unsigned long trap_no; 461 unsigned long error_code; 462 /* floating point and extended processor state */ 463 union thread_xstate *xstate; 464 #ifdef CONFIG_X86_32 465 /* Virtual 86 mode info */ 466 struct vm86_struct __user *vm86_info; 467 unsigned long screen_bitmap; 468 unsigned long v86flags; 469 unsigned long v86mask; 470 unsigned long saved_sp0; 471 unsigned int saved_fs; 472 unsigned int saved_gs; 473 #endif 474 /* IO permissions: */ 475 unsigned long *io_bitmap_ptr; 476 unsigned long iopl; 477 /* Max allowed port in the bitmap, in bytes: */ 478 unsigned io_bitmap_max; 479 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */ 480 unsigned long debugctlmsr; 481 /* Debug Store context; see asm/ds.h */ 482 struct ds_context *ds_ctx; 483 }; 484 485 static inline unsigned long native_get_debugreg(int regno) 486 { 487 unsigned long val = 0; /* Damn you, gcc! */ 488 489 switch (regno) { 490 case 0: 491 asm("mov %%db0, %0" :"=r" (val)); 492 break; 493 case 1: 494 asm("mov %%db1, %0" :"=r" (val)); 495 break; 496 case 2: 497 asm("mov %%db2, %0" :"=r" (val)); 498 break; 499 case 3: 500 asm("mov %%db3, %0" :"=r" (val)); 501 break; 502 case 6: 503 asm("mov %%db6, %0" :"=r" (val)); 504 break; 505 case 7: 506 asm("mov %%db7, %0" :"=r" (val)); 507 break; 508 default: 509 BUG(); 510 } 511 return val; 512 } 513 514 static inline void native_set_debugreg(int regno, unsigned long value) 515 { 516 switch (regno) { 517 case 0: 518 asm("mov %0, %%db0" ::"r" (value)); 519 break; 520 case 1: 521 asm("mov %0, %%db1" ::"r" (value)); 522 break; 523 case 2: 524 asm("mov %0, %%db2" ::"r" (value)); 525 break; 526 case 3: 527 asm("mov %0, %%db3" ::"r" (value)); 528 break; 529 case 6: 530 asm("mov %0, %%db6" ::"r" (value)); 531 break; 532 case 7: 533 asm("mov %0, %%db7" ::"r" (value)); 534 break; 535 default: 536 BUG(); 537 } 538 } 539 540 /* 541 * Set IOPL bits in EFLAGS from given mask 542 */ 543 static inline void native_set_iopl_mask(unsigned mask) 544 { 545 #ifdef CONFIG_X86_32 546 unsigned int reg; 547 548 asm volatile ("pushfl;" 549 "popl %0;" 550 "andl %1, %0;" 551 "orl %2, %0;" 552 "pushl %0;" 553 "popfl" 554 : "=&r" (reg) 555 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 556 #endif 557 } 558 559 static inline void 560 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) 561 { 562 tss->x86_tss.sp0 = thread->sp0; 563 #ifdef CONFIG_X86_32 564 /* Only happens when SEP is enabled, no need to test "SEP"arately: */ 565 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 566 tss->x86_tss.ss1 = thread->sysenter_cs; 567 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 568 } 569 #endif 570 } 571 572 static inline void native_swapgs(void) 573 { 574 #ifdef CONFIG_X86_64 575 asm volatile("swapgs" ::: "memory"); 576 #endif 577 } 578 579 #ifdef CONFIG_PARAVIRT 580 #include <asm/paravirt.h> 581 #else 582 #define __cpuid native_cpuid 583 #define paravirt_enabled() 0 584 585 /* 586 * These special macros can be used to get or set a debugging register 587 */ 588 #define get_debugreg(var, register) \ 589 (var) = native_get_debugreg(register) 590 #define set_debugreg(value, register) \ 591 native_set_debugreg(register, value) 592 593 static inline void load_sp0(struct tss_struct *tss, 594 struct thread_struct *thread) 595 { 596 native_load_sp0(tss, thread); 597 } 598 599 #define set_iopl_mask native_set_iopl_mask 600 #endif /* CONFIG_PARAVIRT */ 601 602 /* 603 * Save the cr4 feature set we're using (ie 604 * Pentium 4MB enable and PPro Global page 605 * enable), so that any CPU's that boot up 606 * after us can get the correct flags. 607 */ 608 extern unsigned long mmu_cr4_features; 609 610 static inline void set_in_cr4(unsigned long mask) 611 { 612 unsigned cr4; 613 614 mmu_cr4_features |= mask; 615 cr4 = read_cr4(); 616 cr4 |= mask; 617 write_cr4(cr4); 618 } 619 620 static inline void clear_in_cr4(unsigned long mask) 621 { 622 unsigned cr4; 623 624 mmu_cr4_features &= ~mask; 625 cr4 = read_cr4(); 626 cr4 &= ~mask; 627 write_cr4(cr4); 628 } 629 630 typedef struct { 631 unsigned long seg; 632 } mm_segment_t; 633 634 635 /* 636 * create a kernel thread without removing it from tasklists 637 */ 638 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); 639 640 /* Free all resources held by a thread. */ 641 extern void release_thread(struct task_struct *); 642 643 /* Prepare to copy thread state - unlazy all lazy state */ 644 extern void prepare_to_copy(struct task_struct *tsk); 645 646 unsigned long get_wchan(struct task_struct *p); 647 648 /* 649 * Generic CPUID function 650 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 651 * resulting in stale register contents being returned. 652 */ 653 static inline void cpuid(unsigned int op, 654 unsigned int *eax, unsigned int *ebx, 655 unsigned int *ecx, unsigned int *edx) 656 { 657 *eax = op; 658 *ecx = 0; 659 __cpuid(eax, ebx, ecx, edx); 660 } 661 662 /* Some CPUID calls want 'count' to be placed in ecx */ 663 static inline void cpuid_count(unsigned int op, int count, 664 unsigned int *eax, unsigned int *ebx, 665 unsigned int *ecx, unsigned int *edx) 666 { 667 *eax = op; 668 *ecx = count; 669 __cpuid(eax, ebx, ecx, edx); 670 } 671 672 /* 673 * CPUID functions returning a single datum 674 */ 675 static inline unsigned int cpuid_eax(unsigned int op) 676 { 677 unsigned int eax, ebx, ecx, edx; 678 679 cpuid(op, &eax, &ebx, &ecx, &edx); 680 681 return eax; 682 } 683 684 static inline unsigned int cpuid_ebx(unsigned int op) 685 { 686 unsigned int eax, ebx, ecx, edx; 687 688 cpuid(op, &eax, &ebx, &ecx, &edx); 689 690 return ebx; 691 } 692 693 static inline unsigned int cpuid_ecx(unsigned int op) 694 { 695 unsigned int eax, ebx, ecx, edx; 696 697 cpuid(op, &eax, &ebx, &ecx, &edx); 698 699 return ecx; 700 } 701 702 static inline unsigned int cpuid_edx(unsigned int op) 703 { 704 unsigned int eax, ebx, ecx, edx; 705 706 cpuid(op, &eax, &ebx, &ecx, &edx); 707 708 return edx; 709 } 710 711 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 712 static inline void rep_nop(void) 713 { 714 asm volatile("rep; nop" ::: "memory"); 715 } 716 717 static inline void cpu_relax(void) 718 { 719 rep_nop(); 720 } 721 722 /* Stop speculative execution and prefetching of modified code. */ 723 static inline void sync_core(void) 724 { 725 int tmp; 726 727 #if defined(CONFIG_M386) || defined(CONFIG_M486) 728 if (boot_cpu_data.x86 < 5) 729 /* There is no speculative execution. 730 * jmp is a barrier to prefetching. */ 731 asm volatile("jmp 1f\n1:\n" ::: "memory"); 732 else 733 #endif 734 /* cpuid is a barrier to speculative execution. 735 * Prefetched instructions are automatically 736 * invalidated when modified. */ 737 asm volatile("cpuid" : "=a" (tmp) : "0" (1) 738 : "ebx", "ecx", "edx", "memory"); 739 } 740 741 static inline void __monitor(const void *eax, unsigned long ecx, 742 unsigned long edx) 743 { 744 /* "monitor %eax, %ecx, %edx;" */ 745 asm volatile(".byte 0x0f, 0x01, 0xc8;" 746 :: "a" (eax), "c" (ecx), "d"(edx)); 747 } 748 749 static inline void __mwait(unsigned long eax, unsigned long ecx) 750 { 751 /* "mwait %eax, %ecx;" */ 752 asm volatile(".byte 0x0f, 0x01, 0xc9;" 753 :: "a" (eax), "c" (ecx)); 754 } 755 756 static inline void __sti_mwait(unsigned long eax, unsigned long ecx) 757 { 758 trace_hardirqs_on(); 759 /* "mwait %eax, %ecx;" */ 760 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;" 761 :: "a" (eax), "c" (ecx)); 762 } 763 764 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx); 765 766 extern void select_idle_routine(const struct cpuinfo_x86 *c); 767 extern void init_c1e_mask(void); 768 769 extern unsigned long boot_option_idle_override; 770 extern unsigned long idle_halt; 771 extern unsigned long idle_nomwait; 772 773 /* 774 * on systems with caches, caches must be flashed as the absolute 775 * last instruction before going into a suspended halt. Otherwise, 776 * dirty data can linger in the cache and become stale on resume, 777 * leading to strange errors. 778 * 779 * perform a variety of operations to guarantee that the compiler 780 * will not reorder instructions. wbinvd itself is serializing 781 * so the processor will not reorder. 782 * 783 * Systems without cache can just go into halt. 784 */ 785 static inline void wbinvd_halt(void) 786 { 787 mb(); 788 /* check for clflush to determine if wbinvd is legal */ 789 if (cpu_has_clflush) 790 asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory"); 791 else 792 while (1) 793 halt(); 794 } 795 796 extern void enable_sep_cpu(void); 797 extern int sysenter_setup(void); 798 799 /* Defined in head.S */ 800 extern struct desc_ptr early_gdt_descr; 801 802 extern void cpu_set_gdt(int); 803 extern void switch_to_new_gdt(int); 804 extern void load_percpu_segment(int); 805 extern void cpu_init(void); 806 807 static inline unsigned long get_debugctlmsr(void) 808 { 809 unsigned long debugctlmsr = 0; 810 811 #ifndef CONFIG_X86_DEBUGCTLMSR 812 if (boot_cpu_data.x86 < 6) 813 return 0; 814 #endif 815 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 816 817 return debugctlmsr; 818 } 819 820 static inline unsigned long get_debugctlmsr_on_cpu(int cpu) 821 { 822 u64 debugctlmsr = 0; 823 u32 val1, val2; 824 825 #ifndef CONFIG_X86_DEBUGCTLMSR 826 if (boot_cpu_data.x86 < 6) 827 return 0; 828 #endif 829 rdmsr_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, &val1, &val2); 830 debugctlmsr = val1 | ((u64)val2 << 32); 831 832 return debugctlmsr; 833 } 834 835 static inline void update_debugctlmsr(unsigned long debugctlmsr) 836 { 837 #ifndef CONFIG_X86_DEBUGCTLMSR 838 if (boot_cpu_data.x86 < 6) 839 return; 840 #endif 841 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 842 } 843 844 static inline void update_debugctlmsr_on_cpu(int cpu, 845 unsigned long debugctlmsr) 846 { 847 #ifndef CONFIG_X86_DEBUGCTLMSR 848 if (boot_cpu_data.x86 < 6) 849 return; 850 #endif 851 wrmsr_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, 852 (u32)((u64)debugctlmsr), 853 (u32)((u64)debugctlmsr >> 32)); 854 } 855 856 /* 857 * from system description table in BIOS. Mostly for MCA use, but 858 * others may find it useful: 859 */ 860 extern unsigned int machine_id; 861 extern unsigned int machine_submodel_id; 862 extern unsigned int BIOS_revision; 863 864 /* Boot loader type from the setup header: */ 865 extern int bootloader_type; 866 extern int bootloader_version; 867 868 extern char ignore_fpu_irq; 869 870 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 871 #define ARCH_HAS_PREFETCHW 872 #define ARCH_HAS_SPINLOCK_PREFETCH 873 874 #ifdef CONFIG_X86_32 875 # define BASE_PREFETCH ASM_NOP4 876 # define ARCH_HAS_PREFETCH 877 #else 878 # define BASE_PREFETCH "prefetcht0 (%1)" 879 #endif 880 881 /* 882 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 883 * 884 * It's not worth to care about 3dnow prefetches for the K6 885 * because they are microcoded there and very slow. 886 */ 887 static inline void prefetch(const void *x) 888 { 889 alternative_input(BASE_PREFETCH, 890 "prefetchnta (%1)", 891 X86_FEATURE_XMM, 892 "r" (x)); 893 } 894 895 /* 896 * 3dnow prefetch to get an exclusive cache line. 897 * Useful for spinlocks to avoid one state transition in the 898 * cache coherency protocol: 899 */ 900 static inline void prefetchw(const void *x) 901 { 902 alternative_input(BASE_PREFETCH, 903 "prefetchw (%1)", 904 X86_FEATURE_3DNOW, 905 "r" (x)); 906 } 907 908 static inline void spin_lock_prefetch(const void *x) 909 { 910 prefetchw(x); 911 } 912 913 #ifdef CONFIG_X86_32 914 /* 915 * User space process size: 3GB (default). 916 */ 917 #define TASK_SIZE PAGE_OFFSET 918 #define TASK_SIZE_MAX TASK_SIZE 919 #define STACK_TOP TASK_SIZE 920 #define STACK_TOP_MAX STACK_TOP 921 922 #define INIT_THREAD { \ 923 .sp0 = sizeof(init_stack) + (long)&init_stack, \ 924 .vm86_info = NULL, \ 925 .sysenter_cs = __KERNEL_CS, \ 926 .io_bitmap_ptr = NULL, \ 927 } 928 929 /* 930 * Note that the .io_bitmap member must be extra-big. This is because 931 * the CPU will access an additional byte beyond the end of the IO 932 * permission bitmap. The extra byte must be all 1 bits, and must 933 * be within the limit. 934 */ 935 #define INIT_TSS { \ 936 .x86_tss = { \ 937 .sp0 = sizeof(init_stack) + (long)&init_stack, \ 938 .ss0 = __KERNEL_DS, \ 939 .ss1 = __KERNEL_CS, \ 940 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \ 941 }, \ 942 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \ 943 } 944 945 extern unsigned long thread_saved_pc(struct task_struct *tsk); 946 947 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long)) 948 #define KSTK_TOP(info) \ 949 ({ \ 950 unsigned long *__ptr = (unsigned long *)(info); \ 951 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \ 952 }) 953 954 /* 955 * The below -8 is to reserve 8 bytes on top of the ring0 stack. 956 * This is necessary to guarantee that the entire "struct pt_regs" 957 * is accessable even if the CPU haven't stored the SS/ESP registers 958 * on the stack (interrupt gate does not save these registers 959 * when switching to the same priv ring). 960 * Therefore beware: accessing the ss/esp fields of the 961 * "struct pt_regs" is possible, but they may contain the 962 * completely wrong values. 963 */ 964 #define task_pt_regs(task) \ 965 ({ \ 966 struct pt_regs *__regs__; \ 967 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \ 968 __regs__ - 1; \ 969 }) 970 971 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 972 973 #else 974 /* 975 * User space process size. 47bits minus one guard page. 976 */ 977 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) 978 979 /* This decides where the kernel will search for a free chunk of vm 980 * space during mmap's. 981 */ 982 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 983 0xc0000000 : 0xFFFFe000) 984 985 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \ 986 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 987 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \ 988 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 989 990 #define STACK_TOP TASK_SIZE 991 #define STACK_TOP_MAX TASK_SIZE_MAX 992 993 #define INIT_THREAD { \ 994 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ 995 } 996 997 #define INIT_TSS { \ 998 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ 999 } 1000 1001 /* 1002 * Return saved PC of a blocked thread. 1003 * What is this good for? it will be always the scheduler or ret_from_fork. 1004 */ 1005 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8)) 1006 1007 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 1008 extern unsigned long KSTK_ESP(struct task_struct *task); 1009 #endif /* CONFIG_X86_64 */ 1010 1011 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 1012 unsigned long new_sp); 1013 1014 /* 1015 * This decides where the kernel will search for a free chunk of vm 1016 * space during mmap's. 1017 */ 1018 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 1019 1020 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 1021 1022 /* Get/set a process' ability to use the timestamp counter instruction */ 1023 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 1024 #define SET_TSC_CTL(val) set_tsc_mode((val)) 1025 1026 extern int get_tsc_mode(unsigned long adr); 1027 extern int set_tsc_mode(unsigned int val); 1028 1029 extern int amd_get_nb_id(int cpu); 1030 1031 struct aperfmperf { 1032 u64 aperf, mperf; 1033 }; 1034 1035 static inline void get_aperfmperf(struct aperfmperf *am) 1036 { 1037 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF)); 1038 1039 rdmsrl(MSR_IA32_APERF, am->aperf); 1040 rdmsrl(MSR_IA32_MPERF, am->mperf); 1041 } 1042 1043 #define APERFMPERF_SHIFT 10 1044 1045 static inline 1046 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old, 1047 struct aperfmperf *new) 1048 { 1049 u64 aperf = new->aperf - old->aperf; 1050 u64 mperf = new->mperf - old->mperf; 1051 unsigned long ratio = aperf; 1052 1053 mperf >>= APERFMPERF_SHIFT; 1054 if (mperf) 1055 ratio = div64_u64(aperf, mperf); 1056 1057 return ratio; 1058 } 1059 1060 #endif /* _ASM_X86_PROCESSOR_H */ 1061