1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 21965aae3SH. Peter Anvin #ifndef _ASM_X86_MICROCODE_H 31965aae3SH. Peter Anvin #define _ASM_X86_MICROCODE_H 4bb898558SAl Viro 5bb898558SAl Viro struct cpu_signature { 6bb898558SAl Viro unsigned int sig; 7bb898558SAl Viro unsigned int pf; 8bb898558SAl Viro unsigned int rev; 9bb898558SAl Viro }; 10bb898558SAl Viro 11bb898558SAl Viro struct ucode_cpu_info { 12bb898558SAl Viro struct cpu_signature cpu_sig; 13bb898558SAl Viro void *mc; 14bb898558SAl Viro }; 1558ce8d6dSBorislav Petkov 16fe055896SBorislav Petkov #ifdef CONFIG_MICROCODE 17*d02a0efdSThomas Gleixner void load_ucode_bsp(void); 18*d02a0efdSThomas Gleixner void load_ucode_ap(void); 19f9e14dbbSBorislav Petkov void microcode_bsp_resume(void); 20a8ebf6d1SFenghua Yu #else load_ucode_bsp(void)21*d02a0efdSThomas Gleixnerstatic inline void load_ucode_bsp(void) { } load_ucode_ap(void)22148f9bb8SPaul Gortmakerstatic inline void load_ucode_ap(void) { } microcode_bsp_resume(void)23f9e14dbbSBorislav Petkovstatic inline void microcode_bsp_resume(void) { } 24a8ebf6d1SFenghua Yu #endif 255f9c01aaSBorislav Petkov 26*d02a0efdSThomas Gleixner #ifdef CONFIG_CPU_SUP_INTEL 27*d02a0efdSThomas Gleixner /* Intel specific microcode defines. Public for IFS */ 28*d02a0efdSThomas Gleixner struct microcode_header_intel { 29*d02a0efdSThomas Gleixner unsigned int hdrver; 30*d02a0efdSThomas Gleixner unsigned int rev; 31*d02a0efdSThomas Gleixner unsigned int date; 32*d02a0efdSThomas Gleixner unsigned int sig; 33*d02a0efdSThomas Gleixner unsigned int cksum; 34*d02a0efdSThomas Gleixner unsigned int ldrver; 35*d02a0efdSThomas Gleixner unsigned int pf; 36*d02a0efdSThomas Gleixner unsigned int datasize; 37*d02a0efdSThomas Gleixner unsigned int totalsize; 38*d02a0efdSThomas Gleixner unsigned int metasize; 39*d02a0efdSThomas Gleixner unsigned int reserved[2]; 40*d02a0efdSThomas Gleixner }; 41*d02a0efdSThomas Gleixner 42*d02a0efdSThomas Gleixner struct microcode_intel { 43*d02a0efdSThomas Gleixner struct microcode_header_intel hdr; 44*d02a0efdSThomas Gleixner unsigned int bits[]; 45*d02a0efdSThomas Gleixner }; 46*d02a0efdSThomas Gleixner 47*d02a0efdSThomas Gleixner #define DEFAULT_UCODE_DATASIZE (2000) 48*d02a0efdSThomas Gleixner #define MC_HEADER_SIZE (sizeof(struct microcode_header_intel)) 49*d02a0efdSThomas Gleixner #define MC_HEADER_TYPE_MICROCODE 1 50*d02a0efdSThomas Gleixner #define MC_HEADER_TYPE_IFS 2 51*d02a0efdSThomas Gleixner intel_microcode_get_datasize(struct microcode_header_intel * hdr)52*d02a0efdSThomas Gleixnerstatic inline int intel_microcode_get_datasize(struct microcode_header_intel *hdr) 53*d02a0efdSThomas Gleixner { 54*d02a0efdSThomas Gleixner return hdr->datasize ? : DEFAULT_UCODE_DATASIZE; 55*d02a0efdSThomas Gleixner } 56*d02a0efdSThomas Gleixner intel_get_microcode_revision(void)57*d02a0efdSThomas Gleixnerstatic inline u32 intel_get_microcode_revision(void) 58*d02a0efdSThomas Gleixner { 59*d02a0efdSThomas Gleixner u32 rev, dummy; 60*d02a0efdSThomas Gleixner 61*d02a0efdSThomas Gleixner native_wrmsrl(MSR_IA32_UCODE_REV, 0); 62*d02a0efdSThomas Gleixner 63*d02a0efdSThomas Gleixner /* As documented in the SDM: Do a CPUID 1 here */ 64*d02a0efdSThomas Gleixner native_cpuid_eax(1); 65*d02a0efdSThomas Gleixner 66*d02a0efdSThomas Gleixner /* get the current revision from MSR 0x8B */ 67*d02a0efdSThomas Gleixner native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev); 68*d02a0efdSThomas Gleixner 69*d02a0efdSThomas Gleixner return rev; 70*d02a0efdSThomas Gleixner } 71*d02a0efdSThomas Gleixner 72*d02a0efdSThomas Gleixner void show_ucode_info_early(void); 73*d02a0efdSThomas Gleixner 74*d02a0efdSThomas Gleixner #else /* CONFIG_CPU_SUP_INTEL */ show_ucode_info_early(void)75*d02a0efdSThomas Gleixnerstatic inline void show_ucode_info_early(void) { } 76*d02a0efdSThomas Gleixner #endif /* !CONFIG_CPU_SUP_INTEL */ 77*d02a0efdSThomas Gleixner 781965aae3SH. Peter Anvin #endif /* _ASM_X86_MICROCODE_H */ 79