1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 21965aae3SH. Peter Anvin #ifndef _ASM_X86_I8259_H 31965aae3SH. Peter Anvin #define _ASM_X86_I8259_H 4bb898558SAl Viro 5bb898558SAl Viro #include <linux/delay.h> 6bb898558SAl Viro 7bb898558SAl Viro extern unsigned int cached_irq_mask; 8bb898558SAl Viro 9bb898558SAl Viro #define __byte(x, y) (((unsigned char *)&(y))[x]) 10bb898558SAl Viro #define cached_master_mask (__byte(0, cached_irq_mask)) 11bb898558SAl Viro #define cached_slave_mask (__byte(1, cached_irq_mask)) 12bb898558SAl Viro 13bb898558SAl Viro /* i8259A PIC registers */ 14bb898558SAl Viro #define PIC_MASTER_CMD 0x20 15bb898558SAl Viro #define PIC_MASTER_IMR 0x21 16bb898558SAl Viro #define PIC_MASTER_ISR PIC_MASTER_CMD 17bb898558SAl Viro #define PIC_MASTER_POLL PIC_MASTER_ISR 18bb898558SAl Viro #define PIC_MASTER_OCW3 PIC_MASTER_ISR 19bb898558SAl Viro #define PIC_SLAVE_CMD 0xa0 20bb898558SAl Viro #define PIC_SLAVE_IMR 0xa1 21bb898558SAl Viro 22bb898558SAl Viro /* i8259A PIC related value */ 23bb898558SAl Viro #define PIC_CASCADE_IR 2 24bb898558SAl Viro #define MASTER_ICW4_DEFAULT 0x01 25bb898558SAl Viro #define SLAVE_ICW4_DEFAULT 0x01 26bb898558SAl Viro #define PIC_ICW4_AEOI 2 27bb898558SAl Viro 285619c280SThomas Gleixner extern raw_spinlock_t i8259A_lock; 29bb898558SAl Viro 30bb898558SAl Viro /* the PIC may need a careful delay on some platforms, hence specific calls */ 31bb898558SAl Viro static inline unsigned char inb_pic(unsigned int port) 32bb898558SAl Viro { 33bb898558SAl Viro unsigned char value = inb(port); 34bb898558SAl Viro 35bb898558SAl Viro /* 36bb898558SAl Viro * delay for some accesses to PIC on motherboard or in chipset 37bb898558SAl Viro * must be at least one microsecond, so be safe here: 38bb898558SAl Viro */ 39bb898558SAl Viro udelay(2); 40bb898558SAl Viro 41bb898558SAl Viro return value; 42bb898558SAl Viro } 43bb898558SAl Viro 44bb898558SAl Viro static inline void outb_pic(unsigned char value, unsigned int port) 45bb898558SAl Viro { 46bb898558SAl Viro outb(value, port); 47bb898558SAl Viro /* 48bb898558SAl Viro * delay for some accesses to PIC on motherboard or in chipset 49bb898558SAl Viro * must be at least one microsecond, so be safe here: 50bb898558SAl Viro */ 51bb898558SAl Viro udelay(2); 52bb898558SAl Viro } 53bb898558SAl Viro 54bb898558SAl Viro extern struct irq_chip i8259A_chip; 55bb898558SAl Viro 56ef354866SJacob Pan struct legacy_pic { 57ef354866SJacob Pan int nr_legacy_irqs; 58ef354866SJacob Pan struct irq_chip *chip; 594305df94SThomas Gleixner void (*mask)(unsigned int irq); 604305df94SThomas Gleixner void (*unmask)(unsigned int irq); 61ef354866SJacob Pan void (*mask_all)(void); 62ef354866SJacob Pan void (*restore_mask)(void); 63ef354866SJacob Pan void (*init)(int auto_eoi); 648c058b0bSVitaly Kuznetsov int (*probe)(void); 65ef354866SJacob Pan int (*irq_pending)(unsigned int irq); 66ef354866SJacob Pan void (*make_irq)(unsigned int irq); 67ef354866SJacob Pan }; 68ef354866SJacob Pan 69ef354866SJacob Pan extern struct legacy_pic *legacy_pic; 70ef354866SJacob Pan extern struct legacy_pic null_legacy_pic; 71ef354866SJacob Pan 72*30c7e5b1SPeter Zijlstra static inline bool has_legacy_pic(void) 73*30c7e5b1SPeter Zijlstra { 74*30c7e5b1SPeter Zijlstra return legacy_pic != &null_legacy_pic; 75*30c7e5b1SPeter Zijlstra } 76*30c7e5b1SPeter Zijlstra 7795d76accSJiang Liu static inline int nr_legacy_irqs(void) 7895d76accSJiang Liu { 7995d76accSJiang Liu return legacy_pic->nr_legacy_irqs; 8095d76accSJiang Liu } 8195d76accSJiang Liu 821965aae3SH. Peter Anvin #endif /* _ASM_X86_I8259_H */ 83