1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 21965aae3SH. Peter Anvin #ifndef _ASM_X86_I8259_H 31965aae3SH. Peter Anvin #define _ASM_X86_I8259_H 4bb898558SAl Viro 5bb898558SAl Viro #include <linux/delay.h> 6*0a957467SGuenter Roeck #include <asm/io.h> 7bb898558SAl Viro 8bb898558SAl Viro extern unsigned int cached_irq_mask; 9bb898558SAl Viro 10bb898558SAl Viro #define __byte(x, y) (((unsigned char *)&(y))[x]) 11bb898558SAl Viro #define cached_master_mask (__byte(0, cached_irq_mask)) 12bb898558SAl Viro #define cached_slave_mask (__byte(1, cached_irq_mask)) 13bb898558SAl Viro 14bb898558SAl Viro /* i8259A PIC registers */ 15bb898558SAl Viro #define PIC_MASTER_CMD 0x20 16bb898558SAl Viro #define PIC_MASTER_IMR 0x21 17bb898558SAl Viro #define PIC_MASTER_ISR PIC_MASTER_CMD 18bb898558SAl Viro #define PIC_MASTER_POLL PIC_MASTER_ISR 19bb898558SAl Viro #define PIC_MASTER_OCW3 PIC_MASTER_ISR 20bb898558SAl Viro #define PIC_SLAVE_CMD 0xa0 21bb898558SAl Viro #define PIC_SLAVE_IMR 0xa1 22bb898558SAl Viro 23bb898558SAl Viro /* i8259A PIC related value */ 24bb898558SAl Viro #define PIC_CASCADE_IR 2 25bb898558SAl Viro #define MASTER_ICW4_DEFAULT 0x01 26bb898558SAl Viro #define SLAVE_ICW4_DEFAULT 0x01 27bb898558SAl Viro #define PIC_ICW4_AEOI 2 28bb898558SAl Viro 295619c280SThomas Gleixner extern raw_spinlock_t i8259A_lock; 30bb898558SAl Viro 31bb898558SAl Viro /* the PIC may need a careful delay on some platforms, hence specific calls */ 32bb898558SAl Viro static inline unsigned char inb_pic(unsigned int port) 33bb898558SAl Viro { 34bb898558SAl Viro unsigned char value = inb(port); 35bb898558SAl Viro 36bb898558SAl Viro /* 37bb898558SAl Viro * delay for some accesses to PIC on motherboard or in chipset 38bb898558SAl Viro * must be at least one microsecond, so be safe here: 39bb898558SAl Viro */ 40bb898558SAl Viro udelay(2); 41bb898558SAl Viro 42bb898558SAl Viro return value; 43bb898558SAl Viro } 44bb898558SAl Viro 45bb898558SAl Viro static inline void outb_pic(unsigned char value, unsigned int port) 46bb898558SAl Viro { 47bb898558SAl Viro outb(value, port); 48bb898558SAl Viro /* 49bb898558SAl Viro * delay for some accesses to PIC on motherboard or in chipset 50bb898558SAl Viro * must be at least one microsecond, so be safe here: 51bb898558SAl Viro */ 52bb898558SAl Viro udelay(2); 53bb898558SAl Viro } 54bb898558SAl Viro 55bb898558SAl Viro extern struct irq_chip i8259A_chip; 56bb898558SAl Viro 57ef354866SJacob Pan struct legacy_pic { 58ef354866SJacob Pan int nr_legacy_irqs; 59ef354866SJacob Pan struct irq_chip *chip; 604305df94SThomas Gleixner void (*mask)(unsigned int irq); 614305df94SThomas Gleixner void (*unmask)(unsigned int irq); 62ef354866SJacob Pan void (*mask_all)(void); 63ef354866SJacob Pan void (*restore_mask)(void); 64ef354866SJacob Pan void (*init)(int auto_eoi); 658c058b0bSVitaly Kuznetsov int (*probe)(void); 66ef354866SJacob Pan int (*irq_pending)(unsigned int irq); 67ef354866SJacob Pan void (*make_irq)(unsigned int irq); 68ef354866SJacob Pan }; 69ef354866SJacob Pan 70ef354866SJacob Pan extern struct legacy_pic *legacy_pic; 71ef354866SJacob Pan extern struct legacy_pic null_legacy_pic; 72ef354866SJacob Pan 7330c7e5b1SPeter Zijlstra static inline bool has_legacy_pic(void) 7430c7e5b1SPeter Zijlstra { 7530c7e5b1SPeter Zijlstra return legacy_pic != &null_legacy_pic; 7630c7e5b1SPeter Zijlstra } 7730c7e5b1SPeter Zijlstra 7895d76accSJiang Liu static inline int nr_legacy_irqs(void) 7995d76accSJiang Liu { 8095d76accSJiang Liu return legacy_pic->nr_legacy_irqs; 8195d76accSJiang Liu } 8295d76accSJiang Liu 831965aae3SH. Peter Anvin #endif /* _ASM_X86_I8259_H */ 84