1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 21965aae3SH. Peter Anvin #ifndef _ASM_X86_I8259_H 31965aae3SH. Peter Anvin #define _ASM_X86_I8259_H 4bb898558SAl Viro 5bb898558SAl Viro #include <linux/delay.h> 60a957467SGuenter Roeck #include <asm/io.h> 7bb898558SAl Viro 8bb898558SAl Viro extern unsigned int cached_irq_mask; 9bb898558SAl Viro 10bb898558SAl Viro #define __byte(x, y) (((unsigned char *)&(y))[x]) 11bb898558SAl Viro #define cached_master_mask (__byte(0, cached_irq_mask)) 12bb898558SAl Viro #define cached_slave_mask (__byte(1, cached_irq_mask)) 13bb898558SAl Viro 14bb898558SAl Viro /* i8259A PIC registers */ 15bb898558SAl Viro #define PIC_MASTER_CMD 0x20 16bb898558SAl Viro #define PIC_MASTER_IMR 0x21 17bb898558SAl Viro #define PIC_MASTER_ISR PIC_MASTER_CMD 18bb898558SAl Viro #define PIC_MASTER_POLL PIC_MASTER_ISR 19bb898558SAl Viro #define PIC_MASTER_OCW3 PIC_MASTER_ISR 20bb898558SAl Viro #define PIC_SLAVE_CMD 0xa0 21bb898558SAl Viro #define PIC_SLAVE_IMR 0xa1 22d2531661SMaciej W. Rozycki #define PIC_ELCR1 0x4d0 23d2531661SMaciej W. Rozycki #define PIC_ELCR2 0x4d1 24bb898558SAl Viro 25bb898558SAl Viro /* i8259A PIC related value */ 26bb898558SAl Viro #define PIC_CASCADE_IR 2 27bb898558SAl Viro #define MASTER_ICW4_DEFAULT 0x01 28bb898558SAl Viro #define SLAVE_ICW4_DEFAULT 0x01 29bb898558SAl Viro #define PIC_ICW4_AEOI 2 30bb898558SAl Viro 315619c280SThomas Gleixner extern raw_spinlock_t i8259A_lock; 32bb898558SAl Viro 33bb898558SAl Viro /* the PIC may need a careful delay on some platforms, hence specific calls */ inb_pic(unsigned int port)34bb898558SAl Virostatic inline unsigned char inb_pic(unsigned int port) 35bb898558SAl Viro { 36bb898558SAl Viro unsigned char value = inb(port); 37bb898558SAl Viro 38bb898558SAl Viro /* 39bb898558SAl Viro * delay for some accesses to PIC on motherboard or in chipset 40bb898558SAl Viro * must be at least one microsecond, so be safe here: 41bb898558SAl Viro */ 42bb898558SAl Viro udelay(2); 43bb898558SAl Viro 44bb898558SAl Viro return value; 45bb898558SAl Viro } 46bb898558SAl Viro outb_pic(unsigned char value,unsigned int port)47bb898558SAl Virostatic inline void outb_pic(unsigned char value, unsigned int port) 48bb898558SAl Viro { 49bb898558SAl Viro outb(value, port); 50bb898558SAl Viro /* 51bb898558SAl Viro * delay for some accesses to PIC on motherboard or in chipset 52bb898558SAl Viro * must be at least one microsecond, so be safe here: 53bb898558SAl Viro */ 54bb898558SAl Viro udelay(2); 55bb898558SAl Viro } 56bb898558SAl Viro 57bb898558SAl Viro extern struct irq_chip i8259A_chip; 58bb898558SAl Viro 59ef354866SJacob Pan struct legacy_pic { 60ef354866SJacob Pan int nr_legacy_irqs; 61ef354866SJacob Pan struct irq_chip *chip; 624305df94SThomas Gleixner void (*mask)(unsigned int irq); 634305df94SThomas Gleixner void (*unmask)(unsigned int irq); 64ef354866SJacob Pan void (*mask_all)(void); 65ef354866SJacob Pan void (*restore_mask)(void); 66ef354866SJacob Pan void (*init)(int auto_eoi); 678c058b0bSVitaly Kuznetsov int (*probe)(void); 68ef354866SJacob Pan int (*irq_pending)(unsigned int irq); 69ef354866SJacob Pan void (*make_irq)(unsigned int irq); 70ef354866SJacob Pan }; 71ef354866SJacob Pan 72*128b0c97SThomas Gleixner void legacy_pic_pcat_compat(void); 73*128b0c97SThomas Gleixner 74ef354866SJacob Pan extern struct legacy_pic *legacy_pic; 75ef354866SJacob Pan extern struct legacy_pic null_legacy_pic; 76ef354866SJacob Pan has_legacy_pic(void)7730c7e5b1SPeter Zijlstrastatic inline bool has_legacy_pic(void) 7830c7e5b1SPeter Zijlstra { 7930c7e5b1SPeter Zijlstra return legacy_pic != &null_legacy_pic; 8030c7e5b1SPeter Zijlstra } 8130c7e5b1SPeter Zijlstra nr_legacy_irqs(void)8295d76accSJiang Liustatic inline int nr_legacy_irqs(void) 8395d76accSJiang Liu { 8495d76accSJiang Liu return legacy_pic->nr_legacy_irqs; 8595d76accSJiang Liu } 8695d76accSJiang Liu 871965aae3SH. Peter Anvin #endif /* _ASM_X86_I8259_H */ 88