1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 28ede0bdbSAl Viro #ifndef __UM_CACHE_H 38ede0bdbSAl Viro #define __UM_CACHE_H 48ede0bdbSAl Viro 58ede0bdbSAl Viro 68ede0bdbSAl Viro #if defined(CONFIG_UML_X86) && !defined(CONFIG_64BIT) 78ede0bdbSAl Viro # define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT) 88ede0bdbSAl Viro #elif defined(CONFIG_UML_X86) /* 64-bit */ 98ede0bdbSAl Viro # define L1_CACHE_SHIFT 6 /* Should be 7 on Intel */ 108ede0bdbSAl Viro #else 118ede0bdbSAl Viro /* XXX: this was taken from x86, now it's completely random. Luckily only 128ede0bdbSAl Viro * affects SMP padding. */ 138ede0bdbSAl Viro # define L1_CACHE_SHIFT 5 148ede0bdbSAl Viro #endif 158ede0bdbSAl Viro 168ede0bdbSAl Viro #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 178ede0bdbSAl Viro 188ede0bdbSAl Viro #endif 19