1*b2441318SGreg Kroah-Hartman/* SPDX-License-Identifier: GPL-2.0 */ 288278ca2SAdrian Bunk/* 31da177e4SLinus Torvalds * tsunami.S: High speed MicroSparc-I mmu/cache operations. 41da177e4SLinus Torvalds * 51da177e4SLinus Torvalds * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) 61da177e4SLinus Torvalds */ 71da177e4SLinus Torvalds 81da177e4SLinus Torvalds#include <asm/ptrace.h> 947003497SSam Ravnborg#include <asm/asm-offsets.h> 101da177e4SLinus Torvalds#include <asm/psr.h> 111da177e4SLinus Torvalds#include <asm/asi.h> 121da177e4SLinus Torvalds#include <asm/page.h> 131da177e4SLinus Torvalds#include <asm/pgtsrmmu.h> 141da177e4SLinus Torvalds 151da177e4SLinus Torvalds .text 161da177e4SLinus Torvalds .align 4 171da177e4SLinus Torvalds 181da177e4SLinus Torvalds .globl tsunami_flush_cache_all, tsunami_flush_cache_mm 191da177e4SLinus Torvalds .globl tsunami_flush_cache_range, tsunami_flush_cache_page 201da177e4SLinus Torvalds .globl tsunami_flush_page_to_ram, tsunami_flush_page_for_dma 211da177e4SLinus Torvalds .globl tsunami_flush_sig_insns 221da177e4SLinus Torvalds .globl tsunami_flush_tlb_all, tsunami_flush_tlb_mm 231da177e4SLinus Torvalds .globl tsunami_flush_tlb_range, tsunami_flush_tlb_page 241da177e4SLinus Torvalds 251da177e4SLinus Torvalds /* Sliiick... */ 261da177e4SLinus Torvaldstsunami_flush_cache_page: 271da177e4SLinus Torvaldstsunami_flush_cache_range: 28961246b4SOlivier DANET ld [%o0 + VMA_VM_MM], %o0 291da177e4SLinus Torvaldstsunami_flush_cache_mm: 301da177e4SLinus Torvalds ld [%o0 + AOFF_mm_context], %g2 311da177e4SLinus Torvalds cmp %g2, -1 321da177e4SLinus Torvalds be tsunami_flush_cache_out 331da177e4SLinus Torvaldstsunami_flush_cache_all: 341da177e4SLinus Torvalds WINDOW_FLUSH(%g4, %g5) 351da177e4SLinus Torvaldstsunami_flush_page_for_dma: 361da177e4SLinus Torvalds sta %g0, [%g0] ASI_M_IC_FLCLEAR 371da177e4SLinus Torvalds sta %g0, [%g0] ASI_M_DC_FLCLEAR 381da177e4SLinus Torvaldstsunami_flush_cache_out: 391da177e4SLinus Torvaldstsunami_flush_page_to_ram: 401da177e4SLinus Torvalds retl 411da177e4SLinus Torvalds nop 421da177e4SLinus Torvalds 431da177e4SLinus Torvaldstsunami_flush_sig_insns: 441da177e4SLinus Torvalds flush %o1 451da177e4SLinus Torvalds retl 461da177e4SLinus Torvalds flush %o1 + 4 471da177e4SLinus Torvalds 481da177e4SLinus Torvalds /* More slick stuff... */ 491da177e4SLinus Torvaldstsunami_flush_tlb_range: 50961246b4SOlivier DANET ld [%o0 + VMA_VM_MM], %o0 511da177e4SLinus Torvaldstsunami_flush_tlb_mm: 521da177e4SLinus Torvalds ld [%o0 + AOFF_mm_context], %g2 531da177e4SLinus Torvalds cmp %g2, -1 541da177e4SLinus Torvalds be tsunami_flush_tlb_out 551da177e4SLinus Torvaldstsunami_flush_tlb_all: 561da177e4SLinus Torvalds mov 0x400, %o1 571da177e4SLinus Torvalds sta %g0, [%o1] ASI_M_FLUSH_PROBE 581da177e4SLinus Torvalds nop 591da177e4SLinus Torvalds nop 601da177e4SLinus Torvalds nop 611da177e4SLinus Torvalds nop 621da177e4SLinus Torvalds nop 631da177e4SLinus Torvaldstsunami_flush_tlb_out: 641da177e4SLinus Torvalds retl 651da177e4SLinus Torvalds nop 661da177e4SLinus Torvalds 671da177e4SLinus Torvalds /* This one can be done in a fine grained manner... */ 681da177e4SLinus Torvaldstsunami_flush_tlb_page: 69961246b4SOlivier DANET ld [%o0 + VMA_VM_MM], %o0 701da177e4SLinus Torvalds mov SRMMU_CTX_REG, %g1 711da177e4SLinus Torvalds ld [%o0 + AOFF_mm_context], %o3 721da177e4SLinus Torvalds andn %o1, (PAGE_SIZE - 1), %o1 731da177e4SLinus Torvalds cmp %o3, -1 741da177e4SLinus Torvalds be tsunami_flush_tlb_page_out 751da177e4SLinus Torvalds lda [%g1] ASI_M_MMUREGS, %g5 761da177e4SLinus Torvalds sta %o3, [%g1] ASI_M_MMUREGS 771da177e4SLinus Torvalds sta %g0, [%o1] ASI_M_FLUSH_PROBE 781da177e4SLinus Torvalds nop 791da177e4SLinus Torvalds nop 801da177e4SLinus Torvalds nop 811da177e4SLinus Torvalds nop 821da177e4SLinus Torvalds nop 831da177e4SLinus Torvaldstsunami_flush_tlb_page_out: 841da177e4SLinus Torvalds retl 851da177e4SLinus Torvalds sta %g5, [%g1] ASI_M_MMUREGS 861da177e4SLinus Torvalds 871da177e4SLinus Torvalds#define MIRROR_BLOCK(dst, src, offset, t0, t1, t2, t3) \ 881da177e4SLinus Torvalds ldd [src + offset + 0x18], t0; \ 891da177e4SLinus Torvalds std t0, [dst + offset + 0x18]; \ 901da177e4SLinus Torvalds ldd [src + offset + 0x10], t2; \ 911da177e4SLinus Torvalds std t2, [dst + offset + 0x10]; \ 921da177e4SLinus Torvalds ldd [src + offset + 0x08], t0; \ 931da177e4SLinus Torvalds std t0, [dst + offset + 0x08]; \ 941da177e4SLinus Torvalds ldd [src + offset + 0x00], t2; \ 951da177e4SLinus Torvalds std t2, [dst + offset + 0x00]; 961da177e4SLinus Torvalds 971da177e4SLinus Torvaldstsunami_copy_1page: 981da177e4SLinus Torvalds/* NOTE: This routine has to be shorter than 70insns --jj */ 991da177e4SLinus Torvalds or %g0, (PAGE_SIZE >> 8), %g1 1001da177e4SLinus Torvalds1: 1011da177e4SLinus Torvalds MIRROR_BLOCK(%o0, %o1, 0x00, %o2, %o3, %o4, %o5) 1021da177e4SLinus Torvalds MIRROR_BLOCK(%o0, %o1, 0x20, %o2, %o3, %o4, %o5) 1031da177e4SLinus Torvalds MIRROR_BLOCK(%o0, %o1, 0x40, %o2, %o3, %o4, %o5) 1041da177e4SLinus Torvalds MIRROR_BLOCK(%o0, %o1, 0x60, %o2, %o3, %o4, %o5) 1051da177e4SLinus Torvalds MIRROR_BLOCK(%o0, %o1, 0x80, %o2, %o3, %o4, %o5) 1061da177e4SLinus Torvalds MIRROR_BLOCK(%o0, %o1, 0xa0, %o2, %o3, %o4, %o5) 1071da177e4SLinus Torvalds MIRROR_BLOCK(%o0, %o1, 0xc0, %o2, %o3, %o4, %o5) 1081da177e4SLinus Torvalds MIRROR_BLOCK(%o0, %o1, 0xe0, %o2, %o3, %o4, %o5) 1091da177e4SLinus Torvalds subcc %g1, 1, %g1 1101da177e4SLinus Torvalds add %o0, 0x100, %o0 1111da177e4SLinus Torvalds bne 1b 1121da177e4SLinus Torvalds add %o1, 0x100, %o1 1131da177e4SLinus Torvalds 1141da177e4SLinus Torvalds .globl tsunami_setup_blockops 1151da177e4SLinus Torvaldstsunami_setup_blockops: 1161da177e4SLinus Torvalds sethi %hi(__copy_1page), %o0 1171da177e4SLinus Torvalds or %o0, %lo(__copy_1page), %o0 1181da177e4SLinus Torvalds sethi %hi(tsunami_copy_1page), %o1 1191da177e4SLinus Torvalds or %o1, %lo(tsunami_copy_1page), %o1 1201da177e4SLinus Torvalds sethi %hi(tsunami_setup_blockops), %o2 1211da177e4SLinus Torvalds or %o2, %lo(tsunami_setup_blockops), %o2 1221da177e4SLinus Torvalds ld [%o1], %o4 1231da177e4SLinus Torvalds1: add %o1, 4, %o1 1241da177e4SLinus Torvalds st %o4, [%o0] 1251da177e4SLinus Torvalds add %o0, 4, %o0 1261da177e4SLinus Torvalds cmp %o1, %o2 1271da177e4SLinus Torvalds bne 1b 1281da177e4SLinus Torvalds ld [%o1], %o4 1291da177e4SLinus Torvalds sta %g0, [%g0] ASI_M_IC_FLCLEAR 1301da177e4SLinus Torvalds sta %g0, [%g0] ASI_M_DC_FLCLEAR 1311da177e4SLinus Torvalds retl 1321da177e4SLinus Torvalds nop 133