1a439fe51SSam Ravnborg #ifndef _SPARC_TLBFLUSH_H 2a439fe51SSam Ravnborg #define _SPARC_TLBFLUSH_H 3a439fe51SSam Ravnborg 4*5d83d666SDavid S. Miller #include <asm/cachetlb_32.h> 5a439fe51SSam Ravnborg 6*5d83d666SDavid S. Miller #define flush_tlb_all() \ 7*5d83d666SDavid S. Miller sparc32_cachetlb_ops->tlb_all() 8*5d83d666SDavid S. Miller #define flush_tlb_mm(mm) \ 9*5d83d666SDavid S. Miller sparc32_cachetlb_ops->tlb_mm(mm) 10*5d83d666SDavid S. Miller #define flush_tlb_range(vma, start, end) \ 11*5d83d666SDavid S. Miller sparc32_cachetlb_ops->tlb_range(vma, start, end) 12*5d83d666SDavid S. Miller #define flush_tlb_page(vma, addr) \ 13*5d83d666SDavid S. Miller sparc32_cachetlb_ops->tlb_page(vma, addr) 14a439fe51SSam Ravnborg 15a439fe51SSam Ravnborg /* 16a439fe51SSam Ravnborg * This is a kludge, until I know better. --zaitcev XXX 17a439fe51SSam Ravnborg */ 18a439fe51SSam Ravnborg static inline void flush_tlb_kernel_range(unsigned long start, 19a439fe51SSam Ravnborg unsigned long end) 20a439fe51SSam Ravnborg { 21a439fe51SSam Ravnborg flush_tlb_all(); 22a439fe51SSam Ravnborg } 23a439fe51SSam Ravnborg 24a439fe51SSam Ravnborg #endif /* _SPARC_TLBFLUSH_H */ 25