1*a439fe51SSam Ravnborg /* 2*a439fe51SSam Ravnborg * include/asm/sunbpp.h 3*a439fe51SSam Ravnborg */ 4*a439fe51SSam Ravnborg 5*a439fe51SSam Ravnborg #ifndef _ASM_SPARC_SUNBPP_H 6*a439fe51SSam Ravnborg #define _ASM_SPARC_SUNBPP_H 7*a439fe51SSam Ravnborg 8*a439fe51SSam Ravnborg struct bpp_regs { 9*a439fe51SSam Ravnborg /* DMA registers */ 10*a439fe51SSam Ravnborg __volatile__ __u32 p_csr; /* DMA Control/Status Register */ 11*a439fe51SSam Ravnborg __volatile__ __u32 p_addr; /* Address Register */ 12*a439fe51SSam Ravnborg __volatile__ __u32 p_bcnt; /* Byte Count Register */ 13*a439fe51SSam Ravnborg __volatile__ __u32 p_tst_csr; /* Test Control/Status (DMA2 only) */ 14*a439fe51SSam Ravnborg /* Parallel Port registers */ 15*a439fe51SSam Ravnborg __volatile__ __u16 p_hcr; /* Hardware Configuration Register */ 16*a439fe51SSam Ravnborg __volatile__ __u16 p_ocr; /* Operation Configuration Register */ 17*a439fe51SSam Ravnborg __volatile__ __u8 p_dr; /* Parallel Data Register */ 18*a439fe51SSam Ravnborg __volatile__ __u8 p_tcr; /* Transfer Control Register */ 19*a439fe51SSam Ravnborg __volatile__ __u8 p_or; /* Output Register */ 20*a439fe51SSam Ravnborg __volatile__ __u8 p_ir; /* Input Register */ 21*a439fe51SSam Ravnborg __volatile__ __u16 p_icr; /* Interrupt Control Register */ 22*a439fe51SSam Ravnborg }; 23*a439fe51SSam Ravnborg 24*a439fe51SSam Ravnborg /* P_HCR. Time is in increments of SBus clock. */ 25*a439fe51SSam Ravnborg #define P_HCR_TEST 0x8000 /* Allows buried counters to be read */ 26*a439fe51SSam Ravnborg #define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */ 27*a439fe51SSam Ravnborg #define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */ 28*a439fe51SSam Ravnborg 29*a439fe51SSam Ravnborg /* P_OCR. */ 30*a439fe51SSam Ravnborg #define P_OCR_MEM_CLR 0x8000 31*a439fe51SSam Ravnborg #define P_OCR_DATA_SRC 0x4000 /* ) */ 32*a439fe51SSam Ravnborg #define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */ 33*a439fe51SSam Ravnborg #define P_OCR_BUSY_DSEL 0x1000 /* ) selects */ 34*a439fe51SSam Ravnborg #define P_OCR_ACK_DSEL 0x0800 /* ) */ 35*a439fe51SSam Ravnborg #define P_OCR_EN_DIAG 0x0400 36*a439fe51SSam Ravnborg #define P_OCR_BUSY_OP 0x0200 /* Busy operation */ 37*a439fe51SSam Ravnborg #define P_OCR_ACK_OP 0x0100 /* Ack operation */ 38*a439fe51SSam Ravnborg #define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */ 39*a439fe51SSam Ravnborg #define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */ 40*a439fe51SSam Ravnborg #define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */ 41*a439fe51SSam Ravnborg #define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */ 42*a439fe51SSam Ravnborg 43*a439fe51SSam Ravnborg /* P_TCR */ 44*a439fe51SSam Ravnborg #define P_TCR_DIR 0x08 45*a439fe51SSam Ravnborg #define P_TCR_BUSY 0x04 46*a439fe51SSam Ravnborg #define P_TCR_ACK 0x02 47*a439fe51SSam Ravnborg #define P_TCR_DS 0x01 /* Strobe */ 48*a439fe51SSam Ravnborg 49*a439fe51SSam Ravnborg /* P_OR */ 50*a439fe51SSam Ravnborg #define P_OR_V3 0x20 /* ) */ 51*a439fe51SSam Ravnborg #define P_OR_V2 0x10 /* ) on Zebra only */ 52*a439fe51SSam Ravnborg #define P_OR_V1 0x08 /* ) */ 53*a439fe51SSam Ravnborg #define P_OR_INIT 0x04 54*a439fe51SSam Ravnborg #define P_OR_AFXN 0x02 /* Auto Feed */ 55*a439fe51SSam Ravnborg #define P_OR_SLCT_IN 0x01 56*a439fe51SSam Ravnborg 57*a439fe51SSam Ravnborg /* P_IR */ 58*a439fe51SSam Ravnborg #define P_IR_PE 0x04 59*a439fe51SSam Ravnborg #define P_IR_SLCT 0x02 60*a439fe51SSam Ravnborg #define P_IR_ERR 0x01 61*a439fe51SSam Ravnborg 62*a439fe51SSam Ravnborg /* P_ICR */ 63*a439fe51SSam Ravnborg #define P_DS_IRQ 0x8000 /* RW1 */ 64*a439fe51SSam Ravnborg #define P_ACK_IRQ 0x4000 /* RW1 */ 65*a439fe51SSam Ravnborg #define P_BUSY_IRQ 0x2000 /* RW1 */ 66*a439fe51SSam Ravnborg #define P_PE_IRQ 0x1000 /* RW1 */ 67*a439fe51SSam Ravnborg #define P_SLCT_IRQ 0x0800 /* RW1 */ 68*a439fe51SSam Ravnborg #define P_ERR_IRQ 0x0400 /* RW1 */ 69*a439fe51SSam Ravnborg #define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */ 70*a439fe51SSam Ravnborg #define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */ 71*a439fe51SSam Ravnborg #define P_BUSY_IRP 0x0080 /* RW 1= rising edge */ 72*a439fe51SSam Ravnborg #define P_BUSY_IRQ_EN 0x0040 /* RW */ 73*a439fe51SSam Ravnborg #define P_PE_IRP 0x0020 /* RW 1= rising edge */ 74*a439fe51SSam Ravnborg #define P_PE_IRQ_EN 0x0010 /* RW */ 75*a439fe51SSam Ravnborg #define P_SLCT_IRP 0x0008 /* RW 1= rising edge */ 76*a439fe51SSam Ravnborg #define P_SLCT_IRQ_EN 0x0004 /* RW */ 77*a439fe51SSam Ravnborg #define P_ERR_IRP 0x0002 /* RW1 1= rising edge */ 78*a439fe51SSam Ravnborg #define P_ERR_IRQ_EN 0x0001 /* RW */ 79*a439fe51SSam Ravnborg 80*a439fe51SSam Ravnborg #endif /* !(_ASM_SPARC_SUNBPP_H) */ 81