xref: /openbmc/linux/arch/sparc/include/asm/smp_32.h (revision 4f2c0a4acffbec01079c28f839422e64ddeff004)
1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2a439fe51SSam Ravnborg /* smp.h: Sparc specific SMP stuff.
3a439fe51SSam Ravnborg  *
4a439fe51SSam Ravnborg  * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5a439fe51SSam Ravnborg  */
6a439fe51SSam Ravnborg 
7a439fe51SSam Ravnborg #ifndef _SPARC_SMP_H
8a439fe51SSam Ravnborg #define _SPARC_SMP_H
9a439fe51SSam Ravnborg 
10a439fe51SSam Ravnborg #include <linux/threads.h>
11a439fe51SSam Ravnborg #include <asm/head.h>
12a439fe51SSam Ravnborg 
13a439fe51SSam Ravnborg #ifndef __ASSEMBLY__
14a439fe51SSam Ravnborg 
15a439fe51SSam Ravnborg #include <linux/cpumask.h>
16a439fe51SSam Ravnborg 
17a439fe51SSam Ravnborg #endif /* __ASSEMBLY__ */
18a439fe51SSam Ravnborg 
19a439fe51SSam Ravnborg #ifdef CONFIG_SMP
20a439fe51SSam Ravnborg 
21a439fe51SSam Ravnborg #ifndef __ASSEMBLY__
22a439fe51SSam Ravnborg 
23a439fe51SSam Ravnborg #include <asm/ptrace.h>
24a439fe51SSam Ravnborg #include <asm/asi.h>
2560063497SArun Sharma #include <linux/atomic.h>
26a439fe51SSam Ravnborg 
27a439fe51SSam Ravnborg /*
28a439fe51SSam Ravnborg  *	Private routines/data
29a439fe51SSam Ravnborg  */
30a439fe51SSam Ravnborg 
31a439fe51SSam Ravnborg extern unsigned char boot_cpu_id;
32b7afdb7eSSam Ravnborg extern volatile unsigned long cpu_callin_map[NR_CPUS];
33b7afdb7eSSam Ravnborg extern cpumask_t smp_commenced_mask;
34b7afdb7eSSam Ravnborg extern struct linux_prom_registers smp_penguin_ctable;
35a439fe51SSam Ravnborg 
36b7afdb7eSSam Ravnborg void cpu_panic(void);
37b7afdb7eSSam Ravnborg 
38a439fe51SSam Ravnborg /*
39a439fe51SSam Ravnborg  *	General functions that each host system must provide.
40a439fe51SSam Ravnborg  */
41a439fe51SSam Ravnborg 
42a439fe51SSam Ravnborg void sun4m_init_smp(void);
43a439fe51SSam Ravnborg void sun4d_init_smp(void);
44a439fe51SSam Ravnborg 
45a439fe51SSam Ravnborg void smp_callin(void);
46a439fe51SSam Ravnborg void smp_store_cpu_info(int);
47a439fe51SSam Ravnborg 
48d6d04819SDaniel Hellstrom void smp_resched_interrupt(void);
49d6d04819SDaniel Hellstrom void smp_call_function_single_interrupt(void);
50d6d04819SDaniel Hellstrom void smp_call_function_interrupt(void);
51d6d04819SDaniel Hellstrom 
52a439fe51SSam Ravnborg struct seq_file;
53a439fe51SSam Ravnborg void smp_bogo(struct seq_file *);
54a439fe51SSam Ravnborg void smp_info(struct seq_file *);
55a439fe51SSam Ravnborg 
564ba22b16SSam Ravnborg struct sparc32_ipi_ops {
57*17006e86SBart Van Assche 	void (*cross_call)(void *func, cpumask_t mask, unsigned long arg1,
584ba22b16SSam Ravnborg 			   unsigned long arg2, unsigned long arg3,
594ba22b16SSam Ravnborg 			   unsigned long arg4);
604ba22b16SSam Ravnborg 	void (*resched)(int cpu);
614ba22b16SSam Ravnborg 	void (*single)(int cpu);
624ba22b16SSam Ravnborg 	void (*mask_one)(int cpu);
634ba22b16SSam Ravnborg };
644ba22b16SSam Ravnborg extern const struct sparc32_ipi_ops *sparc32_ipi_ops;
65a439fe51SSam Ravnborg 
xc0(void * func)66*17006e86SBart Van Assche static inline void xc0(void *func)
674ba22b16SSam Ravnborg {
684ba22b16SSam Ravnborg 	sparc32_ipi_ops->cross_call(func, *cpu_online_mask, 0, 0, 0, 0);
694ba22b16SSam Ravnborg }
70a439fe51SSam Ravnborg 
xc1(void * func,unsigned long arg1)71*17006e86SBart Van Assche static inline void xc1(void *func, unsigned long arg1)
724ba22b16SSam Ravnborg {
734ba22b16SSam Ravnborg 	sparc32_ipi_ops->cross_call(func, *cpu_online_mask, arg1, 0, 0, 0);
744ba22b16SSam Ravnborg }
xc2(void * func,unsigned long arg1,unsigned long arg2)75*17006e86SBart Van Assche static inline void xc2(void *func, unsigned long arg1, unsigned long arg2)
764ba22b16SSam Ravnborg {
774ba22b16SSam Ravnborg 	sparc32_ipi_ops->cross_call(func, *cpu_online_mask, arg1, arg2, 0, 0);
784ba22b16SSam Ravnborg }
794ba22b16SSam Ravnborg 
xc3(void * func,unsigned long arg1,unsigned long arg2,unsigned long arg3)80*17006e86SBart Van Assche static inline void xc3(void *func, unsigned long arg1, unsigned long arg2,
81a439fe51SSam Ravnborg 		       unsigned long arg3)
824ba22b16SSam Ravnborg {
834ba22b16SSam Ravnborg 	sparc32_ipi_ops->cross_call(func, *cpu_online_mask,
844ba22b16SSam Ravnborg 				    arg1, arg2, arg3, 0);
854ba22b16SSam Ravnborg }
864ba22b16SSam Ravnborg 
xc4(void * func,unsigned long arg1,unsigned long arg2,unsigned long arg3,unsigned long arg4)87*17006e86SBart Van Assche static inline void xc4(void *func, unsigned long arg1, unsigned long arg2,
88a439fe51SSam Ravnborg 		       unsigned long arg3, unsigned long arg4)
894ba22b16SSam Ravnborg {
904ba22b16SSam Ravnborg 	sparc32_ipi_ops->cross_call(func, *cpu_online_mask,
914ba22b16SSam Ravnborg 				    arg1, arg2, arg3, arg4);
924ba22b16SSam Ravnborg }
93a439fe51SSam Ravnborg 
94f05a6865SSam Ravnborg void arch_send_call_function_single_ipi(int cpu);
95f05a6865SSam Ravnborg void arch_send_call_function_ipi_mask(const struct cpumask *mask);
9666e4f8c0SDavid S. Miller 
cpu_logical_map(int cpu)97a439fe51SSam Ravnborg static inline int cpu_logical_map(int cpu)
98a439fe51SSam Ravnborg {
99a439fe51SSam Ravnborg 	return cpu;
100a439fe51SSam Ravnborg }
101a439fe51SSam Ravnborg 
102f05a6865SSam Ravnborg int hard_smp_processor_id(void);
103a439fe51SSam Ravnborg 
104a439fe51SSam Ravnborg #define raw_smp_processor_id()		(current_thread_info()->cpu)
105a439fe51SSam Ravnborg 
106a439fe51SSam Ravnborg void smp_setup_cpu_possible_map(void);
107a439fe51SSam Ravnborg 
108a439fe51SSam Ravnborg #endif /* !(__ASSEMBLY__) */
109a439fe51SSam Ravnborg 
110a439fe51SSam Ravnborg /* Sparc specific messages. */
111a439fe51SSam Ravnborg #define MSG_CROSS_CALL         0x0005       /* run func on cpus */
112a439fe51SSam Ravnborg 
113a439fe51SSam Ravnborg /* Empirical PROM processor mailbox constants.  If the per-cpu mailbox
114a439fe51SSam Ravnborg  * contains something other than one of these then the ipi is from
115a439fe51SSam Ravnborg  * Linux's active_kernel_processor.  This facility exists so that
116a439fe51SSam Ravnborg  * the boot monitor can capture all the other cpus when one catches
117a439fe51SSam Ravnborg  * a watchdog reset or the user enters the monitor using L1-A keys.
118a439fe51SSam Ravnborg  */
119a439fe51SSam Ravnborg #define MBOX_STOPCPU          0xFB
120a439fe51SSam Ravnborg #define MBOX_IDLECPU          0xFC
121a439fe51SSam Ravnborg #define MBOX_IDLECPU2         0xFD
122a439fe51SSam Ravnborg #define MBOX_STOPCPU2         0xFE
123a439fe51SSam Ravnborg 
124a439fe51SSam Ravnborg #else /* SMP */
125a439fe51SSam Ravnborg 
126a439fe51SSam Ravnborg #define hard_smp_processor_id()		0
127a439fe51SSam Ravnborg #define smp_setup_cpu_possible_map() do { } while (0)
128a439fe51SSam Ravnborg 
129a439fe51SSam Ravnborg #endif /* !(SMP) */
130a439fe51SSam Ravnborg #endif /* !(_SPARC_SMP_H) */
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