xref: /openbmc/linux/arch/sparc/include/asm/ecc.h (revision a439fe51a1f8eb087c22dd24d69cebae4a3addac)
1*a439fe51SSam Ravnborg /*
2*a439fe51SSam Ravnborg  * ecc.h: Definitions and defines for the external cache/memory
3*a439fe51SSam Ravnborg  *        controller on the sun4m.
4*a439fe51SSam Ravnborg  *
5*a439fe51SSam Ravnborg  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6*a439fe51SSam Ravnborg  */
7*a439fe51SSam Ravnborg 
8*a439fe51SSam Ravnborg #ifndef _SPARC_ECC_H
9*a439fe51SSam Ravnborg #define _SPARC_ECC_H
10*a439fe51SSam Ravnborg 
11*a439fe51SSam Ravnborg /* These registers are accessed through the SRMMU passthrough ASI 0x20 */
12*a439fe51SSam Ravnborg #define ECC_ENABLE     0x00000000       /* ECC enable register */
13*a439fe51SSam Ravnborg #define ECC_FSTATUS    0x00000008       /* ECC fault status register */
14*a439fe51SSam Ravnborg #define ECC_FADDR      0x00000010       /* ECC fault address register */
15*a439fe51SSam Ravnborg #define ECC_DIGNOSTIC  0x00000018       /* ECC diagnostics register */
16*a439fe51SSam Ravnborg #define ECC_MBAENAB    0x00000020       /* MBus arbiter enable register */
17*a439fe51SSam Ravnborg #define ECC_DMESG      0x00001000       /* Diagnostic message passing area */
18*a439fe51SSam Ravnborg 
19*a439fe51SSam Ravnborg /* ECC MBus Arbiter Enable register:
20*a439fe51SSam Ravnborg  *
21*a439fe51SSam Ravnborg  * ----------------------------------------
22*a439fe51SSam Ravnborg  * |              |SBUS|MOD3|MOD2|MOD1|RSV|
23*a439fe51SSam Ravnborg  * ----------------------------------------
24*a439fe51SSam Ravnborg  *  31           5   4   3    2    1    0
25*a439fe51SSam Ravnborg  *
26*a439fe51SSam Ravnborg  * SBUS: Enable MBus Arbiter on the SBus 0=off 1=on
27*a439fe51SSam Ravnborg  * MOD3: Enable MBus Arbiter on MBus module 3  0=off 1=on
28*a439fe51SSam Ravnborg  * MOD2: Enable MBus Arbiter on MBus module 2  0=off 1=on
29*a439fe51SSam Ravnborg  * MOD1: Enable MBus Arbiter on MBus module 1  0=off 1=on
30*a439fe51SSam Ravnborg  */
31*a439fe51SSam Ravnborg 
32*a439fe51SSam Ravnborg #define ECC_MBAE_SBUS     0x00000010
33*a439fe51SSam Ravnborg #define ECC_MBAE_MOD3     0x00000008
34*a439fe51SSam Ravnborg #define ECC_MBAE_MOD2     0x00000004
35*a439fe51SSam Ravnborg #define ECC_MBAE_MOD1     0x00000002
36*a439fe51SSam Ravnborg 
37*a439fe51SSam Ravnborg /* ECC Fault Control Register layout:
38*a439fe51SSam Ravnborg  *
39*a439fe51SSam Ravnborg  * -----------------------------
40*a439fe51SSam Ravnborg  * |    RESV   | ECHECK | EINT |
41*a439fe51SSam Ravnborg  * -----------------------------
42*a439fe51SSam Ravnborg  *  31        2     1       0
43*a439fe51SSam Ravnborg  *
44*a439fe51SSam Ravnborg  * ECHECK:  Enable ECC checking.  0=off 1=on
45*a439fe51SSam Ravnborg  * EINT:  Enable Interrupts for correctable errors. 0=off 1=on
46*a439fe51SSam Ravnborg  */
47*a439fe51SSam Ravnborg #define ECC_FCR_CHECK    0x00000002
48*a439fe51SSam Ravnborg #define ECC_FCR_INTENAB  0x00000001
49*a439fe51SSam Ravnborg 
50*a439fe51SSam Ravnborg /* ECC Fault Address Register Zero layout:
51*a439fe51SSam Ravnborg  *
52*a439fe51SSam Ravnborg  * -----------------------------------------------------
53*a439fe51SSam Ravnborg  * | MID | S | RSV |  VA   | BM |AT| C| SZ |TYP| PADDR |
54*a439fe51SSam Ravnborg  * -----------------------------------------------------
55*a439fe51SSam Ravnborg  *  31-28  27 26-22  21-14   13  12 11 10-8 7-4   3-0
56*a439fe51SSam Ravnborg  *
57*a439fe51SSam Ravnborg  * MID: ModuleID of the faulting processor. ie. who did it?
58*a439fe51SSam Ravnborg  * S: Supervisor/Privileged access? 0=no 1=yes
59*a439fe51SSam Ravnborg  * VA: Bits 19-12 of the virtual faulting address, these are the
60*a439fe51SSam Ravnborg  *     superset bits in the virtual cache and can be used for
61*a439fe51SSam Ravnborg  *     a flush operation if necessary.
62*a439fe51SSam Ravnborg  * BM: Boot mode? 0=no 1=yes  This is just like the SRMMU boot
63*a439fe51SSam Ravnborg  *     mode bit.
64*a439fe51SSam Ravnborg  * AT: Did this fault happen during an atomic instruction? 0=no
65*a439fe51SSam Ravnborg  *     1=yes.  This means either an 'ldstub' or 'swap' instruction
66*a439fe51SSam Ravnborg  *     was in progress (but not finished) when this fault happened.
67*a439fe51SSam Ravnborg  *     This indicated whether the bus was locked when the fault
68*a439fe51SSam Ravnborg  *     occurred.
69*a439fe51SSam Ravnborg  * C: Did the pte for this access indicate that it was cacheable?
70*a439fe51SSam Ravnborg  *    0=no 1=yes
71*a439fe51SSam Ravnborg  * SZ: The size of the transaction.
72*a439fe51SSam Ravnborg  * TYP: The transaction type.
73*a439fe51SSam Ravnborg  * PADDR: Bits 35-32 of the physical address for the fault.
74*a439fe51SSam Ravnborg  */
75*a439fe51SSam Ravnborg #define ECC_FADDR0_MIDMASK   0xf0000000
76*a439fe51SSam Ravnborg #define ECC_FADDR0_S         0x08000000
77*a439fe51SSam Ravnborg #define ECC_FADDR0_VADDR     0x003fc000
78*a439fe51SSam Ravnborg #define ECC_FADDR0_BMODE     0x00002000
79*a439fe51SSam Ravnborg #define ECC_FADDR0_ATOMIC    0x00001000
80*a439fe51SSam Ravnborg #define ECC_FADDR0_CACHE     0x00000800
81*a439fe51SSam Ravnborg #define ECC_FADDR0_SIZE      0x00000700
82*a439fe51SSam Ravnborg #define ECC_FADDR0_TYPE      0x000000f0
83*a439fe51SSam Ravnborg #define ECC_FADDR0_PADDR     0x0000000f
84*a439fe51SSam Ravnborg 
85*a439fe51SSam Ravnborg /* ECC Fault Address Register One layout:
86*a439fe51SSam Ravnborg  *
87*a439fe51SSam Ravnborg  * -------------------------------------
88*a439fe51SSam Ravnborg  * |          Physical Address 31-0    |
89*a439fe51SSam Ravnborg  * -------------------------------------
90*a439fe51SSam Ravnborg  *  31                               0
91*a439fe51SSam Ravnborg  *
92*a439fe51SSam Ravnborg  * You get the upper 4 bits of the physical address from the
93*a439fe51SSam Ravnborg  * PADDR field in ECC Fault Address Zero register.
94*a439fe51SSam Ravnborg  */
95*a439fe51SSam Ravnborg 
96*a439fe51SSam Ravnborg /* ECC Fault Status Register layout:
97*a439fe51SSam Ravnborg  *
98*a439fe51SSam Ravnborg  * ----------------------------------------------
99*a439fe51SSam Ravnborg  * | RESV|C2E|MULT|SYNDROME|DWORD|UNC|TIMEO|BS|C|
100*a439fe51SSam Ravnborg  * ----------------------------------------------
101*a439fe51SSam Ravnborg  *  31-18  17  16    15-8    7-4   3    2    1 0
102*a439fe51SSam Ravnborg  *
103*a439fe51SSam Ravnborg  * C2E: A C2 graphics error occurred. 0=no 1=yes (SS10 only)
104*a439fe51SSam Ravnborg  * MULT: Multiple errors occurred ;-O 0=no 1=prom_panic(yes)
105*a439fe51SSam Ravnborg  * SYNDROME: Controller is mentally unstable.
106*a439fe51SSam Ravnborg  * DWORD:
107*a439fe51SSam Ravnborg  * UNC: Uncorrectable error.  0=no 1=yes
108*a439fe51SSam Ravnborg  * TIMEO: Timeout occurred. 0=no 1=yes
109*a439fe51SSam Ravnborg  * BS: C2 graphics bad slot access. 0=no 1=yes (SS10 only)
110*a439fe51SSam Ravnborg  * C: Correctable error? 0=no 1=yes
111*a439fe51SSam Ravnborg  */
112*a439fe51SSam Ravnborg 
113*a439fe51SSam Ravnborg #define ECC_FSR_C2ERR    0x00020000
114*a439fe51SSam Ravnborg #define ECC_FSR_MULT     0x00010000
115*a439fe51SSam Ravnborg #define ECC_FSR_SYND     0x0000ff00
116*a439fe51SSam Ravnborg #define ECC_FSR_DWORD    0x000000f0
117*a439fe51SSam Ravnborg #define ECC_FSR_UNC      0x00000008
118*a439fe51SSam Ravnborg #define ECC_FSR_TIMEO    0x00000004
119*a439fe51SSam Ravnborg #define ECC_FSR_BADSLOT  0x00000002
120*a439fe51SSam Ravnborg #define ECC_FSR_C        0x00000001
121*a439fe51SSam Ravnborg 
122*a439fe51SSam Ravnborg #endif /* !(_SPARC_ECC_H) */
123