1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2a439fe51SSam Ravnborg #ifndef _SPARC64_CHMCTRL_H 3a439fe51SSam Ravnborg #define _SPARC64_CHMCTRL_H 4a439fe51SSam Ravnborg 5a439fe51SSam Ravnborg /* Cheetah memory controller programmable registers. */ 6a439fe51SSam Ravnborg #define CHMCTRL_TCTRL1 0x00 /* Memory Timing Control I */ 7a439fe51SSam Ravnborg #define CHMCTRL_TCTRL2 0x08 /* Memory Timing Control II */ 8a439fe51SSam Ravnborg #define CHMCTRL_TCTRL3 0x38 /* Memory Timing Control III */ 9a439fe51SSam Ravnborg #define CHMCTRL_TCTRL4 0x40 /* Memory Timing Control IV */ 10a439fe51SSam Ravnborg #define CHMCTRL_DECODE1 0x10 /* Memory Address Decode I */ 11a439fe51SSam Ravnborg #define CHMCTRL_DECODE2 0x18 /* Memory Address Decode II */ 12a439fe51SSam Ravnborg #define CHMCTRL_DECODE3 0x20 /* Memory Address Decode III */ 13a439fe51SSam Ravnborg #define CHMCTRL_DECODE4 0x28 /* Memory Address Decode IV */ 14a439fe51SSam Ravnborg #define CHMCTRL_MACTRL 0x30 /* Memory Address Control */ 15a439fe51SSam Ravnborg 16a439fe51SSam Ravnborg /* Memory Timing Control I */ 17a439fe51SSam Ravnborg #define TCTRL1_SDRAMCTL_DLY 0xf000000000000000UL 18a439fe51SSam Ravnborg #define TCTRL1_SDRAMCTL_DLY_SHIFT 60 19a439fe51SSam Ravnborg #define TCTRL1_SDRAMCLK_DLY 0x0e00000000000000UL 20a439fe51SSam Ravnborg #define TCTRL1_SDRAMCLK_DLY_SHIFT 57 21a439fe51SSam Ravnborg #define TCTRL1_R 0x0100000000000000UL 22a439fe51SSam Ravnborg #define TCTRL1_R_SHIFT 56 23a439fe51SSam Ravnborg #define TCTRL1_AUTORFR_CYCLE 0x00fe000000000000UL 24a439fe51SSam Ravnborg #define TCTRL1_AUTORFR_CYCLE_SHIFT 49 25a439fe51SSam Ravnborg #define TCTRL1_RD_WAIT 0x0001f00000000000UL 26a439fe51SSam Ravnborg #define TCTRL1_RD_WAIT_SHIFT 44 27a439fe51SSam Ravnborg #define TCTRL1_PC_CYCLE 0x00000fc000000000UL 28a439fe51SSam Ravnborg #define TCTRL1_PC_CYCLE_SHIFT 38 29a439fe51SSam Ravnborg #define TCTRL1_WR_MORE_RAS_PW 0x0000003f00000000UL 30a439fe51SSam Ravnborg #define TCTRL1_WR_MORE_RAS_PW_SHIFT 32 31a439fe51SSam Ravnborg #define TCTRL1_RD_MORE_RAW_PW 0x00000000fc000000UL 32a439fe51SSam Ravnborg #define TCTRL1_RD_MORE_RAS_PW_SHIFT 26 33a439fe51SSam Ravnborg #define TCTRL1_ACT_WR_DLY 0x0000000003f00000UL 34a439fe51SSam Ravnborg #define TCTRL1_ACT_WR_DLY_SHIFT 20 35a439fe51SSam Ravnborg #define TCTRL1_ACT_RD_DLY 0x00000000000fc000UL 36a439fe51SSam Ravnborg #define TCTRL1_ACT_RD_DLY_SHIFT 14 37a439fe51SSam Ravnborg #define TCTRL1_BANK_PRESENT 0x0000000000003000UL 38a439fe51SSam Ravnborg #define TCTRL1_BANK_PRESENT_SHIFT 12 39a439fe51SSam Ravnborg #define TCTRL1_RFR_INT 0x0000000000000ff8UL 40a439fe51SSam Ravnborg #define TCTRL1_RFR_INT_SHIFT 3 41a439fe51SSam Ravnborg #define TCTRL1_SET_MODE_REG 0x0000000000000004UL 42a439fe51SSam Ravnborg #define TCTRL1_SET_MODE_REG_SHIFT 2 43a439fe51SSam Ravnborg #define TCTRL1_RFR_ENABLE 0x0000000000000002UL 44a439fe51SSam Ravnborg #define TCTRL1_RFR_ENABLE_SHIFT 1 45a439fe51SSam Ravnborg #define TCTRL1_PRECHG_ALL 0x0000000000000001UL 46a439fe51SSam Ravnborg #define TCTRL1_PRECHG_ALL_SHIFT 0 47a439fe51SSam Ravnborg 48a439fe51SSam Ravnborg /* Memory Timing Control II */ 49a439fe51SSam Ravnborg #define TCTRL2_WR_MSEL_DLY 0xfc00000000000000UL 50a439fe51SSam Ravnborg #define TCTRL2_WR_MSEL_DLY_SHIFT 58 51a439fe51SSam Ravnborg #define TCTRL2_RD_MSEL_DLY 0x03f0000000000000UL 52a439fe51SSam Ravnborg #define TCTRL2_RD_MSEL_DLY_SHIFT 52 53a439fe51SSam Ravnborg #define TCTRL2_WRDATA_THLD 0x000c000000000000UL 54a439fe51SSam Ravnborg #define TCTRL2_WRDATA_THLD_SHIFT 50 55a439fe51SSam Ravnborg #define TCTRL2_RDWR_RD_TI_DLY 0x0003f00000000000UL 56a439fe51SSam Ravnborg #define TCTRL2_RDWR_RD_TI_DLY_SHIFT 44 57a439fe51SSam Ravnborg #define TCTRL2_AUTOPRECHG_ENBL 0x0000080000000000UL 58a439fe51SSam Ravnborg #define TCTRL2_AUTOPRECHG_ENBL_SHIFT 43 59a439fe51SSam Ravnborg #define TCTRL2_RDWR_PI_MORE_DLY 0x000007c000000000UL 60a439fe51SSam Ravnborg #define TCTRL2_RDWR_PI_MORE_DLY_SHIFT 38 61a439fe51SSam Ravnborg #define TCTRL2_RDWR_1_DLY 0x0000003f00000000UL 62a439fe51SSam Ravnborg #define TCTRL2_RDWR_1_DLY_SHIFT 32 63a439fe51SSam Ravnborg #define TCTRL2_WRWR_PI_MORE_DLY 0x00000000f8000000UL 64a439fe51SSam Ravnborg #define TCTRL2_WRWR_PI_MORE_DLY_SHIFT 27 65a439fe51SSam Ravnborg #define TCTRL2_WRWR_1_DLY 0x0000000007e00000UL 66a439fe51SSam Ravnborg #define TCTRL2_WRWR_1_DLY_SHIFT 21 67a439fe51SSam Ravnborg #define TCTRL2_RDWR_RD_PI_MORE_DLY 0x00000000001f0000UL 68a439fe51SSam Ravnborg #define TCTRL2_RDWR_RD_PI_MORE_DLY_SHIFT 16 69a439fe51SSam Ravnborg #define TCTRL2_R 0x0000000000008000UL 70a439fe51SSam Ravnborg #define TCTRL2_R_SHIFT 15 71a439fe51SSam Ravnborg #define TCTRL2_SDRAM_MODE_REG_DATA 0x0000000000007fffUL 72a439fe51SSam Ravnborg #define TCTRL2_SDRAM_MODE_REG_DATA_SHIFT 0 73a439fe51SSam Ravnborg 74a439fe51SSam Ravnborg /* Memory Timing Control III */ 75a439fe51SSam Ravnborg #define TCTRL3_SDRAM_CTL_DLY 0xf000000000000000UL 76a439fe51SSam Ravnborg #define TCTRL3_SDRAM_CTL_DLY_SHIFT 60 77a439fe51SSam Ravnborg #define TCTRL3_SDRAM_CLK_DLY 0x0e00000000000000UL 78a439fe51SSam Ravnborg #define TCTRL3_SDRAM_CLK_DLY_SHIFT 57 79a439fe51SSam Ravnborg #define TCTRL3_R 0x0100000000000000UL 80a439fe51SSam Ravnborg #define TCTRL3_R_SHIFT 56 81a439fe51SSam Ravnborg #define TCTRL3_AUTO_RFR_CYCLE 0x00fe000000000000UL 82a439fe51SSam Ravnborg #define TCTRL3_AUTO_RFR_CYCLE_SHIFT 49 83a439fe51SSam Ravnborg #define TCTRL3_RD_WAIT 0x0001f00000000000UL 84a439fe51SSam Ravnborg #define TCTRL3_RD_WAIT_SHIFT 44 85a439fe51SSam Ravnborg #define TCTRL3_PC_CYCLE 0x00000fc000000000UL 86a439fe51SSam Ravnborg #define TCTRL3_PC_CYCLE_SHIFT 38 87a439fe51SSam Ravnborg #define TCTRL3_WR_MORE_RAW_PW 0x0000003f00000000UL 88a439fe51SSam Ravnborg #define TCTRL3_WR_MORE_RAW_PW_SHIFT 32 89a439fe51SSam Ravnborg #define TCTRL3_RD_MORE_RAW_PW 0x00000000fc000000UL 90a439fe51SSam Ravnborg #define TCTRL3_RD_MORE_RAW_PW_SHIFT 26 91a439fe51SSam Ravnborg #define TCTRL3_ACT_WR_DLY 0x0000000003f00000UL 92a439fe51SSam Ravnborg #define TCTRL3_ACT_WR_DLY_SHIFT 20 93a439fe51SSam Ravnborg #define TCTRL3_ACT_RD_DLY 0x00000000000fc000UL 94a439fe51SSam Ravnborg #define TCTRL3_ACT_RD_DLY_SHIFT 14 95a439fe51SSam Ravnborg #define TCTRL3_BANK_PRESENT 0x0000000000003000UL 96a439fe51SSam Ravnborg #define TCTRL3_BANK_PRESENT_SHIFT 12 97a439fe51SSam Ravnborg #define TCTRL3_RFR_INT 0x0000000000000ff8UL 98a439fe51SSam Ravnborg #define TCTRL3_RFR_INT_SHIFT 3 99a439fe51SSam Ravnborg #define TCTRL3_SET_MODE_REG 0x0000000000000004UL 100a439fe51SSam Ravnborg #define TCTRL3_SET_MODE_REG_SHIFT 2 101a439fe51SSam Ravnborg #define TCTRL3_RFR_ENABLE 0x0000000000000002UL 102a439fe51SSam Ravnborg #define TCTRL3_RFR_ENABLE_SHIFT 1 103a439fe51SSam Ravnborg #define TCTRL3_PRECHG_ALL 0x0000000000000001UL 104a439fe51SSam Ravnborg #define TCTRL3_PRECHG_ALL_SHIFT 0 105a439fe51SSam Ravnborg 106a439fe51SSam Ravnborg /* Memory Timing Control IV */ 107a439fe51SSam Ravnborg #define TCTRL4_WR_MSEL_DLY 0xfc00000000000000UL 108a439fe51SSam Ravnborg #define TCTRL4_WR_MSEL_DLY_SHIFT 58 109a439fe51SSam Ravnborg #define TCTRL4_RD_MSEL_DLY 0x03f0000000000000UL 110a439fe51SSam Ravnborg #define TCTRL4_RD_MSEL_DLY_SHIFT 52 111a439fe51SSam Ravnborg #define TCTRL4_WRDATA_THLD 0x000c000000000000UL 112a439fe51SSam Ravnborg #define TCTRL4_WRDATA_THLD_SHIFT 50 113a439fe51SSam Ravnborg #define TCTRL4_RDWR_RD_RI_DLY 0x0003f00000000000UL 114a439fe51SSam Ravnborg #define TCTRL4_RDWR_RD_RI_DLY_SHIFT 44 115a439fe51SSam Ravnborg #define TCTRL4_AUTO_PRECHG_ENBL 0x0000080000000000UL 116a439fe51SSam Ravnborg #define TCTRL4_AUTO_PRECHG_ENBL_SHIFT 43 117a439fe51SSam Ravnborg #define TCTRL4_RD_WR_PI_MORE_DLY 0x000007c000000000UL 118a439fe51SSam Ravnborg #define TCTRL4_RD_WR_PI_MORE_DLY_SHIFT 38 119a439fe51SSam Ravnborg #define TCTRL4_RD_WR_TI_DLY 0x0000003f00000000UL 120a439fe51SSam Ravnborg #define TCTRL4_RD_WR_TI_DLY_SHIFT 32 121a439fe51SSam Ravnborg #define TCTRL4_WR_WR_PI_MORE_DLY 0x00000000f8000000UL 122a439fe51SSam Ravnborg #define TCTRL4_WR_WR_PI_MORE_DLY_SHIFT 27 123a439fe51SSam Ravnborg #define TCTRL4_WR_WR_TI_DLY 0x0000000007e00000UL 124a439fe51SSam Ravnborg #define TCTRL4_WR_WR_TI_DLY_SHIFT 21 125a439fe51SSam Ravnborg #define TCTRL4_RDWR_RD_PI_MORE_DLY 0x00000000001f000UL0 126a439fe51SSam Ravnborg #define TCTRL4_RDWR_RD_PI_MORE_DLY_SHIFT 16 127a439fe51SSam Ravnborg #define TCTRL4_R 0x0000000000008000UL 128a439fe51SSam Ravnborg #define TCTRL4_R_SHIFT 15 129a439fe51SSam Ravnborg #define TCTRL4_SDRAM_MODE_REG_DATA 0x0000000000007fffUL 130a439fe51SSam Ravnborg #define TCTRL4_SDRAM_MODE_REG_DATA_SHIFT 0 131a439fe51SSam Ravnborg 132a439fe51SSam Ravnborg /* All 4 memory address decoding registers have the 133a439fe51SSam Ravnborg * same layout. 134a439fe51SSam Ravnborg */ 135a439fe51SSam Ravnborg #define MEM_DECODE_VALID 0x8000000000000000UL /* Valid */ 136a439fe51SSam Ravnborg #define MEM_DECODE_VALID_SHIFT 63 137a439fe51SSam Ravnborg #define MEM_DECODE_UK 0x001ffe0000000000UL /* Upper mask */ 138a439fe51SSam Ravnborg #define MEM_DECODE_UK_SHIFT 41 139a439fe51SSam Ravnborg #define MEM_DECODE_UM 0x0000001ffff00000UL /* Upper match */ 140a439fe51SSam Ravnborg #define MEM_DECODE_UM_SHIFT 20 141a439fe51SSam Ravnborg #define MEM_DECODE_LK 0x000000000003c000UL /* Lower mask */ 142a439fe51SSam Ravnborg #define MEM_DECODE_LK_SHIFT 14 143a439fe51SSam Ravnborg #define MEM_DECODE_LM 0x0000000000000f00UL /* Lower match */ 144a439fe51SSam Ravnborg #define MEM_DECODE_LM_SHIFT 8 145a439fe51SSam Ravnborg 146a439fe51SSam Ravnborg #define PA_UPPER_BITS 0x000007fffc000000UL 147a439fe51SSam Ravnborg #define PA_UPPER_BITS_SHIFT 26 148a439fe51SSam Ravnborg #define PA_LOWER_BITS 0x00000000000003c0UL 149a439fe51SSam Ravnborg #define PA_LOWER_BITS_SHIFT 6 150a439fe51SSam Ravnborg 151a439fe51SSam Ravnborg #define MACTRL_R0 0x8000000000000000UL 152a439fe51SSam Ravnborg #define MACTRL_R0_SHIFT 63 153a439fe51SSam Ravnborg #define MACTRL_ADDR_LE_PW 0x7000000000000000UL 154a439fe51SSam Ravnborg #define MACTRL_ADDR_LE_PW_SHIFT 60 155a439fe51SSam Ravnborg #define MACTRL_CMD_PW 0x0f00000000000000UL 156a439fe51SSam Ravnborg #define MACTRL_CMD_PW_SHIFT 56 157a439fe51SSam Ravnborg #define MACTRL_HALF_MODE_WR_MSEL_DLY 0x00fc000000000000UL 158a439fe51SSam Ravnborg #define MACTRL_HALF_MODE_WR_MSEL_DLY_SHIFT 50 159a439fe51SSam Ravnborg #define MACTRL_HALF_MODE_RD_MSEL_DLY 0x0003f00000000000UL 160a439fe51SSam Ravnborg #define MACTRL_HALF_MODE_RD_MSEL_DLY_SHIFT 44 161a439fe51SSam Ravnborg #define MACTRL_HALF_MODE_SDRAM_CTL_DLY 0x00000f0000000000UL 162a439fe51SSam Ravnborg #define MACTRL_HALF_MODE_SDRAM_CTL_DLY_SHIFT 40 163a439fe51SSam Ravnborg #define MACTRL_HALF_MODE_SDRAM_CLK_DLY 0x000000e000000000UL 164a439fe51SSam Ravnborg #define MACTRL_HALF_MODE_SDRAM_CLK_DLY_SHIFT 37 165a439fe51SSam Ravnborg #define MACTRL_R1 0x0000001000000000UL 166a439fe51SSam Ravnborg #define MACTRL_R1_SHIFT 36 167a439fe51SSam Ravnborg #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3 0x0000000f00000000UL 168a439fe51SSam Ravnborg #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3_SHIFT 32 169a439fe51SSam Ravnborg #define MACTRL_ENC_INTLV_B3 0x00000000f8000000UL 170a439fe51SSam Ravnborg #define MACTRL_ENC_INTLV_B3_SHIFT 27 171a439fe51SSam Ravnborg #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2 0x0000000007800000UL 172a439fe51SSam Ravnborg #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2_SHIFT 23 173a439fe51SSam Ravnborg #define MACTRL_ENC_INTLV_B2 0x00000000007c0000UL 174a439fe51SSam Ravnborg #define MACTRL_ENC_INTLV_B2_SHIFT 18 175a439fe51SSam Ravnborg #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1 0x000000000003c000UL 176a439fe51SSam Ravnborg #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1_SHIFT 14 177a439fe51SSam Ravnborg #define MACTRL_ENC_INTLV_B1 0x0000000000003e00UL 178a439fe51SSam Ravnborg #define MACTRL_ENC_INTLV_B1_SHIFT 9 179a439fe51SSam Ravnborg #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0 0x00000000000001e0UL 180a439fe51SSam Ravnborg #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0_SHIFT 5 181a439fe51SSam Ravnborg #define MACTRL_ENC_INTLV_B0 0x000000000000001fUL 182a439fe51SSam Ravnborg #define MACTRL_ENC_INTLV_B0_SHIFT 0 183a439fe51SSam Ravnborg 184a439fe51SSam Ravnborg #endif /* _SPARC64_CHMCTRL_H */ 185