1 /* 2 * SH7760 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <asm/sci.h> 14 15 enum { 16 UNUSED = 0, 17 18 /* interrupt sources */ 19 IRL0, IRL1, IRL2, IRL3, 20 HUDI, GPIOI, 21 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3, 22 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7, 23 DMAC_DMAE, 24 IRQ4, IRQ5, IRQ6, IRQ7, 25 HCAN20, HCAN21, 26 SSI0, SSI1, 27 HAC0, HAC1, 28 I2C0, I2C1, 29 USB, LCDC, 30 DMABRG0, DMABRG1, DMABRG2, 31 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI, 32 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI, 33 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, 34 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, 35 HSPI, 36 MMCIF0, MMCIF1, MMCIF2, MMCIF3, 37 MFI, ADC, CMT, 38 TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, 39 WDT, 40 REF_RCMI, REF_ROVI, 41 42 /* interrupt groups */ 43 DMAC, DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, TMU2, REF, 44 }; 45 46 static struct intc_vect vectors[] __initdata = { 47 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 48 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 49 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 50 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), 51 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), 52 INTC_VECT(DMAC_DMAE, 0x6c0), 53 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820), 54 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860), 55 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920), 56 INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960), 57 INTC_VECT(HAC0, 0x980), INTC_VECT(HAC1, 0x9a0), 58 INTC_VECT(I2C0, 0x9c0), INTC_VECT(I2C1, 0x9e0), 59 INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20), 60 INTC_VECT(DMABRG0, 0xa80), INTC_VECT(DMABRG1, 0xaa0), 61 INTC_VECT(DMABRG2, 0xac0), 62 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0), 63 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0), 64 INTC_VECT(SCIF1_ERI, 0xb00), INTC_VECT(SCIF1_RXI, 0xb20), 65 INTC_VECT(SCIF1_BRI, 0xb40), INTC_VECT(SCIF1_TXI, 0xb60), 66 INTC_VECT(SCIF2_ERI, 0xb80), INTC_VECT(SCIF2_RXI, 0xba0), 67 INTC_VECT(SCIF2_BRI, 0xbc0), INTC_VECT(SCIF2_TXI, 0xbe0), 68 INTC_VECT(SIM_ERI, 0xc00), INTC_VECT(SIM_RXI, 0xc20), 69 INTC_VECT(SIM_TXI, 0xc40), INTC_VECT(SIM_TEI, 0xc60), 70 INTC_VECT(HSPI, 0xc80), 71 INTC_VECT(MMCIF0, 0xd00), INTC_VECT(MMCIF1, 0xd20), 72 INTC_VECT(MMCIF2, 0xd40), INTC_VECT(MMCIF3, 0xd60), 73 INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */ 74 INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0), 75 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 76 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 77 INTC_VECT(WDT, 0x560), 78 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), 79 }; 80 81 static struct intc_group groups[] __initdata = { 82 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, 83 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, 84 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), 85 INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2), 86 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), 87 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI), 88 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI), 89 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), 90 INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3), 91 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), 92 INTC_GROUP(REF, REF_RCMI, REF_ROVI), 93 }; 94 95 static struct intc_prio priorities[] __initdata = { 96 INTC_PRIO(SCIF0, 3), 97 INTC_PRIO(SCIF1, 3), 98 INTC_PRIO(SCIF2, 3), 99 INTC_PRIO(SIM, 3), 100 INTC_PRIO(DMAC, 7), 101 INTC_PRIO(DMABRG, 13), 102 }; 103 104 static struct intc_mask_reg mask_registers[] __initdata = { 105 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ 106 { IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21, 107 SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC, 108 0, DMABRG0, DMABRG1, DMABRG2, 109 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI, 110 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI, 111 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, } }, 112 { 0xfe080044, 0xfe080064, 32, /* INTMSK04 / INTMSKCLR04 */ 113 { 0, 0, 0, 0, 0, 0, 0, 0, 114 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, 115 HSPI, MMCIF0, MMCIF1, MMCIF2, 116 MMCIF3, 0, 0, 0, 0, 0, 0, 0, 117 0, MFI, 0, 0, 0, 0, ADC, CMT, } }, 118 }; 119 120 static struct intc_prio_reg prio_registers[] __initdata = { 121 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, 122 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, 123 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } }, 124 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, 125 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, 126 { 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1, 127 HAC0, HAC1, I2C0, I2C1 } }, 128 { 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0, 129 SCIF1, SCIF2, SIM, HSPI } }, 130 { 0xfe08000c, 0, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0, 131 MFI, 0, ADC, CMT } }, 132 }; 133 134 static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups, 135 priorities, mask_registers, prio_registers, NULL); 136 137 static struct intc_vect vectors_irq[] __initdata = { 138 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), 139 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), 140 }; 141 142 static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups, 143 priorities, mask_registers, prio_registers, NULL); 144 145 static struct plat_sci_port sci_platform_data[] = { 146 { 147 .mapbase = 0xfe600000, 148 .flags = UPF_BOOT_AUTOCONF, 149 .type = PORT_SCIF, 150 .irqs = { 52, 53, 55, 54 }, 151 }, { 152 .mapbase = 0xfe610000, 153 .flags = UPF_BOOT_AUTOCONF, 154 .type = PORT_SCIF, 155 .irqs = { 72, 73, 75, 74 }, 156 }, { 157 .mapbase = 0xfe620000, 158 .flags = UPF_BOOT_AUTOCONF, 159 .type = PORT_SCIF, 160 .irqs = { 76, 77, 79, 78 }, 161 }, { 162 .mapbase = 0xfe480000, 163 .flags = UPF_BOOT_AUTOCONF, 164 .type = PORT_SCI, 165 .irqs = { 80, 81, 82, 0 }, 166 }, { 167 .flags = 0, 168 } 169 }; 170 171 static struct platform_device sci_device = { 172 .name = "sh-sci", 173 .id = -1, 174 .dev = { 175 .platform_data = sci_platform_data, 176 }, 177 }; 178 179 static struct platform_device *sh7760_devices[] __initdata = { 180 &sci_device, 181 }; 182 183 static int __init sh7760_devices_setup(void) 184 { 185 return platform_add_devices(sh7760_devices, 186 ARRAY_SIZE(sh7760_devices)); 187 } 188 __initcall(sh7760_devices_setup); 189 190 void __init plat_irq_setup_pins(int mode) 191 { 192 switch (mode) { 193 case IRQ_MODE_IRQ: 194 register_intc_controller(&intc_desc_irq); 195 break; 196 default: 197 BUG(); 198 } 199 } 200 201 void __init plat_irq_setup(void) 202 { 203 register_intc_controller(&intc_desc); 204 } 205