1 /* 2 * SH7720 Setup 3 * 4 * Copyright (C) 2007 Markus Brunner, Mark Jonas 5 * 6 * Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c: 7 * 8 * Copyright (C) 2006 Paul Mundt 9 * Copyright (C) 2006 Jamie Lenehan 10 * 11 * This file is subject to the terms and conditions of the GNU General Public 12 * License. See the file "COPYING" in the main directory of this archive 13 * for more details. 14 */ 15 #include <linux/platform_device.h> 16 #include <linux/init.h> 17 #include <linux/serial.h> 18 #include <linux/io.h> 19 #include <asm/sci.h> 20 #include <asm/rtc.h> 21 22 #define INTC_ICR1 0xA4140010UL 23 #define INTC_ICR_IRLM 0x4000 24 #define INTC_ICR_IRQ (~INTC_ICR_IRLM) 25 26 static struct resource rtc_resources[] = { 27 [0] = { 28 .start = 0xa413fec0, 29 .end = 0xa413fec0 + 0x28 - 1, 30 .flags = IORESOURCE_IO, 31 }, 32 [1] = { 33 /* Period IRQ */ 34 .start = 21, 35 .flags = IORESOURCE_IRQ, 36 }, 37 [2] = { 38 /* Carry IRQ */ 39 .start = 22, 40 .flags = IORESOURCE_IRQ, 41 }, 42 [3] = { 43 /* Alarm IRQ */ 44 .start = 20, 45 .flags = IORESOURCE_IRQ, 46 }, 47 }; 48 49 static struct sh_rtc_platform_info rtc_info = { 50 .capabilities = RTC_CAP_4_DIGIT_YEAR, 51 }; 52 53 static struct platform_device rtc_device = { 54 .name = "sh-rtc", 55 .id = -1, 56 .num_resources = ARRAY_SIZE(rtc_resources), 57 .resource = rtc_resources, 58 .dev = { 59 .platform_data = &rtc_info, 60 }, 61 }; 62 63 static struct plat_sci_port sci_platform_data[] = { 64 { 65 .mapbase = 0xa4430000, 66 .flags = UPF_BOOT_AUTOCONF, 67 .type = PORT_SCIF, 68 .irqs = { 80, 80, 80, 80 }, 69 }, { 70 .mapbase = 0xa4438000, 71 .flags = UPF_BOOT_AUTOCONF, 72 .type = PORT_SCIF, 73 .irqs = { 81, 81, 81, 81 }, 74 }, { 75 76 .flags = 0, 77 } 78 }; 79 80 static struct platform_device sci_device = { 81 .name = "sh-sci", 82 .id = -1, 83 .dev = { 84 .platform_data = sci_platform_data, 85 }, 86 }; 87 88 static struct platform_device *sh7720_devices[] __initdata = { 89 &rtc_device, 90 &sci_device, 91 }; 92 93 static int __init sh7720_devices_setup(void) 94 { 95 return platform_add_devices(sh7720_devices, 96 ARRAY_SIZE(sh7720_devices)); 97 } 98 __initcall(sh7720_devices_setup); 99 100 enum { 101 UNUSED = 0, 102 103 /* interrupt sources */ 104 TMU0, TMU1, TMU2, RTC_ATI, RTC_PRI, RTC_CUI, 105 WDT, REF_RCMI, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND, 106 IRQ0, IRQ1, IRQ2, IRQ3, 107 USBF_SPD, TMU_SUNI, IRQ5, IRQ4, 108 DMAC1_DEI0, DMAC1_DEI1, DMAC1_DEI2, DMAC1_DEI3, LCDC, SSL, 109 ADC, DMAC2_DEI4, DMAC2_DEI5, USBFI0, USBFI1, CMT, 110 SCIF0, SCIF1, 111 PINT07, PINT815, TPU0, TPU1, TPU2, TPU3, IIC, 112 SIOF0, SIOF1, MMCI0, MMCI1, MMCI2, MMCI3, PCC, 113 USBHI, AFEIF, 114 H_UDI, 115 /* interrupt groups */ 116 TMU, RTC, SIM, DMAC1, USBFI, DMAC2, USB, TPU, MMC, 117 }; 118 119 static struct intc_vect vectors[] __initdata = { 120 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 121 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC_ATI, 0x480), 122 INTC_VECT(RTC_PRI, 0x4a0), INTC_VECT(RTC_CUI, 0x4c0), 123 INTC_VECT(SIM_ERI, 0x4e0), INTC_VECT(SIM_RXI, 0x500), 124 INTC_VECT(SIM_TXI, 0x520), INTC_VECT(SIM_TEND, 0x540), 125 INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580), 126 /* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0), 127 INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1_DEI0, 0x800), 128 INTC_VECT(DMAC1_DEI1, 0x820), INTC_VECT(DMAC1_DEI2, 0x840), 129 INTC_VECT(DMAC1_DEI3, 0x860), INTC_VECT(LCDC, 0x900), 130 INTC_VECT(SSL, 0x980), INTC_VECT(USBFI0, 0xa20), 131 INTC_VECT(USBFI1, 0xa40), INTC_VECT(USBHI, 0xa60), 132 INTC_VECT(DMAC2_DEI4, 0xb80), INTC_VECT(DMAC2_DEI5, 0xba0), 133 INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00), 134 INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80), 135 INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00), 136 INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU0, 0xd80), 137 INTC_VECT(TPU1, 0xda0), INTC_VECT(TPU2, 0xdc0), 138 INTC_VECT(TPU3, 0xde0), INTC_VECT(IIC, 0xe00), 139 INTC_VECT(MMCI0, 0xe80), INTC_VECT(MMCI1, 0xea0), 140 INTC_VECT(MMCI2, 0xec0), INTC_VECT(MMCI3, 0xee0), 141 INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60), 142 INTC_VECT(AFEIF, 0xfe0), 143 }; 144 145 static struct intc_group groups[] __initdata = { 146 INTC_GROUP(TMU, TMU0, TMU1, TMU2), 147 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 148 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND), 149 INTC_GROUP(DMAC1, DMAC1_DEI0, DMAC1_DEI1, DMAC1_DEI2, DMAC1_DEI3), 150 INTC_GROUP(USBFI, USBFI0, USBFI1), 151 INTC_GROUP(DMAC2, DMAC2_DEI4, DMAC2_DEI5), 152 INTC_GROUP(TPU, TPU0, TPU1, TPU2, TPU3), 153 INTC_GROUP(MMC, MMCI0, MMCI1, MMCI2, MMCI3), 154 }; 155 156 static struct intc_prio priorities[] __initdata = { 157 INTC_PRIO(SCIF0, 2), 158 INTC_PRIO(SCIF1, 2), 159 INTC_PRIO(DMAC1, 1), 160 INTC_PRIO(DMAC2, 1), 161 INTC_PRIO(RTC, 2), 162 INTC_PRIO(TMU, 2), 163 INTC_PRIO(TPU, 2), 164 }; 165 166 static struct intc_prio_reg prio_registers[] __initdata = { 167 { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 168 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } }, 169 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 170 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } }, 171 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } }, 172 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } }, 173 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } }, 174 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } }, 175 { 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } }, 176 { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } }, 177 }; 178 179 static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, groups, 180 priorities, NULL, prio_registers, NULL); 181 182 static struct intc_sense_reg sense_registers[] __initdata = { 183 { INTC_ICR1, 16, 2, { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } }, 184 }; 185 186 static struct intc_vect vectors_irq[] __initdata = { 187 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 188 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 189 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 190 }; 191 192 static DECLARE_INTC_DESC(intc_irq_desc, "sh7720-irq", vectors_irq, 193 NULL, priorities, NULL, prio_registers, sense_registers); 194 195 void __init plat_irq_setup_pins(int mode) 196 { 197 switch (mode) { 198 case IRQ_MODE_IRQ: 199 ctrl_outw(ctrl_inw(INTC_ICR1) & INTC_ICR_IRQ, INTC_ICR1); 200 register_intc_controller(&intc_irq_desc); 201 break; 202 default: 203 BUG(); 204 } 205 } 206 207 void __init plat_irq_setup(void) 208 { 209 register_intc_controller(&intc_desc); 210 } 211