19d4436a6SYoshinori Sato /* 29d4436a6SYoshinori Sato * arch/sh/kernel/cpu/sh2a/probe.c 39d4436a6SYoshinori Sato * 49d4436a6SYoshinori Sato * CPU Subtype Probing for SH-2A. 59d4436a6SYoshinori Sato * 66d01f510SPaul Mundt * Copyright (C) 2004 - 2007 Paul Mundt 79d4436a6SYoshinori Sato * 89d4436a6SYoshinori Sato * This file is subject to the terms and conditions of the GNU General Public 99d4436a6SYoshinori Sato * License. See the file "COPYING" in the main directory of this archive 109d4436a6SYoshinori Sato * for more details. 119d4436a6SYoshinori Sato */ 129d4436a6SYoshinori Sato #include <linux/init.h> 139d4436a6SYoshinori Sato #include <asm/processor.h> 149d4436a6SYoshinori Sato #include <asm/cache.h> 159d4436a6SYoshinori Sato 169d4436a6SYoshinori Sato int __init detect_cpu_and_cache_system(void) 179d4436a6SYoshinori Sato { 18*e82da214SPaul Mundt boot_cpu_data.family = CPU_FAMILY_SH2A; 19*e82da214SPaul Mundt 206d01f510SPaul Mundt /* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */ 21cb7af21fSPaul Mundt boot_cpu_data.flags |= CPU_HAS_OP32; 229d4436a6SYoshinori Sato 232825999eSPeter Griffin #if defined(CONFIG_CPU_SUBTYPE_SH7201) 242825999eSPeter Griffin boot_cpu_data.type = CPU_SH7201; 252825999eSPeter Griffin boot_cpu_data.flags |= CPU_HAS_FPU; 262825999eSPeter Griffin #elif defined(CONFIG_CPU_SUBTYPE_SH7203) 276d01f510SPaul Mundt boot_cpu_data.type = CPU_SH7203; 286d01f510SPaul Mundt boot_cpu_data.flags |= CPU_HAS_FPU; 29a8f67f4bSPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_SH7263) 30a8f67f4bSPaul Mundt boot_cpu_data.type = CPU_SH7263; 31a8f67f4bSPaul Mundt boot_cpu_data.flags |= CPU_HAS_FPU; 326d01f510SPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_SH7206) 336d01f510SPaul Mundt boot_cpu_data.type = CPU_SH7206; 346d01f510SPaul Mundt boot_cpu_data.flags |= CPU_HAS_DSP; 352ad69908SPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_MXG) 362ad69908SPaul Mundt boot_cpu_data.type = CPU_MXG; 372ad69908SPaul Mundt boot_cpu_data.flags |= CPU_HAS_DSP; 386d01f510SPaul Mundt #endif 396d01f510SPaul Mundt 40cb7af21fSPaul Mundt boot_cpu_data.dcache.ways = 4; 41cb7af21fSPaul Mundt boot_cpu_data.dcache.way_incr = (1 << 11); 42cb7af21fSPaul Mundt boot_cpu_data.dcache.sets = 128; 43cb7af21fSPaul Mundt boot_cpu_data.dcache.entry_shift = 4; 44cb7af21fSPaul Mundt boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; 45cb7af21fSPaul Mundt boot_cpu_data.dcache.flags = 0; 469d4436a6SYoshinori Sato 479d4436a6SYoshinori Sato /* 489d4436a6SYoshinori Sato * The icache is the same as the dcache as far as this setup is 499d4436a6SYoshinori Sato * concerned. The only real difference in hardware is that the icache 509d4436a6SYoshinori Sato * lacks the U bit that the dcache has, none of this has any bearing 519d4436a6SYoshinori Sato * on the cache info. 529d4436a6SYoshinori Sato */ 53cb7af21fSPaul Mundt boot_cpu_data.icache = boot_cpu_data.dcache; 549d4436a6SYoshinori Sato 559d4436a6SYoshinori Sato return 0; 569d4436a6SYoshinori Sato } 57