1*9d4436a6SYoshinori Sato /* 2*9d4436a6SYoshinori Sato * arch/sh/kernel/cpu/sh2a/probe.c 3*9d4436a6SYoshinori Sato * 4*9d4436a6SYoshinori Sato * CPU Subtype Probing for SH-2A. 5*9d4436a6SYoshinori Sato * 6*9d4436a6SYoshinori Sato * Copyright (C) 2004, 2005 Paul Mundt 7*9d4436a6SYoshinori Sato * 8*9d4436a6SYoshinori Sato * This file is subject to the terms and conditions of the GNU General Public 9*9d4436a6SYoshinori Sato * License. See the file "COPYING" in the main directory of this archive 10*9d4436a6SYoshinori Sato * for more details. 11*9d4436a6SYoshinori Sato */ 12*9d4436a6SYoshinori Sato 13*9d4436a6SYoshinori Sato #include <linux/init.h> 14*9d4436a6SYoshinori Sato #include <asm/processor.h> 15*9d4436a6SYoshinori Sato #include <asm/cache.h> 16*9d4436a6SYoshinori Sato 17*9d4436a6SYoshinori Sato int __init detect_cpu_and_cache_system(void) 18*9d4436a6SYoshinori Sato { 19*9d4436a6SYoshinori Sato /* Just SH7206 for now .. */ 20*9d4436a6SYoshinori Sato cpu_data->type = CPU_SH7206; 21*9d4436a6SYoshinori Sato 22*9d4436a6SYoshinori Sato cpu_data->dcache.ways = 4; 23*9d4436a6SYoshinori Sato cpu_data->dcache.way_incr = (1 << 11); 24*9d4436a6SYoshinori Sato cpu_data->dcache.sets = 128; 25*9d4436a6SYoshinori Sato cpu_data->dcache.entry_shift = 4; 26*9d4436a6SYoshinori Sato cpu_data->dcache.linesz = L1_CACHE_BYTES; 27*9d4436a6SYoshinori Sato cpu_data->dcache.flags = 0; 28*9d4436a6SYoshinori Sato 29*9d4436a6SYoshinori Sato /* 30*9d4436a6SYoshinori Sato * The icache is the same as the dcache as far as this setup is 31*9d4436a6SYoshinori Sato * concerned. The only real difference in hardware is that the icache 32*9d4436a6SYoshinori Sato * lacks the U bit that the dcache has, none of this has any bearing 33*9d4436a6SYoshinori Sato * on the cache info. 34*9d4436a6SYoshinori Sato */ 35*9d4436a6SYoshinori Sato cpu_data->icache = cpu_data->dcache; 36*9d4436a6SYoshinori Sato 37*9d4436a6SYoshinori Sato return 0; 38*9d4436a6SYoshinori Sato } 39*9d4436a6SYoshinori Sato 40