19d4436a6SYoshinori Sato /* 29d4436a6SYoshinori Sato * arch/sh/kernel/cpu/sh2a/probe.c 39d4436a6SYoshinori Sato * 49d4436a6SYoshinori Sato * CPU Subtype Probing for SH-2A. 59d4436a6SYoshinori Sato * 66d01f510SPaul Mundt * Copyright (C) 2004 - 2007 Paul Mundt 79d4436a6SYoshinori Sato * 89d4436a6SYoshinori Sato * This file is subject to the terms and conditions of the GNU General Public 99d4436a6SYoshinori Sato * License. See the file "COPYING" in the main directory of this archive 109d4436a6SYoshinori Sato * for more details. 119d4436a6SYoshinori Sato */ 129d4436a6SYoshinori Sato #include <linux/init.h> 139d4436a6SYoshinori Sato #include <asm/processor.h> 149d4436a6SYoshinori Sato #include <asm/cache.h> 159d4436a6SYoshinori Sato 169d4436a6SYoshinori Sato int __init detect_cpu_and_cache_system(void) 179d4436a6SYoshinori Sato { 186d01f510SPaul Mundt /* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */ 19cb7af21fSPaul Mundt boot_cpu_data.flags |= CPU_HAS_OP32; 209d4436a6SYoshinori Sato 216d01f510SPaul Mundt #if defined(CONFIG_CPU_SUBTYPE_SH7203) 226d01f510SPaul Mundt boot_cpu_data.type = CPU_SH7203; 236d01f510SPaul Mundt /* SH7203 has an FPU.. */ 246d01f510SPaul Mundt boot_cpu_data.flags |= CPU_HAS_FPU; 25a8f67f4bSPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_SH7263) 26a8f67f4bSPaul Mundt boot_cpu_data.type = CPU_SH7263; 27a8f67f4bSPaul Mundt boot_cpu_data.flags |= CPU_HAS_FPU; 286d01f510SPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_SH7206) 296d01f510SPaul Mundt boot_cpu_data.type = CPU_SH7206; 306d01f510SPaul Mundt /* While SH7206 has a DSP.. */ 316d01f510SPaul Mundt boot_cpu_data.flags |= CPU_HAS_DSP; 32*2ad69908SPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_MXG) 33*2ad69908SPaul Mundt boot_cpu_data.type = CPU_MXG; 34*2ad69908SPaul Mundt boot_cpu_data.flags |= CPU_HAS_DSP; 356d01f510SPaul Mundt #endif 366d01f510SPaul Mundt 37cb7af21fSPaul Mundt boot_cpu_data.dcache.ways = 4; 38cb7af21fSPaul Mundt boot_cpu_data.dcache.way_incr = (1 << 11); 39cb7af21fSPaul Mundt boot_cpu_data.dcache.sets = 128; 40cb7af21fSPaul Mundt boot_cpu_data.dcache.entry_shift = 4; 41cb7af21fSPaul Mundt boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; 42cb7af21fSPaul Mundt boot_cpu_data.dcache.flags = 0; 439d4436a6SYoshinori Sato 449d4436a6SYoshinori Sato /* 459d4436a6SYoshinori Sato * The icache is the same as the dcache as far as this setup is 469d4436a6SYoshinori Sato * concerned. The only real difference in hardware is that the icache 479d4436a6SYoshinori Sato * lacks the U bit that the dcache has, none of this has any bearing 489d4436a6SYoshinori Sato * on the cache info. 499d4436a6SYoshinori Sato */ 50cb7af21fSPaul Mundt boot_cpu_data.icache = boot_cpu_data.dcache; 519d4436a6SYoshinori Sato 529d4436a6SYoshinori Sato return 0; 539d4436a6SYoshinori Sato } 54