19d4436a6SYoshinori Sato /* 29d4436a6SYoshinori Sato * arch/sh/kernel/cpu/sh2a/probe.c 39d4436a6SYoshinori Sato * 49d4436a6SYoshinori Sato * CPU Subtype Probing for SH-2A. 59d4436a6SYoshinori Sato * 66d01f510SPaul Mundt * Copyright (C) 2004 - 2007 Paul Mundt 79d4436a6SYoshinori Sato * 89d4436a6SYoshinori Sato * This file is subject to the terms and conditions of the GNU General Public 99d4436a6SYoshinori Sato * License. See the file "COPYING" in the main directory of this archive 109d4436a6SYoshinori Sato * for more details. 119d4436a6SYoshinori Sato */ 129d4436a6SYoshinori Sato #include <linux/init.h> 139d4436a6SYoshinori Sato #include <asm/processor.h> 149d4436a6SYoshinori Sato #include <asm/cache.h> 159d4436a6SYoshinori Sato 16a9079ca0SPaul Mundt void __cpuinit cpu_probe(void) 179d4436a6SYoshinori Sato { 18e82da214SPaul Mundt boot_cpu_data.family = CPU_FAMILY_SH2A; 19e82da214SPaul Mundt 206d01f510SPaul Mundt /* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */ 21cb7af21fSPaul Mundt boot_cpu_data.flags |= CPU_HAS_OP32; 229d4436a6SYoshinori Sato 232825999eSPeter Griffin #if defined(CONFIG_CPU_SUBTYPE_SH7201) 242825999eSPeter Griffin boot_cpu_data.type = CPU_SH7201; 252825999eSPeter Griffin boot_cpu_data.flags |= CPU_HAS_FPU; 262825999eSPeter Griffin #elif defined(CONFIG_CPU_SUBTYPE_SH7203) 276d01f510SPaul Mundt boot_cpu_data.type = CPU_SH7203; 286d01f510SPaul Mundt boot_cpu_data.flags |= CPU_HAS_FPU; 29a8f67f4bSPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_SH7263) 30a8f67f4bSPaul Mundt boot_cpu_data.type = CPU_SH7263; 31a8f67f4bSPaul Mundt boot_cpu_data.flags |= CPU_HAS_FPU; 3251ce3068SPhil Edworthy #elif defined(CONFIG_CPU_SUBTYPE_SH7264) 3351ce3068SPhil Edworthy boot_cpu_data.type = CPU_SH7264; 3451ce3068SPhil Edworthy boot_cpu_data.flags |= CPU_HAS_FPU; 35*0b25b7c8SPhil Edworthy #elif defined(CONFIG_CPU_SUBTYPE_SH7269) 36*0b25b7c8SPhil Edworthy boot_cpu_data.type = CPU_SH7269; 37*0b25b7c8SPhil Edworthy boot_cpu_data.flags |= CPU_HAS_FPU; 386d01f510SPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_SH7206) 396d01f510SPaul Mundt boot_cpu_data.type = CPU_SH7206; 406d01f510SPaul Mundt boot_cpu_data.flags |= CPU_HAS_DSP; 412ad69908SPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_MXG) 422ad69908SPaul Mundt boot_cpu_data.type = CPU_MXG; 432ad69908SPaul Mundt boot_cpu_data.flags |= CPU_HAS_DSP; 446d01f510SPaul Mundt #endif 456d01f510SPaul Mundt 46cb7af21fSPaul Mundt boot_cpu_data.dcache.ways = 4; 47cb7af21fSPaul Mundt boot_cpu_data.dcache.way_incr = (1 << 11); 48cb7af21fSPaul Mundt boot_cpu_data.dcache.sets = 128; 49cb7af21fSPaul Mundt boot_cpu_data.dcache.entry_shift = 4; 50cb7af21fSPaul Mundt boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; 51cb7af21fSPaul Mundt boot_cpu_data.dcache.flags = 0; 529d4436a6SYoshinori Sato 539d4436a6SYoshinori Sato /* 549d4436a6SYoshinori Sato * The icache is the same as the dcache as far as this setup is 559d4436a6SYoshinori Sato * concerned. The only real difference in hardware is that the icache 569d4436a6SYoshinori Sato * lacks the U bit that the dcache has, none of this has any bearing 579d4436a6SYoshinori Sato * on the cache info. 589d4436a6SYoshinori Sato */ 59cb7af21fSPaul Mundt boot_cpu_data.icache = boot_cpu_data.dcache; 609d4436a6SYoshinori Sato } 61