1*234a0538SKuninori Morimoto // SPDX-License-Identifier: GPL-2.0 29d4436a6SYoshinori Sato /* 39d4436a6SYoshinori Sato * arch/sh/kernel/cpu/sh2a/probe.c 49d4436a6SYoshinori Sato * 59d4436a6SYoshinori Sato * CPU Subtype Probing for SH-2A. 69d4436a6SYoshinori Sato * 76d01f510SPaul Mundt * Copyright (C) 2004 - 2007 Paul Mundt 89d4436a6SYoshinori Sato */ 99d4436a6SYoshinori Sato #include <linux/init.h> 109d4436a6SYoshinori Sato #include <asm/processor.h> 119d4436a6SYoshinori Sato #include <asm/cache.h> 129d4436a6SYoshinori Sato cpu_probe(void)134603f53aSPaul Gortmakervoid cpu_probe(void) 149d4436a6SYoshinori Sato { 15e82da214SPaul Mundt boot_cpu_data.family = CPU_FAMILY_SH2A; 16e82da214SPaul Mundt 176d01f510SPaul Mundt /* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */ 18cb7af21fSPaul Mundt boot_cpu_data.flags |= CPU_HAS_OP32; 199d4436a6SYoshinori Sato 202825999eSPeter Griffin #if defined(CONFIG_CPU_SUBTYPE_SH7201) 212825999eSPeter Griffin boot_cpu_data.type = CPU_SH7201; 222825999eSPeter Griffin boot_cpu_data.flags |= CPU_HAS_FPU; 232825999eSPeter Griffin #elif defined(CONFIG_CPU_SUBTYPE_SH7203) 246d01f510SPaul Mundt boot_cpu_data.type = CPU_SH7203; 256d01f510SPaul Mundt boot_cpu_data.flags |= CPU_HAS_FPU; 26a8f67f4bSPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_SH7263) 27a8f67f4bSPaul Mundt boot_cpu_data.type = CPU_SH7263; 28a8f67f4bSPaul Mundt boot_cpu_data.flags |= CPU_HAS_FPU; 2951ce3068SPhil Edworthy #elif defined(CONFIG_CPU_SUBTYPE_SH7264) 3051ce3068SPhil Edworthy boot_cpu_data.type = CPU_SH7264; 3151ce3068SPhil Edworthy boot_cpu_data.flags |= CPU_HAS_FPU; 320b25b7c8SPhil Edworthy #elif defined(CONFIG_CPU_SUBTYPE_SH7269) 330b25b7c8SPhil Edworthy boot_cpu_data.type = CPU_SH7269; 340b25b7c8SPhil Edworthy boot_cpu_data.flags |= CPU_HAS_FPU; 356d01f510SPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_SH7206) 366d01f510SPaul Mundt boot_cpu_data.type = CPU_SH7206; 376d01f510SPaul Mundt boot_cpu_data.flags |= CPU_HAS_DSP; 382ad69908SPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_MXG) 392ad69908SPaul Mundt boot_cpu_data.type = CPU_MXG; 402ad69908SPaul Mundt boot_cpu_data.flags |= CPU_HAS_DSP; 416d01f510SPaul Mundt #endif 426d01f510SPaul Mundt 43cb7af21fSPaul Mundt boot_cpu_data.dcache.ways = 4; 44cb7af21fSPaul Mundt boot_cpu_data.dcache.way_incr = (1 << 11); 45cb7af21fSPaul Mundt boot_cpu_data.dcache.sets = 128; 46cb7af21fSPaul Mundt boot_cpu_data.dcache.entry_shift = 4; 47cb7af21fSPaul Mundt boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; 48cb7af21fSPaul Mundt boot_cpu_data.dcache.flags = 0; 499d4436a6SYoshinori Sato 509d4436a6SYoshinori Sato /* 519d4436a6SYoshinori Sato * The icache is the same as the dcache as far as this setup is 529d4436a6SYoshinori Sato * concerned. The only real difference in hardware is that the icache 539d4436a6SYoshinori Sato * lacks the U bit that the dcache has, none of this has any bearing 549d4436a6SYoshinori Sato * on the cache info. 559d4436a6SYoshinori Sato */ 56cb7af21fSPaul Mundt boot_cpu_data.icache = boot_cpu_data.dcache; 579d4436a6SYoshinori Sato } 58