1 /* 2 * arch/sh/kernel/cpu/init.c 3 * 4 * CPU init code 5 * 6 * Copyright (C) 2002, 2003 Paul Mundt 7 * Copyright (C) 2003 Richard Curnow 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13 #include <linux/init.h> 14 #include <linux/kernel.h> 15 #include <asm/processor.h> 16 #include <asm/uaccess.h> 17 #include <asm/page.h> 18 #include <asm/system.h> 19 #include <asm/cacheflush.h> 20 #include <asm/cache.h> 21 #include <asm/io.h> 22 23 extern void detect_cpu_and_cache_system(void); 24 25 /* 26 * Generic wrapper for command line arguments to disable on-chip 27 * peripherals (nofpu, nodsp, and so forth). 28 */ 29 #define onchip_setup(x) \ 30 static int x##_disabled __initdata = 0; \ 31 \ 32 static int __init x##_setup(char *opts) \ 33 { \ 34 x##_disabled = 1; \ 35 return 1; \ 36 } \ 37 __setup("no" __stringify(x), x##_setup); 38 39 onchip_setup(fpu); 40 onchip_setup(dsp); 41 42 /* 43 * Generic first-level cache init 44 */ 45 static void __init cache_init(void) 46 { 47 unsigned long ccr, flags; 48 49 if (cpu_data->type == CPU_SH_NONE) 50 panic("Unknown CPU"); 51 52 jump_to_P2(); 53 ccr = ctrl_inl(CCR); 54 55 /* 56 * At this point we don't know whether the cache is enabled or not - a 57 * bootloader may have enabled it. There are at least 2 things that 58 * could be dirty in the cache at this point: 59 * 1. kernel command line set up by boot loader 60 * 2. spilled registers from the prolog of this function 61 * => before re-initialising the cache, we must do a purge of the whole 62 * cache out to memory for safety. As long as nothing is spilled 63 * during the loop to lines that have already been done, this is safe. 64 * - RPC 65 */ 66 if (ccr & CCR_CACHE_ENABLE) { 67 unsigned long ways, waysize, addrstart; 68 69 waysize = cpu_data->dcache.sets; 70 71 /* 72 * If the OC is already in RAM mode, we only have 73 * half of the entries to flush.. 74 */ 75 if (ccr & CCR_CACHE_ORA) 76 waysize >>= 1; 77 78 waysize <<= cpu_data->dcache.entry_shift; 79 80 #ifdef CCR_CACHE_EMODE 81 /* If EMODE is not set, we only have 1 way to flush. */ 82 if (!(ccr & CCR_CACHE_EMODE)) 83 ways = 1; 84 else 85 #endif 86 ways = cpu_data->dcache.ways; 87 88 addrstart = CACHE_OC_ADDRESS_ARRAY; 89 do { 90 unsigned long addr; 91 92 for (addr = addrstart; 93 addr < addrstart + waysize; 94 addr += cpu_data->dcache.linesz) 95 ctrl_outl(0, addr); 96 97 addrstart += cpu_data->dcache.way_incr; 98 } while (--ways); 99 } 100 101 /* 102 * Default CCR values .. enable the caches 103 * and invalidate them immediately.. 104 */ 105 flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE; 106 107 #ifdef CCR_CACHE_EMODE 108 /* Force EMODE if possible */ 109 if (cpu_data->dcache.ways > 1) 110 flags |= CCR_CACHE_EMODE; 111 else 112 flags &= ~CCR_CACHE_EMODE; 113 #endif 114 115 #ifdef CONFIG_SH_WRITETHROUGH 116 /* Turn on Write-through caching */ 117 flags |= CCR_CACHE_WT; 118 #else 119 /* .. or default to Write-back */ 120 flags |= CCR_CACHE_CB; 121 #endif 122 123 #ifdef CONFIG_SH_OCRAM 124 /* Turn on OCRAM -- halve the OC */ 125 flags |= CCR_CACHE_ORA; 126 cpu_data->dcache.sets >>= 1; 127 128 cpu_data->dcache.way_size = cpu_data->dcache.sets * 129 cpu_data->dcache.linesz; 130 #endif 131 132 ctrl_outl(flags, CCR); 133 back_to_P1(); 134 } 135 136 #ifdef CONFIG_SH_DSP 137 static void __init release_dsp(void) 138 { 139 unsigned long sr; 140 141 /* Clear SR.DSP bit */ 142 __asm__ __volatile__ ( 143 "stc\tsr, %0\n\t" 144 "and\t%1, %0\n\t" 145 "ldc\t%0, sr\n\t" 146 : "=&r" (sr) 147 : "r" (~SR_DSP) 148 ); 149 } 150 151 static void __init dsp_init(void) 152 { 153 unsigned long sr; 154 155 /* 156 * Set the SR.DSP bit, wait for one instruction, and then read 157 * back the SR value. 158 */ 159 __asm__ __volatile__ ( 160 "stc\tsr, %0\n\t" 161 "or\t%1, %0\n\t" 162 "ldc\t%0, sr\n\t" 163 "nop\n\t" 164 "stc\tsr, %0\n\t" 165 : "=&r" (sr) 166 : "r" (SR_DSP) 167 ); 168 169 /* If the DSP bit is still set, this CPU has a DSP */ 170 if (sr & SR_DSP) 171 cpu_data->flags |= CPU_HAS_DSP; 172 173 /* Now that we've determined the DSP status, clear the DSP bit. */ 174 release_dsp(); 175 } 176 #endif /* CONFIG_SH_DSP */ 177 178 /** 179 * sh_cpu_init 180 * 181 * This is our initial entry point for each CPU, and is invoked on the boot 182 * CPU prior to calling start_kernel(). For SMP, a combination of this and 183 * start_secondary() will bring up each processor to a ready state prior 184 * to hand forking the idle loop. 185 * 186 * We do all of the basic processor init here, including setting up the 187 * caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is 188 * hit (and subsequently platform_setup()) things like determining the 189 * CPU subtype and initial configuration will all be done. 190 * 191 * Each processor family is still responsible for doing its own probing 192 * and cache configuration in detect_cpu_and_cache_system(). 193 */ 194 asmlinkage void __init sh_cpu_init(void) 195 { 196 /* First, probe the CPU */ 197 detect_cpu_and_cache_system(); 198 199 /* Init the cache */ 200 cache_init(); 201 202 shm_align_mask = max_t(unsigned long, 203 cpu_data->dcache.way_size - 1, 204 PAGE_SIZE - 1); 205 206 /* Disable the FPU */ 207 if (fpu_disabled) { 208 printk("FPU Disabled\n"); 209 cpu_data->flags &= ~CPU_HAS_FPU; 210 disable_fpu(); 211 } 212 213 /* FPU initialization */ 214 if ((cpu_data->flags & CPU_HAS_FPU)) { 215 clear_thread_flag(TIF_USEDFPU); 216 clear_used_math(); 217 } 218 219 #ifdef CONFIG_SH_DSP 220 /* Probe for DSP */ 221 dsp_init(); 222 223 /* Disable the DSP */ 224 if (dsp_disabled) { 225 printk("DSP Disabled\n"); 226 cpu_data->flags &= ~CPU_HAS_DSP; 227 release_dsp(); 228 } 229 #endif 230 231 #ifdef CONFIG_UBC_WAKEUP 232 /* 233 * Some brain-damaged loaders decided it would be a good idea to put 234 * the UBC to sleep. This causes some issues when it comes to things 235 * like PTRACE_SINGLESTEP or doing hardware watchpoints in GDB. So .. 236 * we wake it up and hope that all is well. 237 */ 238 ubc_wakeup(); 239 #endif 240 } 241 242