1*939a24a6SPaul Mundt #ifndef __ASM_SH_HITACHI_7751SE_H 2*939a24a6SPaul Mundt #define __ASM_SH_HITACHI_7751SE_H 3*939a24a6SPaul Mundt 4*939a24a6SPaul Mundt /* 5*939a24a6SPaul Mundt * linux/include/asm-sh/hitachi_7751se.h 6*939a24a6SPaul Mundt * 7*939a24a6SPaul Mundt * Copyright (C) 2000 Kazumoto Kojima 8*939a24a6SPaul Mundt * 9*939a24a6SPaul Mundt * Hitachi SolutionEngine support 10*939a24a6SPaul Mundt 11*939a24a6SPaul Mundt * Modified for 7751 Solution Engine by 12*939a24a6SPaul Mundt * Ian da Silva and Jeremy Siegel, 2001. 13*939a24a6SPaul Mundt */ 14*939a24a6SPaul Mundt 15*939a24a6SPaul Mundt /* Box specific addresses. */ 16*939a24a6SPaul Mundt 17*939a24a6SPaul Mundt #define PA_ROM 0x00000000 /* EPROM */ 18*939a24a6SPaul Mundt #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ 19*939a24a6SPaul Mundt #define PA_FROM 0x01000000 /* EPROM */ 20*939a24a6SPaul Mundt #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ 21*939a24a6SPaul Mundt #define PA_EXT1 0x04000000 22*939a24a6SPaul Mundt #define PA_EXT1_SIZE 0x04000000 23*939a24a6SPaul Mundt #define PA_EXT2 0x08000000 24*939a24a6SPaul Mundt #define PA_EXT2_SIZE 0x04000000 25*939a24a6SPaul Mundt #define PA_SDRAM 0x0c000000 26*939a24a6SPaul Mundt #define PA_SDRAM_SIZE 0x04000000 27*939a24a6SPaul Mundt 28*939a24a6SPaul Mundt #define PA_EXT4 0x12000000 29*939a24a6SPaul Mundt #define PA_EXT4_SIZE 0x02000000 30*939a24a6SPaul Mundt #define PA_EXT5 0x14000000 31*939a24a6SPaul Mundt #define PA_EXT5_SIZE 0x04000000 32*939a24a6SPaul Mundt #define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ 33*939a24a6SPaul Mundt 34*939a24a6SPaul Mundt #define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */ 35*939a24a6SPaul Mundt #define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */ 36*939a24a6SPaul Mundt #define PA_LED 0xba000000 /* LED */ 37*939a24a6SPaul Mundt #define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */ 38*939a24a6SPaul Mundt 39*939a24a6SPaul Mundt #define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */ 40*939a24a6SPaul Mundt #define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ 41*939a24a6SPaul Mundt #define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ 42*939a24a6SPaul Mundt #define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ 43*939a24a6SPaul Mundt #define MRSHPC_MODE (PA_MRSHPC + 4) 44*939a24a6SPaul Mundt #define MRSHPC_OPTION (PA_MRSHPC + 6) 45*939a24a6SPaul Mundt #define MRSHPC_CSR (PA_MRSHPC + 8) 46*939a24a6SPaul Mundt #define MRSHPC_ISR (PA_MRSHPC + 10) 47*939a24a6SPaul Mundt #define MRSHPC_ICR (PA_MRSHPC + 12) 48*939a24a6SPaul Mundt #define MRSHPC_CPWCR (PA_MRSHPC + 14) 49*939a24a6SPaul Mundt #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) 50*939a24a6SPaul Mundt #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) 51*939a24a6SPaul Mundt #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) 52*939a24a6SPaul Mundt #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) 53*939a24a6SPaul Mundt #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) 54*939a24a6SPaul Mundt #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) 55*939a24a6SPaul Mundt #define MRSHPC_CDCR (PA_MRSHPC + 28) 56*939a24a6SPaul Mundt #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) 57*939a24a6SPaul Mundt 58*939a24a6SPaul Mundt #define BCR_ILCRA (PA_BCR + 0) 59*939a24a6SPaul Mundt #define BCR_ILCRB (PA_BCR + 2) 60*939a24a6SPaul Mundt #define BCR_ILCRC (PA_BCR + 4) 61*939a24a6SPaul Mundt #define BCR_ILCRD (PA_BCR + 6) 62*939a24a6SPaul Mundt #define BCR_ILCRE (PA_BCR + 8) 63*939a24a6SPaul Mundt #define BCR_ILCRF (PA_BCR + 10) 64*939a24a6SPaul Mundt #define BCR_ILCRG (PA_BCR + 12) 65*939a24a6SPaul Mundt 66*939a24a6SPaul Mundt #define IRQ_79C973 13 67*939a24a6SPaul Mundt 68*939a24a6SPaul Mundt void init_7751se_IRQ(void); 69*939a24a6SPaul Mundt 70*939a24a6SPaul Mundt #define __IO_PREFIX sh7751se 71*939a24a6SPaul Mundt #include <asm/io_generic.h> 72*939a24a6SPaul Mundt 73*939a24a6SPaul Mundt #endif /* __ASM_SH_HITACHI_7751SE_H */ 74