1*f15cbe6fSPaul Mundt /* include/asm-sh/dreamcast/sysasic.h 2*f15cbe6fSPaul Mundt * 3*f15cbe6fSPaul Mundt * Definitions for the Dreamcast System ASIC and related peripherals. 4*f15cbe6fSPaul Mundt * 5*f15cbe6fSPaul Mundt * Copyright (c) 2001 M. R. Brown <mrbrown@linuxdc.org> 6*f15cbe6fSPaul Mundt * Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org> 7*f15cbe6fSPaul Mundt * 8*f15cbe6fSPaul Mundt * This file is part of the LinuxDC project (www.linuxdc.org) 9*f15cbe6fSPaul Mundt * 10*f15cbe6fSPaul Mundt * Released under the terms of the GNU GPL v2.0. 11*f15cbe6fSPaul Mundt * 12*f15cbe6fSPaul Mundt */ 13*f15cbe6fSPaul Mundt #ifndef __ASM_SH_DREAMCAST_SYSASIC_H 14*f15cbe6fSPaul Mundt #define __ASM_SH_DREAMCAST_SYSASIC_H 15*f15cbe6fSPaul Mundt 16*f15cbe6fSPaul Mundt #include <asm/irq.h> 17*f15cbe6fSPaul Mundt 18*f15cbe6fSPaul Mundt /* Hardware events - 19*f15cbe6fSPaul Mundt 20*f15cbe6fSPaul Mundt Each of these events correspond to a bit within the Event Mask Registers/ 21*f15cbe6fSPaul Mundt Event Status Registers. Because of the virtual IRQ numbering scheme, a 22*f15cbe6fSPaul Mundt base offset must be used when calculating the virtual IRQ that each event 23*f15cbe6fSPaul Mundt takes. 24*f15cbe6fSPaul Mundt */ 25*f15cbe6fSPaul Mundt 26*f15cbe6fSPaul Mundt #define HW_EVENT_IRQ_BASE 48 27*f15cbe6fSPaul Mundt 28*f15cbe6fSPaul Mundt /* IRQ 13 */ 29*f15cbe6fSPaul Mundt #define HW_EVENT_VSYNC (HW_EVENT_IRQ_BASE + 5) /* VSync */ 30*f15cbe6fSPaul Mundt #define HW_EVENT_MAPLE_DMA (HW_EVENT_IRQ_BASE + 12) /* Maple DMA complete */ 31*f15cbe6fSPaul Mundt #define HW_EVENT_GDROM_DMA (HW_EVENT_IRQ_BASE + 14) /* GD-ROM DMA complete */ 32*f15cbe6fSPaul Mundt #define HW_EVENT_G2_DMA (HW_EVENT_IRQ_BASE + 15) /* G2 DMA complete */ 33*f15cbe6fSPaul Mundt #define HW_EVENT_PVR2_DMA (HW_EVENT_IRQ_BASE + 19) /* PVR2 DMA complete */ 34*f15cbe6fSPaul Mundt 35*f15cbe6fSPaul Mundt /* IRQ 11 */ 36*f15cbe6fSPaul Mundt #define HW_EVENT_GDROM_CMD (HW_EVENT_IRQ_BASE + 32) /* GD-ROM cmd. complete */ 37*f15cbe6fSPaul Mundt #define HW_EVENT_AICA_SYS (HW_EVENT_IRQ_BASE + 33) /* AICA-related */ 38*f15cbe6fSPaul Mundt #define HW_EVENT_EXTERNAL (HW_EVENT_IRQ_BASE + 35) /* Ext. (expansion) */ 39*f15cbe6fSPaul Mundt 40*f15cbe6fSPaul Mundt #define HW_EVENT_IRQ_MAX (HW_EVENT_IRQ_BASE + 95) 41*f15cbe6fSPaul Mundt 42*f15cbe6fSPaul Mundt #endif /* __ASM_SH_DREAMCAST_SYSASIC_H */ 43*f15cbe6fSPaul Mundt 44