1*6a0abce4SKuninori Morimoto /* SPDX-License-Identifier: GPL-2.0 2*6a0abce4SKuninori Morimoto * 3f15cbe6fSPaul Mundt * include/asm-sh/cpu-sh4/mmu_context.h 4f15cbe6fSPaul Mundt * 5f15cbe6fSPaul Mundt * Copyright (C) 1999 Niibe Yutaka 6f15cbe6fSPaul Mundt */ 7f15cbe6fSPaul Mundt #ifndef __ASM_CPU_SH4_MMU_CONTEXT_H 8f15cbe6fSPaul Mundt #define __ASM_CPU_SH4_MMU_CONTEXT_H 9f15cbe6fSPaul Mundt 10f15cbe6fSPaul Mundt #define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */ 11f15cbe6fSPaul Mundt #define MMU_PTEL 0xFF000004 /* Page table entry register LOW */ 12f15cbe6fSPaul Mundt #define MMU_TTB 0xFF000008 /* Translation table base register */ 13f15cbe6fSPaul Mundt #define MMU_TEA 0xFF00000C /* TLB Exception Address */ 148263a67eSPaul Mundt #define MMU_PTEA 0xFF000034 /* PTE assistance register */ 158263a67eSPaul Mundt #define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */ 16f15cbe6fSPaul Mundt 17f15cbe6fSPaul Mundt #define MMUCR 0xFF000010 /* MMU Control Register */ 18f15cbe6fSPaul Mundt 196ae66502SMatt Fleming #define MMU_TLB_ENTRY_SHIFT 8 206ae66502SMatt Fleming 21a9eb4f6dSMatt Fleming #define MMU_ITLB_ADDRESS_ARRAY 0xF2000000 22a9eb4f6dSMatt Fleming #define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000 236ae66502SMatt Fleming #define MMU_ITLB_DATA_ARRAY 0xF3000000 246ae66502SMatt Fleming #define MMU_ITLB_DATA_ARRAY2 0xF3800000 256ae66502SMatt Fleming 26f15cbe6fSPaul Mundt #define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 278263a67eSPaul Mundt #define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000 286ae66502SMatt Fleming #define MMU_UTLB_DATA_ARRAY 0xF7000000 296ae66502SMatt Fleming #define MMU_UTLB_DATA_ARRAY2 0xF7800000 30f15cbe6fSPaul Mundt #define MMU_PAGE_ASSOC_BIT 0x80 31f15cbe6fSPaul Mundt 3299dc5c0cSPaul Mundt #ifdef CONFIG_MMU 3399dc5c0cSPaul Mundt #define MMUCR_AT (1 << 0) 3499dc5c0cSPaul Mundt #else 3599dc5c0cSPaul Mundt #define MMUCR_AT (0) 3699dc5c0cSPaul Mundt #endif 3799dc5c0cSPaul Mundt 38f15cbe6fSPaul Mundt #define MMUCR_TI (1 << 2) 39f15cbe6fSPaul Mundt 408eda5514SMatt Fleming #define MMUCR_URB 0x00FC0000 418eda5514SMatt Fleming #define MMUCR_URB_SHIFT 18 428eda5514SMatt Fleming #define MMUCR_URB_NENTRIES 64 434539282dSMatt Fleming #define MMUCR_URC 0x0000FC00 444539282dSMatt Fleming #define MMUCR_URC_SHIFT 10 458eda5514SMatt Fleming 46f15cbe6fSPaul Mundt #if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40) 47f15cbe6fSPaul Mundt #define MMUCR_SE (1 << 4) 48f15cbe6fSPaul Mundt #else 49f15cbe6fSPaul Mundt #define MMUCR_SE (0) 50f15cbe6fSPaul Mundt #endif 51f15cbe6fSPaul Mundt 528263a67eSPaul Mundt #ifdef CONFIG_CPU_HAS_PTEAEX 538263a67eSPaul Mundt #define MMUCR_AEX (1 << 6) 548263a67eSPaul Mundt #else 558263a67eSPaul Mundt #define MMUCR_AEX (0) 568263a67eSPaul Mundt #endif 578263a67eSPaul Mundt 588263a67eSPaul Mundt #ifdef CONFIG_X2TLB 598263a67eSPaul Mundt #define MMUCR_ME (1 << 7) 608263a67eSPaul Mundt #else 618263a67eSPaul Mundt #define MMUCR_ME (0) 628263a67eSPaul Mundt #endif 638263a67eSPaul Mundt 64f15cbe6fSPaul Mundt #ifdef CONFIG_SH_STORE_QUEUES 65f15cbe6fSPaul Mundt #define MMUCR_SQMD (1 << 9) 66f15cbe6fSPaul Mundt #else 67f15cbe6fSPaul Mundt #define MMUCR_SQMD (0) 68f15cbe6fSPaul Mundt #endif 69f15cbe6fSPaul Mundt 70f15cbe6fSPaul Mundt #define MMU_NTLB_ENTRIES 64 7199dc5c0cSPaul Mundt #define MMU_CONTROL_INIT (MMUCR_AT | MMUCR_TI | MMUCR_SQMD | \ 7299dc5c0cSPaul Mundt MMUCR_ME | MMUCR_SE | MMUCR_AEX) 73f15cbe6fSPaul Mundt 74f15cbe6fSPaul Mundt #define TRA 0xff000020 75f15cbe6fSPaul Mundt #define EXPEVT 0xff000024 76f15cbe6fSPaul Mundt #define INTEVT 0xff000028 77f15cbe6fSPaul Mundt 78f15cbe6fSPaul Mundt #endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */ 79f15cbe6fSPaul Mundt 80