1*f15cbe6fSPaul Mundt /* 2*f15cbe6fSPaul Mundt * include/asm-sh/cpu-sh4/freq.h 3*f15cbe6fSPaul Mundt * 4*f15cbe6fSPaul Mundt * Copyright (C) 2002, 2003 Paul Mundt 5*f15cbe6fSPaul Mundt * 6*f15cbe6fSPaul Mundt * This file is subject to the terms and conditions of the GNU General Public 7*f15cbe6fSPaul Mundt * License. See the file "COPYING" in the main directory of this archive 8*f15cbe6fSPaul Mundt * for more details. 9*f15cbe6fSPaul Mundt */ 10*f15cbe6fSPaul Mundt #ifndef __ASM_CPU_SH4_FREQ_H 11*f15cbe6fSPaul Mundt #define __ASM_CPU_SH4_FREQ_H 12*f15cbe6fSPaul Mundt 13*f15cbe6fSPaul Mundt #if defined(CONFIG_CPU_SUBTYPE_SH7722) || \ 14*f15cbe6fSPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7723) || \ 15*f15cbe6fSPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7343) || \ 16*f15cbe6fSPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7366) 17*f15cbe6fSPaul Mundt #define FRQCR 0xa4150000 18*f15cbe6fSPaul Mundt #define VCLKCR 0xa4150004 19*f15cbe6fSPaul Mundt #define SCLKACR 0xa4150008 20*f15cbe6fSPaul Mundt #define SCLKBCR 0xa415000c 21*f15cbe6fSPaul Mundt #define IrDACLKCR 0xa4150010 22*f15cbe6fSPaul Mundt #define MSTPCR0 0xa4150030 23*f15cbe6fSPaul Mundt #define MSTPCR1 0xa4150034 24*f15cbe6fSPaul Mundt #define MSTPCR2 0xa4150038 25*f15cbe6fSPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 26*f15cbe6fSPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7780) 27*f15cbe6fSPaul Mundt #define FRQCR 0xffc80000 28*f15cbe6fSPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_SH7785) 29*f15cbe6fSPaul Mundt #define FRQCR0 0xffc80000 30*f15cbe6fSPaul Mundt #define FRQCR1 0xffc80004 31*f15cbe6fSPaul Mundt #define FRQMR1 0xffc80014 32*f15cbe6fSPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_SHX3) 33*f15cbe6fSPaul Mundt #define FRQCR 0xffc00014 34*f15cbe6fSPaul Mundt #else 35*f15cbe6fSPaul Mundt #define FRQCR 0xffc00000 36*f15cbe6fSPaul Mundt #define FRQCR_PSTBY 0x0200 37*f15cbe6fSPaul Mundt #define FRQCR_PLLEN 0x0400 38*f15cbe6fSPaul Mundt #define FRQCR_CKOEN 0x0800 39*f15cbe6fSPaul Mundt #endif 40*f15cbe6fSPaul Mundt #define MIN_DIVISOR_NR 0 41*f15cbe6fSPaul Mundt #define MAX_DIVISOR_NR 3 42*f15cbe6fSPaul Mundt 43*f15cbe6fSPaul Mundt #endif /* __ASM_CPU_SH4_FREQ_H */ 44*f15cbe6fSPaul Mundt 45