1f15cbe6fSPaul Mundt /* 2f15cbe6fSPaul Mundt * include/asm-sh/cpu-sh4/freq.h 3f15cbe6fSPaul Mundt * 4f15cbe6fSPaul Mundt * Copyright (C) 2002, 2003 Paul Mundt 5f15cbe6fSPaul Mundt * 6f15cbe6fSPaul Mundt * This file is subject to the terms and conditions of the GNU General Public 7f15cbe6fSPaul Mundt * License. See the file "COPYING" in the main directory of this archive 8f15cbe6fSPaul Mundt * for more details. 9f15cbe6fSPaul Mundt */ 10f15cbe6fSPaul Mundt #ifndef __ASM_CPU_SH4_FREQ_H 11f15cbe6fSPaul Mundt #define __ASM_CPU_SH4_FREQ_H 12f15cbe6fSPaul Mundt 13f15cbe6fSPaul Mundt #if defined(CONFIG_CPU_SUBTYPE_SH7722) || \ 14f15cbe6fSPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7723) || \ 15f15cbe6fSPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7343) || \ 16f15cbe6fSPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7366) 17f15cbe6fSPaul Mundt #define FRQCR 0xa4150000 18f15cbe6fSPaul Mundt #define VCLKCR 0xa4150004 19f15cbe6fSPaul Mundt #define SCLKACR 0xa4150008 20f15cbe6fSPaul Mundt #define SCLKBCR 0xa415000c 21f15cbe6fSPaul Mundt #define IrDACLKCR 0xa4150010 22f15cbe6fSPaul Mundt #define MSTPCR0 0xa4150030 23f15cbe6fSPaul Mundt #define MSTPCR1 0xa4150034 24f15cbe6fSPaul Mundt #define MSTPCR2 0xa4150038 25f15cbe6fSPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 26f15cbe6fSPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7780) 27f15cbe6fSPaul Mundt #define FRQCR 0xffc80000 28f15cbe6fSPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_SH7785) 29f15cbe6fSPaul Mundt #define FRQCR0 0xffc80000 30f15cbe6fSPaul Mundt #define FRQCR1 0xffc80004 31f15cbe6fSPaul Mundt #define FRQMR1 0xffc80014 32*55ba99ebSKuninori Morimoto #elif defined(CONFIG_CPU_SUBTYPE_SH7786) 33*55ba99ebSKuninori Morimoto #define FRQCR0 0xffc40000 34*55ba99ebSKuninori Morimoto #define FRQCR1 0xffc40004 35*55ba99ebSKuninori Morimoto #define FRQMR1 0xffc40014 36f15cbe6fSPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_SHX3) 37f15cbe6fSPaul Mundt #define FRQCR 0xffc00014 38f15cbe6fSPaul Mundt #else 39f15cbe6fSPaul Mundt #define FRQCR 0xffc00000 40f15cbe6fSPaul Mundt #define FRQCR_PSTBY 0x0200 41f15cbe6fSPaul Mundt #define FRQCR_PLLEN 0x0400 42f15cbe6fSPaul Mundt #define FRQCR_CKOEN 0x0800 43f15cbe6fSPaul Mundt #endif 44f15cbe6fSPaul Mundt #define MIN_DIVISOR_NR 0 45f15cbe6fSPaul Mundt #define MAX_DIVISOR_NR 3 46f15cbe6fSPaul Mundt 47f15cbe6fSPaul Mundt #endif /* __ASM_CPU_SH4_FREQ_H */ 48f15cbe6fSPaul Mundt 49