1*6a0abce4SKuninori Morimoto /* SPDX-License-Identifier: GPL-2.0 2*6a0abce4SKuninori Morimoto * 3f15cbe6fSPaul Mundt * include/asm-sh/cpu-sh4/freq.h 4f15cbe6fSPaul Mundt * 5f15cbe6fSPaul Mundt * Copyright (C) 2002, 2003 Paul Mundt 6f15cbe6fSPaul Mundt */ 7f15cbe6fSPaul Mundt #ifndef __ASM_CPU_SH4_FREQ_H 8f15cbe6fSPaul Mundt #define __ASM_CPU_SH4_FREQ_H 9f15cbe6fSPaul Mundt 10f15cbe6fSPaul Mundt #if defined(CONFIG_CPU_SUBTYPE_SH7722) || \ 11f15cbe6fSPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7723) || \ 12f15cbe6fSPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7343) || \ 13f15cbe6fSPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7366) 14f15cbe6fSPaul Mundt #define FRQCR 0xa4150000 15f15cbe6fSPaul Mundt #define VCLKCR 0xa4150004 16f15cbe6fSPaul Mundt #define SCLKACR 0xa4150008 17f15cbe6fSPaul Mundt #define SCLKBCR 0xa415000c 18f15cbe6fSPaul Mundt #define IrDACLKCR 0xa4150010 19f15cbe6fSPaul Mundt #define MSTPCR0 0xa4150030 20f15cbe6fSPaul Mundt #define MSTPCR1 0xa4150034 21f15cbe6fSPaul Mundt #define MSTPCR2 0xa4150038 22c01f0f1aSYoshihiro Shimoda #elif defined(CONFIG_CPU_SUBTYPE_SH7757) 23c01f0f1aSYoshihiro Shimoda #define FRQCR 0xffc80000 24c01f0f1aSYoshihiro Shimoda #define OSCCR 0xffc80018 25c01f0f1aSYoshihiro Shimoda #define PLLCR 0xffc80024 26f15cbe6fSPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 27f15cbe6fSPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7780) 28f15cbe6fSPaul Mundt #define FRQCR 0xffc80000 290207a2efSKuninori Morimoto #elif defined(CONFIG_CPU_SUBTYPE_SH7724) 300207a2efSKuninori Morimoto #define FRQCRA 0xa4150000 310207a2efSKuninori Morimoto #define FRQCRB 0xa4150004 320207a2efSKuninori Morimoto #define VCLKCR 0xa4150048 330207a2efSKuninori Morimoto 340207a2efSKuninori Morimoto #define FCLKACR 0xa4150008 350207a2efSKuninori Morimoto #define FCLKBCR 0xa415000c 360207a2efSKuninori Morimoto #define FRQCR FRQCRA 370207a2efSKuninori Morimoto #define SCLKACR FCLKACR 380207a2efSKuninori Morimoto #define SCLKBCR FCLKBCR 390207a2efSKuninori Morimoto #define FCLKACR 0xa4150008 400207a2efSKuninori Morimoto #define FCLKBCR 0xa415000c 410207a2efSKuninori Morimoto #define IrDACLKCR 0xa4150018 420207a2efSKuninori Morimoto 430207a2efSKuninori Morimoto #define MSTPCR0 0xa4150030 440207a2efSKuninori Morimoto #define MSTPCR1 0xa4150034 450207a2efSKuninori Morimoto #define MSTPCR2 0xa4150038 460207a2efSKuninori Morimoto 47fea88a0cSNobuhiro Iwamatsu #elif defined(CONFIG_CPU_SUBTYPE_SH7734) 48fea88a0cSNobuhiro Iwamatsu #define FRQCR0 0xffc80000 49fea88a0cSNobuhiro Iwamatsu #define FRQCR2 0xffc80008 50fea88a0cSNobuhiro Iwamatsu #define FRQMR1 0xffc80014 51fea88a0cSNobuhiro Iwamatsu #define FRQMR2 0xffc80018 52f15cbe6fSPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_SH7785) 53f15cbe6fSPaul Mundt #define FRQCR0 0xffc80000 54f15cbe6fSPaul Mundt #define FRQCR1 0xffc80004 55f15cbe6fSPaul Mundt #define FRQMR1 0xffc80014 5655ba99ebSKuninori Morimoto #elif defined(CONFIG_CPU_SUBTYPE_SH7786) 5755ba99ebSKuninori Morimoto #define FRQCR0 0xffc40000 5855ba99ebSKuninori Morimoto #define FRQCR1 0xffc40004 5955ba99ebSKuninori Morimoto #define FRQMR1 0xffc40014 60f15cbe6fSPaul Mundt #elif defined(CONFIG_CPU_SUBTYPE_SHX3) 615924ad0dSPaul Mundt #define FRQCR0 0xffc00000 625924ad0dSPaul Mundt #define FRQCR1 0xffc00004 635924ad0dSPaul Mundt #define FRQMR1 0xffc00014 64f15cbe6fSPaul Mundt #else 65f15cbe6fSPaul Mundt #define FRQCR 0xffc00000 66f15cbe6fSPaul Mundt #define FRQCR_PSTBY 0x0200 67f15cbe6fSPaul Mundt #define FRQCR_PLLEN 0x0400 68f15cbe6fSPaul Mundt #define FRQCR_CKOEN 0x0800 69f15cbe6fSPaul Mundt #endif 70f15cbe6fSPaul Mundt #define MIN_DIVISOR_NR 0 71f15cbe6fSPaul Mundt #define MAX_DIVISOR_NR 3 72f15cbe6fSPaul Mundt 73f15cbe6fSPaul Mundt #endif /* __ASM_CPU_SH4_FREQ_H */ 74f15cbe6fSPaul Mundt 75