1*6a0abce4SKuninori Morimoto /* SPDX-License-Identifier: GPL-2.0 2*6a0abce4SKuninori Morimoto * 3f15cbe6fSPaul Mundt * include/asm-sh/cpu-sh3/gpio.h 4f15cbe6fSPaul Mundt * 5f15cbe6fSPaul Mundt * Copyright (C) 2007 Markus Brunner, Mark Jonas 6f15cbe6fSPaul Mundt * 7f15cbe6fSPaul Mundt * Addresses for the Pin Function Controller 8f15cbe6fSPaul Mundt */ 9f15cbe6fSPaul Mundt #ifndef _CPU_SH3_GPIO_H 10f15cbe6fSPaul Mundt #define _CPU_SH3_GPIO_H 11f15cbe6fSPaul Mundt 12f15cbe6fSPaul Mundt #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 13f15cbe6fSPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7721) 14f15cbe6fSPaul Mundt 15f15cbe6fSPaul Mundt /* Control registers */ 16f15cbe6fSPaul Mundt #define PORT_PACR 0xA4050100UL 17f15cbe6fSPaul Mundt #define PORT_PBCR 0xA4050102UL 18f15cbe6fSPaul Mundt #define PORT_PCCR 0xA4050104UL 19f15cbe6fSPaul Mundt #define PORT_PDCR 0xA4050106UL 20f15cbe6fSPaul Mundt #define PORT_PECR 0xA4050108UL 21f15cbe6fSPaul Mundt #define PORT_PFCR 0xA405010AUL 22f15cbe6fSPaul Mundt #define PORT_PGCR 0xA405010CUL 23f15cbe6fSPaul Mundt #define PORT_PHCR 0xA405010EUL 24f15cbe6fSPaul Mundt #define PORT_PJCR 0xA4050110UL 25f15cbe6fSPaul Mundt #define PORT_PKCR 0xA4050112UL 26f15cbe6fSPaul Mundt #define PORT_PLCR 0xA4050114UL 27f15cbe6fSPaul Mundt #define PORT_PMCR 0xA4050116UL 28f15cbe6fSPaul Mundt #define PORT_PPCR 0xA4050118UL 29f15cbe6fSPaul Mundt #define PORT_PRCR 0xA405011AUL 30f15cbe6fSPaul Mundt #define PORT_PSCR 0xA405011CUL 31f15cbe6fSPaul Mundt #define PORT_PTCR 0xA405011EUL 32f15cbe6fSPaul Mundt #define PORT_PUCR 0xA4050120UL 33f15cbe6fSPaul Mundt #define PORT_PVCR 0xA4050122UL 34f15cbe6fSPaul Mundt 35f15cbe6fSPaul Mundt /* Data registers */ 36f15cbe6fSPaul Mundt #define PORT_PADR 0xA4050140UL 37f15cbe6fSPaul Mundt /* Address of PORT_PBDR is wrong in the datasheet, see errata 2005-09-21 */ 38f15cbe6fSPaul Mundt #define PORT_PBDR 0xA4050142UL 39f15cbe6fSPaul Mundt #define PORT_PCDR 0xA4050144UL 40f15cbe6fSPaul Mundt #define PORT_PDDR 0xA4050146UL 41f15cbe6fSPaul Mundt #define PORT_PEDR 0xA4050148UL 42f15cbe6fSPaul Mundt #define PORT_PFDR 0xA405014AUL 43f15cbe6fSPaul Mundt #define PORT_PGDR 0xA405014CUL 44f15cbe6fSPaul Mundt #define PORT_PHDR 0xA405014EUL 45f15cbe6fSPaul Mundt #define PORT_PJDR 0xA4050150UL 46f15cbe6fSPaul Mundt #define PORT_PKDR 0xA4050152UL 47f15cbe6fSPaul Mundt #define PORT_PLDR 0xA4050154UL 48f15cbe6fSPaul Mundt #define PORT_PMDR 0xA4050156UL 49f15cbe6fSPaul Mundt #define PORT_PPDR 0xA4050158UL 50f15cbe6fSPaul Mundt #define PORT_PRDR 0xA405015AUL 51f15cbe6fSPaul Mundt #define PORT_PSDR 0xA405015CUL 52f15cbe6fSPaul Mundt #define PORT_PTDR 0xA405015EUL 53f15cbe6fSPaul Mundt #define PORT_PUDR 0xA4050160UL 54f15cbe6fSPaul Mundt #define PORT_PVDR 0xA4050162UL 55f15cbe6fSPaul Mundt 56f15cbe6fSPaul Mundt /* Pin Select Registers */ 57f15cbe6fSPaul Mundt #define PORT_PSELA 0xA4050124UL 58f15cbe6fSPaul Mundt #define PORT_PSELB 0xA4050126UL 59f15cbe6fSPaul Mundt #define PORT_PSELC 0xA4050128UL 60f15cbe6fSPaul Mundt #define PORT_PSELD 0xA405012AUL 61f15cbe6fSPaul Mundt 628085ac75SSteve Glendinning #elif defined(CONFIG_CPU_SUBTYPE_SH7709) 638085ac75SSteve Glendinning 648085ac75SSteve Glendinning /* Control registers */ 658085ac75SSteve Glendinning #define PORT_PACR 0xa4000100UL 668085ac75SSteve Glendinning #define PORT_PBCR 0xa4000102UL 678085ac75SSteve Glendinning #define PORT_PCCR 0xa4000104UL 688085ac75SSteve Glendinning #define PORT_PFCR 0xa400010aUL 698085ac75SSteve Glendinning 708085ac75SSteve Glendinning /* Data registers */ 718085ac75SSteve Glendinning #define PORT_PADR 0xa4000120UL 728085ac75SSteve Glendinning #define PORT_PBDR 0xa4000122UL 738085ac75SSteve Glendinning #define PORT_PCDR 0xa4000124UL 748085ac75SSteve Glendinning #define PORT_PFDR 0xa400012aUL 758085ac75SSteve Glendinning 76f15cbe6fSPaul Mundt #endif 77f15cbe6fSPaul Mundt 78f15cbe6fSPaul Mundt #endif 79