1f15cbe6fSPaul Mundt #ifndef __ASM_SH_PROCESSOR_H 2f15cbe6fSPaul Mundt #define __ASM_SH_PROCESSOR_H 3f15cbe6fSPaul Mundt 4f15cbe6fSPaul Mundt #include <asm/cpu-features.h> 5f15cbe6fSPaul Mundt #include <asm/segment.h> 681b66995SPaul Mundt #include <asm/cache.h> 7f15cbe6fSPaul Mundt 8f15cbe6fSPaul Mundt #ifndef __ASSEMBLY__ 9f15cbe6fSPaul Mundt /* 10f15cbe6fSPaul Mundt * CPU type and hardware bug flags. Kept separately for each CPU. 11f15cbe6fSPaul Mundt * 12f15cbe6fSPaul Mundt * Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry 13f15cbe6fSPaul Mundt * in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c 14f15cbe6fSPaul Mundt * for parsing the subtype in get_cpu_subtype(). 15f15cbe6fSPaul Mundt */ 16f15cbe6fSPaul Mundt enum cpu_type { 17f15cbe6fSPaul Mundt /* SH-2 types */ 18f15cbe6fSPaul Mundt CPU_SH7619, 19f15cbe6fSPaul Mundt 20f15cbe6fSPaul Mundt /* SH-2A types */ 212825999eSPeter Griffin CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG, 22f15cbe6fSPaul Mundt 23f15cbe6fSPaul Mundt /* SH-3 types */ 24f15cbe6fSPaul Mundt CPU_SH7705, CPU_SH7706, CPU_SH7707, 25f15cbe6fSPaul Mundt CPU_SH7708, CPU_SH7708S, CPU_SH7708R, 26f15cbe6fSPaul Mundt CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712, 27f15cbe6fSPaul Mundt CPU_SH7720, CPU_SH7721, CPU_SH7729, 28f15cbe6fSPaul Mundt 29f15cbe6fSPaul Mundt /* SH-4 types */ 30f15cbe6fSPaul Mundt CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, 31f15cbe6fSPaul Mundt CPU_SH7760, CPU_SH4_202, CPU_SH4_501, 32f15cbe6fSPaul Mundt 33f15cbe6fSPaul Mundt /* SH-4A types */ 3455ba99ebSKuninori Morimoto CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786, 35*fea88a0cSNobuhiro Iwamatsu CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SH7734, CPU_SHX3, 36f15cbe6fSPaul Mundt 37f15cbe6fSPaul Mundt /* SH4AL-DSP types */ 38fac6c2a8SMagnus Damm CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372, 39f15cbe6fSPaul Mundt 40f15cbe6fSPaul Mundt /* SH-5 types */ 41f15cbe6fSPaul Mundt CPU_SH5_101, CPU_SH5_103, 42f15cbe6fSPaul Mundt 43f15cbe6fSPaul Mundt /* Unknown subtype */ 44f15cbe6fSPaul Mundt CPU_SH_NONE 45f15cbe6fSPaul Mundt }; 46f15cbe6fSPaul Mundt 47e82da214SPaul Mundt enum cpu_family { 48e82da214SPaul Mundt CPU_FAMILY_SH2, 49e82da214SPaul Mundt CPU_FAMILY_SH2A, 50e82da214SPaul Mundt CPU_FAMILY_SH3, 51e82da214SPaul Mundt CPU_FAMILY_SH4, 52e82da214SPaul Mundt CPU_FAMILY_SH4A, 53e82da214SPaul Mundt CPU_FAMILY_SH4AL_DSP, 54e82da214SPaul Mundt CPU_FAMILY_SH5, 55e82da214SPaul Mundt CPU_FAMILY_UNKNOWN, 56e82da214SPaul Mundt }; 57e82da214SPaul Mundt 5881b66995SPaul Mundt /* 5981b66995SPaul Mundt * TLB information structure 6081b66995SPaul Mundt * 6181b66995SPaul Mundt * Defined for both I and D tlb, per-processor. 6281b66995SPaul Mundt */ 6381b66995SPaul Mundt struct tlb_info { 6481b66995SPaul Mundt unsigned long long next; 6581b66995SPaul Mundt unsigned long long first; 6681b66995SPaul Mundt unsigned long long last; 6781b66995SPaul Mundt 6881b66995SPaul Mundt unsigned int entries; 6981b66995SPaul Mundt unsigned int step; 7081b66995SPaul Mundt 7181b66995SPaul Mundt unsigned long flags; 7281b66995SPaul Mundt }; 7381b66995SPaul Mundt 7481b66995SPaul Mundt struct sh_cpuinfo { 75e82da214SPaul Mundt unsigned int type, family; 7681b66995SPaul Mundt int cut_major, cut_minor; 7781b66995SPaul Mundt unsigned long loops_per_jiffy; 7881b66995SPaul Mundt unsigned long asid_cache; 7981b66995SPaul Mundt 8081b66995SPaul Mundt struct cache_info icache; /* Primary I-cache */ 8181b66995SPaul Mundt struct cache_info dcache; /* Primary D-cache */ 8281b66995SPaul Mundt struct cache_info scache; /* Secondary cache */ 8381b66995SPaul Mundt 8481b66995SPaul Mundt /* TLB info */ 8581b66995SPaul Mundt struct tlb_info itlb; 8681b66995SPaul Mundt struct tlb_info dtlb; 8781b66995SPaul Mundt 888db2bc45SPaul Mundt #ifdef CONFIG_SMP 898db2bc45SPaul Mundt struct task_struct *idle; 908db2bc45SPaul Mundt #endif 918db2bc45SPaul Mundt 922f98492cSPaul Mundt unsigned int phys_bits; 9381b66995SPaul Mundt unsigned long flags; 9481b66995SPaul Mundt } __attribute__ ((aligned(L1_CACHE_BYTES))); 9581b66995SPaul Mundt 9681b66995SPaul Mundt extern struct sh_cpuinfo cpu_data[]; 9781b66995SPaul Mundt #define boot_cpu_data cpu_data[0] 9881b66995SPaul Mundt #define current_cpu_data cpu_data[smp_processor_id()] 9981b66995SPaul Mundt #define raw_current_cpu_data cpu_data[raw_smp_processor_id()] 10081b66995SPaul Mundt 101eb67cf14SPaul Mundt #define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory") 102eb67cf14SPaul Mundt #define cpu_relax() barrier() 103eb67cf14SPaul Mundt 104e839ca52SDavid Howells void default_idle(void); 105e839ca52SDavid Howells void cpu_idle_wait(void); 106e839ca52SDavid Howells void stop_this_cpu(void *); 107e839ca52SDavid Howells 108f15cbe6fSPaul Mundt /* Forward decl */ 109fa43972fSPaul Mundt struct seq_operations; 1103ef2932bSPaul Mundt struct task_struct; 111fa43972fSPaul Mundt 112fa43972fSPaul Mundt extern struct pt_regs fake_swapper_regs; 113f15cbe6fSPaul Mundt 1144a6feab0SPaul Mundt extern void cpu_init(void); 115a9079ca0SPaul Mundt extern void cpu_probe(void); 116a9079ca0SPaul Mundt 1173ef2932bSPaul Mundt /* arch/sh/kernel/process.c */ 1183ef2932bSPaul Mundt extern unsigned int xstate_size; 1193ef2932bSPaul Mundt extern void free_thread_xstate(struct task_struct *); 1203ef2932bSPaul Mundt extern struct kmem_cache *task_xstate_cachep; 1213ef2932bSPaul Mundt 12294ea5e44SPaul Mundt /* arch/sh/mm/alignment.c */ 12394ea5e44SPaul Mundt extern int get_unalign_ctl(struct task_struct *, unsigned long addr); 12494ea5e44SPaul Mundt extern int set_unalign_ctl(struct task_struct *, unsigned int val); 12594ea5e44SPaul Mundt 12694ea5e44SPaul Mundt #define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) 12794ea5e44SPaul Mundt #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) 12894ea5e44SPaul Mundt 129d9b9487aSPaul Mundt /* arch/sh/mm/init.c */ 130d9b9487aSPaul Mundt extern unsigned int mem_init_done; 131d9b9487aSPaul Mundt 132f15cbe6fSPaul Mundt /* arch/sh/kernel/setup.c */ 133f15cbe6fSPaul Mundt const char *get_cpu_subtype(struct sh_cpuinfo *c); 134fa43972fSPaul Mundt extern const struct seq_operations cpuinfo_op; 135f15cbe6fSPaul Mundt 13694ea5e44SPaul Mundt /* thread_struct flags */ 13794ea5e44SPaul Mundt #define SH_THREAD_UAC_NOPRINT (1 << 0) 13894ea5e44SPaul Mundt #define SH_THREAD_UAC_SIGBUS (1 << 1) 13994ea5e44SPaul Mundt #define SH_THREAD_UAC_MASK (SH_THREAD_UAC_NOPRINT | SH_THREAD_UAC_SIGBUS) 14094ea5e44SPaul Mundt 141eb9b9b56SMagnus Damm /* processor boot mode configuration */ 1420d4fdbb6SMagnus Damm #define MODE_PIN0 (1 << 0) 1430d4fdbb6SMagnus Damm #define MODE_PIN1 (1 << 1) 1440d4fdbb6SMagnus Damm #define MODE_PIN2 (1 << 2) 1450d4fdbb6SMagnus Damm #define MODE_PIN3 (1 << 3) 1460d4fdbb6SMagnus Damm #define MODE_PIN4 (1 << 4) 1470d4fdbb6SMagnus Damm #define MODE_PIN5 (1 << 5) 1480d4fdbb6SMagnus Damm #define MODE_PIN6 (1 << 6) 1490d4fdbb6SMagnus Damm #define MODE_PIN7 (1 << 7) 1500d4fdbb6SMagnus Damm #define MODE_PIN8 (1 << 8) 1510d4fdbb6SMagnus Damm #define MODE_PIN9 (1 << 9) 1520d4fdbb6SMagnus Damm #define MODE_PIN10 (1 << 10) 1530d4fdbb6SMagnus Damm #define MODE_PIN11 (1 << 11) 1540d4fdbb6SMagnus Damm #define MODE_PIN12 (1 << 12) 1550d4fdbb6SMagnus Damm #define MODE_PIN13 (1 << 13) 1560d4fdbb6SMagnus Damm #define MODE_PIN14 (1 << 14) 1570d4fdbb6SMagnus Damm #define MODE_PIN15 (1 << 15) 1580d4fdbb6SMagnus Damm 159eb9b9b56SMagnus Damm int generic_mode_pins(void); 160eb9b9b56SMagnus Damm int test_mode_pin(int pin); 161eb9b9b56SMagnus Damm 162f15cbe6fSPaul Mundt #ifdef CONFIG_VSYSCALL 163f15cbe6fSPaul Mundt int vsyscall_init(void); 164f15cbe6fSPaul Mundt #else 165f15cbe6fSPaul Mundt #define vsyscall_init() do { } while (0) 166f15cbe6fSPaul Mundt #endif 167f15cbe6fSPaul Mundt 168e839ca52SDavid Howells /* 169e839ca52SDavid Howells * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks. 170e839ca52SDavid Howells */ 171e839ca52SDavid Howells #ifdef CONFIG_CPU_SH2A 172e839ca52SDavid Howells extern unsigned int instruction_size(unsigned int insn); 173e839ca52SDavid Howells #elif defined(CONFIG_SUPERH32) 174e839ca52SDavid Howells #define instruction_size(insn) (2) 175e839ca52SDavid Howells #else 176e839ca52SDavid Howells #define instruction_size(insn) (4) 177e839ca52SDavid Howells #endif 178e839ca52SDavid Howells 179f15cbe6fSPaul Mundt #endif /* __ASSEMBLY__ */ 180f15cbe6fSPaul Mundt 181f15cbe6fSPaul Mundt #ifdef CONFIG_SUPERH32 182f15cbe6fSPaul Mundt # include "processor_32.h" 183f15cbe6fSPaul Mundt #else 184f15cbe6fSPaul Mundt # include "processor_64.h" 185f15cbe6fSPaul Mundt #endif 186f15cbe6fSPaul Mundt 187f15cbe6fSPaul Mundt #endif /* __ASM_SH_PROCESSOR_H */ 188