1 #ifndef __ASM_SH_PCI_H 2 #define __ASM_SH_PCI_H 3 4 #ifdef __KERNEL__ 5 6 /* Can be used to override the logic in pci_scan_bus for skipping 7 already-configured bus numbers - to be used for buggy BIOSes 8 or architectures with incomplete PCI setup by the loader */ 9 10 #define pcibios_assign_all_busses() 1 11 12 /* 13 * A board can define one or more PCI channels that represent built-in (or 14 * external) PCI controllers. 15 */ 16 struct pci_channel { 17 struct pci_channel *next; 18 struct pci_bus *bus; 19 20 struct pci_ops *pci_ops; 21 22 struct resource *resources; 23 unsigned int nr_resources; 24 25 unsigned long io_offset; 26 unsigned long mem_offset; 27 28 unsigned long reg_base; 29 unsigned long io_map_base; 30 31 unsigned int index; 32 unsigned int need_domain_info; 33 34 /* Optional error handling */ 35 struct timer_list err_timer, serr_timer; 36 unsigned int err_irq, serr_irq; 37 }; 38 39 /* arch/sh/drivers/pci/pci.c */ 40 extern int register_pci_controller(struct pci_channel *hose); 41 extern void pcibios_report_status(unsigned int status_mask, int warn); 42 43 /* arch/sh/drivers/pci/common.c */ 44 extern void pcibios_enable_timers(struct pci_channel *hose); 45 extern unsigned int pcibios_handle_status_errors(unsigned long addr, 46 unsigned int status, struct pci_channel *hose); 47 extern int pci_is_66mhz_capable(struct pci_channel *hose, 48 int top_bus, int current_bus); 49 50 extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM; 51 52 struct pci_dev; 53 54 #define HAVE_PCI_MMAP 55 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 56 enum pci_mmap_state mmap_state, int write_combine); 57 extern void pcibios_set_master(struct pci_dev *dev); 58 59 static inline void pcibios_penalize_isa_irq(int irq, int active) 60 { 61 /* We don't do dynamic PCI IRQ allocation */ 62 } 63 64 /* Dynamic DMA mapping stuff. 65 * SuperH has everything mapped statically like x86. 66 */ 67 68 /* The PCI address space does equal the physical memory 69 * address space. The networking and block device layers use 70 * this boolean for bounce buffer decisions. 71 */ 72 #define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys) 73 74 /* pci_unmap_{single,page} being a nop depends upon the 75 * configuration. 76 */ 77 #ifdef CONFIG_DMA_NONCOHERENT 78 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME; 79 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME; 80 #define pci_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME) 81 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL)) 82 #define pci_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME) 83 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL)) 84 #else 85 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) 86 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) 87 #define pci_unmap_addr(PTR, ADDR_NAME) (0) 88 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) 89 #define pci_unmap_len(PTR, LEN_NAME) (0) 90 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) 91 #endif 92 93 #ifdef CONFIG_PCI 94 /* 95 * None of the SH PCI controllers support MWI, it is always treated as a 96 * direct memory write. 97 */ 98 #define PCI_DISABLE_MWI 99 100 static inline void pci_dma_burst_advice(struct pci_dev *pdev, 101 enum pci_dma_burst_strategy *strat, 102 unsigned long *strategy_parameter) 103 { 104 unsigned long cacheline_size; 105 u8 byte; 106 107 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); 108 109 if (byte == 0) 110 cacheline_size = L1_CACHE_BYTES; 111 else 112 cacheline_size = byte << 2; 113 114 *strat = PCI_DMA_BURST_MULTIPLE; 115 *strategy_parameter = cacheline_size; 116 } 117 #endif 118 119 /* Board-specific fixup routines. */ 120 int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin); 121 122 extern void pcibios_resource_to_bus(struct pci_dev *dev, 123 struct pci_bus_region *region, struct resource *res); 124 125 extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 126 struct pci_bus_region *region); 127 128 #define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index 129 130 static inline int pci_proc_domain(struct pci_bus *bus) 131 { 132 struct pci_channel *hose = bus->sysdata; 133 return hose->need_domain_info; 134 } 135 136 /* Chances are this interrupt is wired PC-style ... */ 137 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) 138 { 139 return channel ? 15 : 14; 140 } 141 142 /* generic DMA-mapping stuff */ 143 #include <asm-generic/pci-dma-compat.h> 144 145 #endif /* __KERNEL__ */ 146 #endif /* __ASM_SH_PCI_H */ 147 148