1 #ifndef __ASM_SH_IO_H 2 #define __ASM_SH_IO_H 3 /* 4 * Convention: 5 * read{b,w,l,q}/write{b,w,l,q} are for PCI, 6 * while in{b,w,l}/out{b,w,l} are for ISA 7 * 8 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p 9 * and 'string' versions: ins{b,w,l}/outs{b,w,l} 10 * 11 * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers 12 * automatically, there are also __raw versions, which do not. 13 * 14 * Historically, we have also had ctrl_in{b,w,l,q}/ctrl_out{b,w,l,q} for 15 * SuperH specific I/O (raw I/O to on-chip CPU peripherals). In practice 16 * these have the same semantics as the __raw variants, and as such, all 17 * new code should be using the __raw versions. 18 * 19 * All ISA I/O routines are wrapped through the machine vector. If a 20 * board does not provide overrides, a generic set that are copied in 21 * from the default machine vector are used instead. These are largely 22 * for old compat code for I/O offseting to SuperIOs, all of which are 23 * better handled through the machvec ioport mapping routines these days. 24 */ 25 #include <linux/errno.h> 26 #include <asm/cache.h> 27 #include <asm/system.h> 28 #include <asm/addrspace.h> 29 #include <asm/machvec.h> 30 #include <asm/pgtable.h> 31 #include <asm-generic/iomap.h> 32 33 #ifdef __KERNEL__ 34 /* 35 * Depending on which platform we are running on, we need different 36 * I/O functions. 37 */ 38 #define __IO_PREFIX generic 39 #include <asm/io_generic.h> 40 #include <asm/io_trapped.h> 41 42 #define inb(p) sh_mv.mv_inb((p)) 43 #define inw(p) sh_mv.mv_inw((p)) 44 #define inl(p) sh_mv.mv_inl((p)) 45 #define outb(x,p) sh_mv.mv_outb((x),(p)) 46 #define outw(x,p) sh_mv.mv_outw((x),(p)) 47 #define outl(x,p) sh_mv.mv_outl((x),(p)) 48 49 #define inb_p(p) sh_mv.mv_inb_p((p)) 50 #define inw_p(p) sh_mv.mv_inw_p((p)) 51 #define inl_p(p) sh_mv.mv_inl_p((p)) 52 #define outb_p(x,p) sh_mv.mv_outb_p((x),(p)) 53 #define outw_p(x,p) sh_mv.mv_outw_p((x),(p)) 54 #define outl_p(x,p) sh_mv.mv_outl_p((x),(p)) 55 56 #define insb(p,b,c) sh_mv.mv_insb((p), (b), (c)) 57 #define insw(p,b,c) sh_mv.mv_insw((p), (b), (c)) 58 #define insl(p,b,c) sh_mv.mv_insl((p), (b), (c)) 59 #define outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c)) 60 #define outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c)) 61 #define outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c)) 62 63 #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v)) 64 #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v)) 65 #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v)) 66 #define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v)) 67 68 #define __raw_readb(a) (__chk_io_ptr(a), *(volatile u8 __force *)(a)) 69 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile u16 __force *)(a)) 70 #define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a)) 71 #define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a)) 72 73 #define readb(a) ({ u8 r_ = __raw_readb(a); mb(); r_; }) 74 #define readw(a) ({ u16 r_ = __raw_readw(a); mb(); r_; }) 75 #define readl(a) ({ u32 r_ = __raw_readl(a); mb(); r_; }) 76 #define readq(a) ({ u64 r_ = __raw_readq(a); mb(); r_; }) 77 78 #define writeb(v,a) ({ __raw_writeb((v),(a)); mb(); }) 79 #define writew(v,a) ({ __raw_writew((v),(a)); mb(); }) 80 #define writel(v,a) ({ __raw_writel((v),(a)); mb(); }) 81 #define writeq(v,a) ({ __raw_writeq((v),(a)); mb(); }) 82 83 /* 84 * Legacy SuperH on-chip I/O functions 85 * 86 * These are all deprecated, all new (and especially cross-platform) code 87 * should be using the __raw_xxx() routines directly. 88 */ 89 static inline u8 __deprecated ctrl_inb(unsigned long addr) 90 { 91 return __raw_readb(addr); 92 } 93 94 static inline u16 __deprecated ctrl_inw(unsigned long addr) 95 { 96 return __raw_readw(addr); 97 } 98 99 static inline u32 __deprecated ctrl_inl(unsigned long addr) 100 { 101 return __raw_readl(addr); 102 } 103 104 static inline u64 __deprecated ctrl_inq(unsigned long addr) 105 { 106 return __raw_readq(addr); 107 } 108 109 static inline void __deprecated ctrl_outb(u8 v, unsigned long addr) 110 { 111 __raw_writeb(v, addr); 112 } 113 114 static inline void __deprecated ctrl_outw(u16 v, unsigned long addr) 115 { 116 __raw_writew(v, addr); 117 } 118 119 static inline void __deprecated ctrl_outl(u32 v, unsigned long addr) 120 { 121 __raw_writel(v, addr); 122 } 123 124 static inline void __deprecated ctrl_outq(u64 v, unsigned long addr) 125 { 126 __raw_writeq(v, addr); 127 } 128 129 extern unsigned long generic_io_base; 130 131 static inline void ctrl_delay(void) 132 { 133 __raw_readw(generic_io_base); 134 } 135 136 #define __BUILD_UNCACHED_IO(bwlq, type) \ 137 static inline type read##bwlq##_uncached(unsigned long addr) \ 138 { \ 139 type ret; \ 140 jump_to_uncached(); \ 141 ret = __raw_read##bwlq(addr); \ 142 back_to_cached(); \ 143 return ret; \ 144 } \ 145 \ 146 static inline void write##bwlq##_uncached(type v, unsigned long addr) \ 147 { \ 148 jump_to_uncached(); \ 149 __raw_write##bwlq(v, addr); \ 150 back_to_cached(); \ 151 } 152 153 __BUILD_UNCACHED_IO(b, u8) 154 __BUILD_UNCACHED_IO(w, u16) 155 __BUILD_UNCACHED_IO(l, u32) 156 __BUILD_UNCACHED_IO(q, u64) 157 158 #define __BUILD_MEMORY_STRING(bwlq, type) \ 159 \ 160 static inline void __raw_writes##bwlq(volatile void __iomem *mem, \ 161 const void *addr, unsigned int count) \ 162 { \ 163 const volatile type *__addr = addr; \ 164 \ 165 while (count--) { \ 166 __raw_write##bwlq(*__addr, mem); \ 167 __addr++; \ 168 } \ 169 } \ 170 \ 171 static inline void __raw_reads##bwlq(volatile void __iomem *mem, \ 172 void *addr, unsigned int count) \ 173 { \ 174 volatile type *__addr = addr; \ 175 \ 176 while (count--) { \ 177 *__addr = __raw_read##bwlq(mem); \ 178 __addr++; \ 179 } \ 180 } 181 182 __BUILD_MEMORY_STRING(b, u8) 183 __BUILD_MEMORY_STRING(w, u16) 184 185 #ifdef CONFIG_SUPERH32 186 void __raw_writesl(void __iomem *addr, const void *data, int longlen); 187 void __raw_readsl(const void __iomem *addr, void *data, int longlen); 188 #else 189 __BUILD_MEMORY_STRING(l, u32) 190 #endif 191 192 __BUILD_MEMORY_STRING(q, u64) 193 194 #define writesb __raw_writesb 195 #define writesw __raw_writesw 196 #define writesl __raw_writesl 197 198 #define readsb __raw_readsb 199 #define readsw __raw_readsw 200 #define readsl __raw_readsl 201 202 #define readb_relaxed(a) readb(a) 203 #define readw_relaxed(a) readw(a) 204 #define readl_relaxed(a) readl(a) 205 #define readq_relaxed(a) readq(a) 206 207 #ifndef CONFIG_GENERIC_IOMAP 208 /* Simple MMIO */ 209 #define ioread8(a) __raw_readb(a) 210 #define ioread16(a) __raw_readw(a) 211 #define ioread16be(a) be16_to_cpu(__raw_readw((a))) 212 #define ioread32(a) __raw_readl(a) 213 #define ioread32be(a) be32_to_cpu(__raw_readl((a))) 214 215 #define iowrite8(v,a) __raw_writeb((v),(a)) 216 #define iowrite16(v,a) __raw_writew((v),(a)) 217 #define iowrite16be(v,a) __raw_writew(cpu_to_be16((v)),(a)) 218 #define iowrite32(v,a) __raw_writel((v),(a)) 219 #define iowrite32be(v,a) __raw_writel(cpu_to_be32((v)),(a)) 220 221 #define ioread8_rep(a, d, c) __raw_readsb((a), (d), (c)) 222 #define ioread16_rep(a, d, c) __raw_readsw((a), (d), (c)) 223 #define ioread32_rep(a, d, c) __raw_readsl((a), (d), (c)) 224 225 #define iowrite8_rep(a, s, c) __raw_writesb((a), (s), (c)) 226 #define iowrite16_rep(a, s, c) __raw_writesw((a), (s), (c)) 227 #define iowrite32_rep(a, s, c) __raw_writesl((a), (s), (c)) 228 #endif 229 230 #define mmio_insb(p,d,c) __raw_readsb(p,d,c) 231 #define mmio_insw(p,d,c) __raw_readsw(p,d,c) 232 #define mmio_insl(p,d,c) __raw_readsl(p,d,c) 233 234 #define mmio_outsb(p,s,c) __raw_writesb(p,s,c) 235 #define mmio_outsw(p,s,c) __raw_writesw(p,s,c) 236 #define mmio_outsl(p,s,c) __raw_writesl(p,s,c) 237 238 /* synco on SH-4A, otherwise a nop */ 239 #define mmiowb() wmb() 240 241 #define IO_SPACE_LIMIT 0xffffffff 242 243 /* 244 * This function provides a method for the generic case where a 245 * board-specific ioport_map simply needs to return the port + some 246 * arbitrary port base. 247 * 248 * We use this at board setup time to implicitly set the port base, and 249 * as a result, we can use the generic ioport_map. 250 */ 251 static inline void __set_io_port_base(unsigned long pbase) 252 { 253 generic_io_base = pbase; 254 } 255 256 #define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n)) 257 258 /* We really want to try and get these to memcpy etc */ 259 void memcpy_fromio(void *, const volatile void __iomem *, unsigned long); 260 void memcpy_toio(volatile void __iomem *, const void *, unsigned long); 261 void memset_io(volatile void __iomem *, int, unsigned long); 262 263 /* Quad-word real-mode I/O, don't ask.. */ 264 unsigned long long peek_real_address_q(unsigned long long addr); 265 unsigned long long poke_real_address_q(unsigned long long addr, 266 unsigned long long val); 267 268 #if !defined(CONFIG_MMU) 269 #define virt_to_phys(address) ((unsigned long)(address)) 270 #define phys_to_virt(address) ((void *)(address)) 271 #else 272 #define virt_to_phys(address) (__pa(address)) 273 #define phys_to_virt(address) (__va(address)) 274 #endif 275 276 /* 277 * On 32-bit SH, we traditionally have the whole physical address space 278 * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do 279 * not need to do anything but place the address in the proper segment. 280 * This is true for P1 and P2 addresses, as well as some P3 ones. 281 * However, most of the P3 addresses and newer cores using extended 282 * addressing need to map through page tables, so the ioremap() 283 * implementation becomes a bit more complicated. 284 * 285 * See arch/sh/mm/ioremap.c for additional notes on this. 286 * 287 * We cheat a bit and always return uncachable areas until we've fixed 288 * the drivers to handle caching properly. 289 * 290 * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply 291 * doesn't exist, so everything must go through page tables. 292 */ 293 #ifdef CONFIG_MMU 294 void __iomem *__ioremap_caller(phys_addr_t offset, unsigned long size, 295 pgprot_t prot, void *caller); 296 void __iounmap(void __iomem *addr); 297 298 static inline void __iomem * 299 __ioremap(phys_addr_t offset, unsigned long size, pgprot_t prot) 300 { 301 return __ioremap_caller(offset, size, prot, __builtin_return_address(0)); 302 } 303 304 static inline void __iomem * 305 __ioremap_29bit(phys_addr_t offset, unsigned long size, pgprot_t prot) 306 { 307 #ifdef CONFIG_29BIT 308 phys_addr_t last_addr = offset + size - 1; 309 310 /* 311 * For P1 and P2 space this is trivial, as everything is already 312 * mapped. Uncached access for P1 addresses are done through P2. 313 * In the P3 case or for addresses outside of the 29-bit space, 314 * mapping must be done by the PMB or by using page tables. 315 */ 316 if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) { 317 if (unlikely(pgprot_val(prot) & _PAGE_CACHABLE)) 318 return (void __iomem *)P1SEGADDR(offset); 319 320 return (void __iomem *)P2SEGADDR(offset); 321 } 322 323 /* P4 above the store queues are always mapped. */ 324 if (unlikely(offset >= P3_ADDR_MAX)) 325 return (void __iomem *)P4SEGADDR(offset); 326 #endif 327 328 return NULL; 329 } 330 331 static inline void __iomem * 332 __ioremap_mode(phys_addr_t offset, unsigned long size, pgprot_t prot) 333 { 334 void __iomem *ret; 335 336 ret = __ioremap_trapped(offset, size); 337 if (ret) 338 return ret; 339 340 ret = __ioremap_29bit(offset, size, prot); 341 if (ret) 342 return ret; 343 344 return __ioremap(offset, size, prot); 345 } 346 #else 347 #define __ioremap(offset, size, prot) ((void __iomem *)(offset)) 348 #define __ioremap_mode(offset, size, prot) ((void __iomem *)(offset)) 349 #define __iounmap(addr) do { } while (0) 350 #endif /* CONFIG_MMU */ 351 352 static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size) 353 { 354 return __ioremap_mode(offset, size, PAGE_KERNEL_NOCACHE); 355 } 356 357 static inline void __iomem * 358 ioremap_cache(phys_addr_t offset, unsigned long size) 359 { 360 return __ioremap_mode(offset, size, PAGE_KERNEL); 361 } 362 363 #ifdef CONFIG_HAVE_IOREMAP_PROT 364 static inline void __iomem * 365 ioremap_prot(phys_addr_t offset, unsigned long size, unsigned long flags) 366 { 367 return __ioremap_mode(offset, size, __pgprot(flags)); 368 } 369 #endif 370 371 #ifdef CONFIG_IOREMAP_FIXED 372 extern void __iomem *ioremap_fixed(phys_addr_t, unsigned long, pgprot_t); 373 extern int iounmap_fixed(void __iomem *); 374 extern void ioremap_fixed_init(void); 375 #else 376 static inline void __iomem * 377 ioremap_fixed(phys_addr_t phys_addr, unsigned long size, pgprot_t prot) 378 { 379 BUG(); 380 return NULL; 381 } 382 383 static inline void ioremap_fixed_init(void) { } 384 static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; } 385 #endif 386 387 #define ioremap_nocache ioremap 388 #define iounmap __iounmap 389 390 #define maybebadio(port) \ 391 printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \ 392 __func__, __LINE__, (port), (u32)__builtin_return_address(0)) 393 394 /* 395 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 396 * access 397 */ 398 #define xlate_dev_mem_ptr(p) __va(p) 399 400 /* 401 * Convert a virtual cached pointer to an uncached pointer 402 */ 403 #define xlate_dev_kmem_ptr(p) p 404 405 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE 406 int valid_phys_addr_range(unsigned long addr, size_t size); 407 int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); 408 409 #endif /* __KERNEL__ */ 410 411 #endif /* __ASM_SH_IO_H */ 412