1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ASM_SH_IO_H 3 #define __ASM_SH_IO_H 4 5 /* 6 * Convention: 7 * read{b,w,l,q}/write{b,w,l,q} are for PCI, 8 * while in{b,w,l}/out{b,w,l} are for ISA 9 * 10 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p 11 * and 'string' versions: ins{b,w,l}/outs{b,w,l} 12 * 13 * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers 14 * automatically, there are also __raw versions, which do not. 15 */ 16 #include <linux/errno.h> 17 #include <asm/cache.h> 18 #include <asm/addrspace.h> 19 #include <asm/machvec.h> 20 #include <linux/pgtable.h> 21 #include <asm-generic/iomap.h> 22 23 #define __IO_PREFIX generic 24 #include <asm/io_generic.h> 25 #include <asm/io_trapped.h> 26 #include <asm-generic/pci_iomap.h> 27 #include <mach/mangle-port.h> 28 29 #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v)) 30 #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v)) 31 #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v)) 32 #define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v)) 33 34 #define __raw_readb(a) (__chk_io_ptr(a), *(volatile u8 __force *)(a)) 35 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile u16 __force *)(a)) 36 #define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a)) 37 #define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a)) 38 39 #define readb_relaxed(c) ({ u8 __v = ioswabb(__raw_readb(c)); __v; }) 40 #define readw_relaxed(c) ({ u16 __v = ioswabw(__raw_readw(c)); __v; }) 41 #define readl_relaxed(c) ({ u32 __v = ioswabl(__raw_readl(c)); __v; }) 42 #define readq_relaxed(c) ({ u64 __v = ioswabq(__raw_readq(c)); __v; }) 43 44 #define writeb_relaxed(v,c) ((void)__raw_writeb((__force u8)ioswabb(v),c)) 45 #define writew_relaxed(v,c) ((void)__raw_writew((__force u16)ioswabw(v),c)) 46 #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c)) 47 #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)ioswabq(v),c)) 48 49 #define readb(a) ({ u8 r_ = readb_relaxed(a); rmb(); r_; }) 50 #define readw(a) ({ u16 r_ = readw_relaxed(a); rmb(); r_; }) 51 #define readl(a) ({ u32 r_ = readl_relaxed(a); rmb(); r_; }) 52 #define readq(a) ({ u64 r_ = readq_relaxed(a); rmb(); r_; }) 53 54 #define writeb(v,a) ({ wmb(); writeb_relaxed((v),(a)); }) 55 #define writew(v,a) ({ wmb(); writew_relaxed((v),(a)); }) 56 #define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); }) 57 #define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); }) 58 59 #define readsb(p,d,l) __raw_readsb(p,d,l) 60 #define readsw(p,d,l) __raw_readsw(p,d,l) 61 #define readsl(p,d,l) __raw_readsl(p,d,l) 62 63 #define writesb(p,d,l) __raw_writesb(p,d,l) 64 #define writesw(p,d,l) __raw_writesw(p,d,l) 65 #define writesl(p,d,l) __raw_writesl(p,d,l) 66 67 #define __BUILD_UNCACHED_IO(bwlq, type) \ 68 static inline type read##bwlq##_uncached(unsigned long addr) \ 69 { \ 70 type ret; \ 71 jump_to_uncached(); \ 72 ret = __raw_read##bwlq(addr); \ 73 back_to_cached(); \ 74 return ret; \ 75 } \ 76 \ 77 static inline void write##bwlq##_uncached(type v, unsigned long addr) \ 78 { \ 79 jump_to_uncached(); \ 80 __raw_write##bwlq(v, addr); \ 81 back_to_cached(); \ 82 } 83 84 __BUILD_UNCACHED_IO(b, u8) 85 __BUILD_UNCACHED_IO(w, u16) 86 __BUILD_UNCACHED_IO(l, u32) 87 __BUILD_UNCACHED_IO(q, u64) 88 89 #define __BUILD_MEMORY_STRING(pfx, bwlq, type) \ 90 \ 91 static inline void \ 92 pfx##writes##bwlq(volatile void __iomem *mem, const void *addr, \ 93 unsigned int count) \ 94 { \ 95 const volatile type *__addr = addr; \ 96 \ 97 while (count--) { \ 98 __raw_write##bwlq(*__addr, mem); \ 99 __addr++; \ 100 } \ 101 } \ 102 \ 103 static inline void pfx##reads##bwlq(volatile void __iomem *mem, \ 104 void *addr, unsigned int count) \ 105 { \ 106 volatile type *__addr = addr; \ 107 \ 108 while (count--) { \ 109 *__addr = __raw_read##bwlq(mem); \ 110 __addr++; \ 111 } \ 112 } 113 114 __BUILD_MEMORY_STRING(__raw_, b, u8) 115 __BUILD_MEMORY_STRING(__raw_, w, u16) 116 117 void __raw_writesl(void __iomem *addr, const void *data, int longlen); 118 void __raw_readsl(const void __iomem *addr, void *data, int longlen); 119 120 __BUILD_MEMORY_STRING(__raw_, q, u64) 121 122 #ifdef CONFIG_HAS_IOPORT_MAP 123 124 /* 125 * Slowdown I/O port space accesses for antique hardware. 126 */ 127 #undef CONF_SLOWDOWN_IO 128 129 /* 130 * On SuperH I/O ports are memory mapped, so we access them using normal 131 * load/store instructions. sh_io_port_base is the virtual address to 132 * which all ports are being mapped. 133 */ 134 extern unsigned long sh_io_port_base; 135 136 static inline void __set_io_port_base(unsigned long pbase) 137 { 138 *(unsigned long *)&sh_io_port_base = pbase; 139 barrier(); 140 } 141 142 #ifdef CONFIG_GENERIC_IOMAP 143 #define __ioport_map ioport_map 144 #else 145 extern void __iomem *__ioport_map(unsigned long addr, unsigned int size); 146 #endif 147 148 #ifdef CONF_SLOWDOWN_IO 149 #define SLOW_DOWN_IO __raw_readw(sh_io_port_base) 150 #else 151 #define SLOW_DOWN_IO 152 #endif 153 154 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \ 155 \ 156 static inline void pfx##out##bwlq##p(type val, unsigned long port) \ 157 { \ 158 volatile type *__addr; \ 159 \ 160 __addr = __ioport_map(port, sizeof(type)); \ 161 *__addr = val; \ 162 slow; \ 163 } \ 164 \ 165 static inline type pfx##in##bwlq##p(unsigned long port) \ 166 { \ 167 volatile type *__addr; \ 168 type __val; \ 169 \ 170 __addr = __ioport_map(port, sizeof(type)); \ 171 __val = *__addr; \ 172 slow; \ 173 \ 174 return __val; \ 175 } 176 177 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ 178 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \ 179 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO) 180 181 #define BUILDIO_IOPORT(bwlq, type) \ 182 __BUILD_IOPORT_PFX(, bwlq, type) 183 184 BUILDIO_IOPORT(b, u8) 185 BUILDIO_IOPORT(w, u16) 186 BUILDIO_IOPORT(l, u32) 187 BUILDIO_IOPORT(q, u64) 188 189 #define __BUILD_IOPORT_STRING(bwlq, type) \ 190 \ 191 static inline void outs##bwlq(unsigned long port, const void *addr, \ 192 unsigned int count) \ 193 { \ 194 const volatile type *__addr = addr; \ 195 \ 196 while (count--) { \ 197 out##bwlq(*__addr, port); \ 198 __addr++; \ 199 } \ 200 } \ 201 \ 202 static inline void ins##bwlq(unsigned long port, void *addr, \ 203 unsigned int count) \ 204 { \ 205 volatile type *__addr = addr; \ 206 \ 207 while (count--) { \ 208 *__addr = in##bwlq(port); \ 209 __addr++; \ 210 } \ 211 } 212 213 __BUILD_IOPORT_STRING(b, u8) 214 __BUILD_IOPORT_STRING(w, u16) 215 __BUILD_IOPORT_STRING(l, u32) 216 __BUILD_IOPORT_STRING(q, u64) 217 218 #else /* !CONFIG_HAS_IOPORT_MAP */ 219 220 #include <asm/io_noioport.h> 221 222 #endif 223 224 225 #define IO_SPACE_LIMIT 0xffffffff 226 227 /* We really want to try and get these to memcpy etc */ 228 void memcpy_fromio(void *, const volatile void __iomem *, unsigned long); 229 void memcpy_toio(volatile void __iomem *, const void *, unsigned long); 230 void memset_io(volatile void __iomem *, int, unsigned long); 231 232 /* Quad-word real-mode I/O, don't ask.. */ 233 unsigned long long peek_real_address_q(unsigned long long addr); 234 unsigned long long poke_real_address_q(unsigned long long addr, 235 unsigned long long val); 236 237 #if !defined(CONFIG_MMU) 238 #define virt_to_phys(address) ((unsigned long)(address)) 239 #define phys_to_virt(address) ((void *)(address)) 240 #else 241 #define virt_to_phys(address) (__pa(address)) 242 #define phys_to_virt(address) (__va(address)) 243 #endif 244 245 /* 246 * On 32-bit SH, we traditionally have the whole physical address space 247 * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do 248 * not need to do anything but place the address in the proper segment. 249 * This is true for P1 and P2 addresses, as well as some P3 ones. 250 * However, most of the P3 addresses and newer cores using extended 251 * addressing need to map through page tables, so the ioremap() 252 * implementation becomes a bit more complicated. 253 * 254 * See arch/sh/mm/ioremap.c for additional notes on this. 255 * 256 * We cheat a bit and always return uncachable areas until we've fixed 257 * the drivers to handle caching properly. 258 * 259 * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply 260 * doesn't exist, so everything must go through page tables. 261 */ 262 #ifdef CONFIG_MMU 263 void __iomem *__ioremap_caller(phys_addr_t offset, unsigned long size, 264 pgprot_t prot, void *caller); 265 void iounmap(void __iomem *addr); 266 267 static inline void __iomem * 268 __ioremap(phys_addr_t offset, unsigned long size, pgprot_t prot) 269 { 270 return __ioremap_caller(offset, size, prot, __builtin_return_address(0)); 271 } 272 273 static inline void __iomem * 274 __ioremap_29bit(phys_addr_t offset, unsigned long size, pgprot_t prot) 275 { 276 #ifdef CONFIG_29BIT 277 phys_addr_t last_addr = offset + size - 1; 278 279 /* 280 * For P1 and P2 space this is trivial, as everything is already 281 * mapped. Uncached access for P1 addresses are done through P2. 282 * In the P3 case or for addresses outside of the 29-bit space, 283 * mapping must be done by the PMB or by using page tables. 284 */ 285 if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) { 286 u64 flags = pgprot_val(prot); 287 288 /* 289 * Anything using the legacy PTEA space attributes needs 290 * to be kicked down to page table mappings. 291 */ 292 if (unlikely(flags & _PAGE_PCC_MASK)) 293 return NULL; 294 if (unlikely(flags & _PAGE_CACHABLE)) 295 return (void __iomem *)P1SEGADDR(offset); 296 297 return (void __iomem *)P2SEGADDR(offset); 298 } 299 300 /* P4 above the store queues are always mapped. */ 301 if (unlikely(offset >= P3_ADDR_MAX)) 302 return (void __iomem *)P4SEGADDR(offset); 303 #endif 304 305 return NULL; 306 } 307 308 static inline void __iomem * 309 __ioremap_mode(phys_addr_t offset, unsigned long size, pgprot_t prot) 310 { 311 void __iomem *ret; 312 313 ret = __ioremap_trapped(offset, size); 314 if (ret) 315 return ret; 316 317 ret = __ioremap_29bit(offset, size, prot); 318 if (ret) 319 return ret; 320 321 return __ioremap(offset, size, prot); 322 } 323 #else 324 #define __ioremap(offset, size, prot) ((void __iomem *)(offset)) 325 #define __ioremap_mode(offset, size, prot) ((void __iomem *)(offset)) 326 static inline void iounmap(void __iomem *addr) {} 327 #endif /* CONFIG_MMU */ 328 329 static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size) 330 { 331 return __ioremap_mode(offset, size, PAGE_KERNEL_NOCACHE); 332 } 333 334 static inline void __iomem * 335 ioremap_cache(phys_addr_t offset, unsigned long size) 336 { 337 return __ioremap_mode(offset, size, PAGE_KERNEL); 338 } 339 #define ioremap_cache ioremap_cache 340 341 #ifdef CONFIG_HAVE_IOREMAP_PROT 342 static inline void __iomem * 343 ioremap_prot(phys_addr_t offset, unsigned long size, unsigned long flags) 344 { 345 return __ioremap_mode(offset, size, __pgprot(flags)); 346 } 347 #endif 348 349 #define ioremap_uc ioremap 350 351 /* 352 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 353 * access 354 */ 355 #define xlate_dev_mem_ptr(p) __va(p) 356 357 /* 358 * Convert a virtual cached pointer to an uncached pointer 359 */ 360 #define xlate_dev_kmem_ptr(p) p 361 362 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE 363 int valid_phys_addr_range(phys_addr_t addr, size_t size); 364 int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); 365 366 #endif /* __ASM_SH_IO_H */ 367