1f15cbe6fSPaul Mundt /* $Id: cache.h,v 1.6 2004/03/11 18:08:05 lethal Exp $ 2f15cbe6fSPaul Mundt * 3f15cbe6fSPaul Mundt * include/asm-sh/cache.h 4f15cbe6fSPaul Mundt * 5f15cbe6fSPaul Mundt * Copyright 1999 (C) Niibe Yutaka 6f15cbe6fSPaul Mundt * Copyright 2002, 2003 (C) Paul Mundt 7f15cbe6fSPaul Mundt */ 8f15cbe6fSPaul Mundt #ifndef __ASM_SH_CACHE_H 9f15cbe6fSPaul Mundt #define __ASM_SH_CACHE_H 10f15cbe6fSPaul Mundt #ifdef __KERNEL__ 11f15cbe6fSPaul Mundt 12f15cbe6fSPaul Mundt #include <linux/init.h> 13f15cbe6fSPaul Mundt #include <cpu/cache.h> 14f15cbe6fSPaul Mundt 15f15cbe6fSPaul Mundt #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 16f15cbe6fSPaul Mundt 17*54cb27a7SDenys Vlasenko #define __read_mostly __attribute__((__section__(".data..read_mostly"))) 18f15cbe6fSPaul Mundt 19f15cbe6fSPaul Mundt #ifndef __ASSEMBLY__ 20f15cbe6fSPaul Mundt struct cache_info { 21f15cbe6fSPaul Mundt unsigned int ways; /* Number of cache ways */ 22f15cbe6fSPaul Mundt unsigned int sets; /* Number of cache sets */ 23f15cbe6fSPaul Mundt unsigned int linesz; /* Cache line size (bytes) */ 24f15cbe6fSPaul Mundt 25f15cbe6fSPaul Mundt unsigned int way_size; /* sets * line size */ 26f15cbe6fSPaul Mundt 27f15cbe6fSPaul Mundt /* 28f15cbe6fSPaul Mundt * way_incr is the address offset for accessing the next way 29f15cbe6fSPaul Mundt * in memory mapped cache array ops. 30f15cbe6fSPaul Mundt */ 31f15cbe6fSPaul Mundt unsigned int way_incr; 32f15cbe6fSPaul Mundt unsigned int entry_shift; 33f15cbe6fSPaul Mundt unsigned int entry_mask; 34f15cbe6fSPaul Mundt 35f15cbe6fSPaul Mundt /* 36f15cbe6fSPaul Mundt * Compute a mask which selects the address bits which overlap between 37f15cbe6fSPaul Mundt * 1. those used to select the cache set during indexing 38f15cbe6fSPaul Mundt * 2. those in the physical page number. 39f15cbe6fSPaul Mundt */ 40f15cbe6fSPaul Mundt unsigned int alias_mask; 41f15cbe6fSPaul Mundt 42f15cbe6fSPaul Mundt unsigned int n_aliases; /* Number of aliases */ 43f15cbe6fSPaul Mundt 44f15cbe6fSPaul Mundt unsigned long flags; 45f15cbe6fSPaul Mundt }; 46f15cbe6fSPaul Mundt 47f15cbe6fSPaul Mundt int __init detect_cpu_and_cache_system(void); 48f15cbe6fSPaul Mundt 49f15cbe6fSPaul Mundt #endif /* __ASSEMBLY__ */ 50f15cbe6fSPaul Mundt #endif /* __KERNEL__ */ 51f15cbe6fSPaul Mundt #endif /* __ASM_SH_CACHE_H */ 52