1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2f15cbe6fSPaul Mundt /* $Id: cache.h,v 1.6 2004/03/11 18:08:05 lethal Exp $ 3f15cbe6fSPaul Mundt * 4f15cbe6fSPaul Mundt * include/asm-sh/cache.h 5f15cbe6fSPaul Mundt * 6f15cbe6fSPaul Mundt * Copyright 1999 (C) Niibe Yutaka 7f15cbe6fSPaul Mundt * Copyright 2002, 2003 (C) Paul Mundt 8f15cbe6fSPaul Mundt */ 9f15cbe6fSPaul Mundt #ifndef __ASM_SH_CACHE_H 10f15cbe6fSPaul Mundt #define __ASM_SH_CACHE_H 11f15cbe6fSPaul Mundt 12f15cbe6fSPaul Mundt #include <linux/init.h> 13f15cbe6fSPaul Mundt #include <cpu/cache.h> 14f15cbe6fSPaul Mundt 15f15cbe6fSPaul Mundt #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 16f15cbe6fSPaul Mundt 17*e6926a4dSCatalin Marinas /* 18*e6926a4dSCatalin Marinas * Some drivers need to perform DMA into kmalloc'ed buffers 19*e6926a4dSCatalin Marinas * and so we have to increase the kmalloc minalign for this. 20*e6926a4dSCatalin Marinas */ 21*e6926a4dSCatalin Marinas #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 22*e6926a4dSCatalin Marinas 2333def849SJoe Perches #define __read_mostly __section(".data..read_mostly") 24f15cbe6fSPaul Mundt 25f15cbe6fSPaul Mundt #ifndef __ASSEMBLY__ 26f15cbe6fSPaul Mundt struct cache_info { 27f15cbe6fSPaul Mundt unsigned int ways; /* Number of cache ways */ 28f15cbe6fSPaul Mundt unsigned int sets; /* Number of cache sets */ 29f15cbe6fSPaul Mundt unsigned int linesz; /* Cache line size (bytes) */ 30f15cbe6fSPaul Mundt 31f15cbe6fSPaul Mundt unsigned int way_size; /* sets * line size */ 32f15cbe6fSPaul Mundt 33f15cbe6fSPaul Mundt /* 34f15cbe6fSPaul Mundt * way_incr is the address offset for accessing the next way 35f15cbe6fSPaul Mundt * in memory mapped cache array ops. 36f15cbe6fSPaul Mundt */ 37f15cbe6fSPaul Mundt unsigned int way_incr; 38f15cbe6fSPaul Mundt unsigned int entry_shift; 39f15cbe6fSPaul Mundt unsigned int entry_mask; 40f15cbe6fSPaul Mundt 41f15cbe6fSPaul Mundt /* 42f15cbe6fSPaul Mundt * Compute a mask which selects the address bits which overlap between 43f15cbe6fSPaul Mundt * 1. those used to select the cache set during indexing 44f15cbe6fSPaul Mundt * 2. those in the physical page number. 45f15cbe6fSPaul Mundt */ 46f15cbe6fSPaul Mundt unsigned int alias_mask; 47f15cbe6fSPaul Mundt unsigned int n_aliases; /* Number of aliases */ 48f15cbe6fSPaul Mundt 49f15cbe6fSPaul Mundt unsigned long flags; 50f15cbe6fSPaul Mundt }; 51f15cbe6fSPaul Mundt #endif /* __ASSEMBLY__ */ 52f15cbe6fSPaul Mundt #endif /* __ASM_SH_CACHE_H */ 53