xref: /openbmc/linux/arch/sh/drivers/superhyway/ops-sh4-202.c (revision 597473720f4dc69749542bfcfed4a927a43d935e)
1*ff4a7481SKuninori Morimoto // SPDX-License-Identifier: GPL-2.0
2d5cb9783SPaul Mundt /*
3d5cb9783SPaul Mundt  * arch/sh/drivers/superhyway/ops-sh4-202.c
4d5cb9783SPaul Mundt  *
5d5cb9783SPaul Mundt  * SuperHyway bus support for SH4-202
6d5cb9783SPaul Mundt  *
7d5cb9783SPaul Mundt  * Copyright (C) 2005  Paul Mundt
8d5cb9783SPaul Mundt  */
9d5cb9783SPaul Mundt #include <linux/kernel.h>
10d5cb9783SPaul Mundt #include <linux/init.h>
11d5cb9783SPaul Mundt #include <linux/superhyway.h>
12d5cb9783SPaul Mundt #include <linux/string.h>
13d5cb9783SPaul Mundt #include <asm/addrspace.h>
14d5cb9783SPaul Mundt #include <asm/io.h>
15d5cb9783SPaul Mundt 
16d5cb9783SPaul Mundt #define PHYS_EMI_CBLOCK		P4SEGADDR(0x1ec00000)
17d5cb9783SPaul Mundt #define PHYS_EMI_DBLOCK		P4SEGADDR(0x08000000)
18d5cb9783SPaul Mundt #define PHYS_FEMI_CBLOCK	P4SEGADDR(0x1f800000)
19d5cb9783SPaul Mundt #define PHYS_FEMI_DBLOCK	P4SEGADDR(0x00000000)
20d5cb9783SPaul Mundt 
21d5cb9783SPaul Mundt #define PHYS_EPBR_BLOCK		P4SEGADDR(0x1de00000)
22d5cb9783SPaul Mundt #define PHYS_DMAC_BLOCK		P4SEGADDR(0x1fa00000)
23d5cb9783SPaul Mundt #define PHYS_PBR_BLOCK		P4SEGADDR(0x1fc00000)
24d5cb9783SPaul Mundt 
25d5cb9783SPaul Mundt static struct resource emi_resources[] = {
26d5cb9783SPaul Mundt 	[0] = {
27d5cb9783SPaul Mundt 		.start	= PHYS_EMI_CBLOCK,
28d5cb9783SPaul Mundt 		.end	= PHYS_EMI_CBLOCK + 0x00300000 - 1,
29d5cb9783SPaul Mundt 		.flags	= IORESOURCE_MEM,
30d5cb9783SPaul Mundt 	},
31d5cb9783SPaul Mundt 	[1] = {
32d5cb9783SPaul Mundt 		.start	= PHYS_EMI_DBLOCK,
33d5cb9783SPaul Mundt 		.end	= PHYS_EMI_DBLOCK + 0x08000000 - 1,
34d5cb9783SPaul Mundt 		.flags	= IORESOURCE_MEM,
35d5cb9783SPaul Mundt 	},
36d5cb9783SPaul Mundt };
37d5cb9783SPaul Mundt 
38d5cb9783SPaul Mundt static struct superhyway_device emi_device = {
39d5cb9783SPaul Mundt 	.name		= "emi",
40d5cb9783SPaul Mundt 	.num_resources	= ARRAY_SIZE(emi_resources),
41d5cb9783SPaul Mundt 	.resource	= emi_resources,
42d5cb9783SPaul Mundt };
43d5cb9783SPaul Mundt 
44d5cb9783SPaul Mundt static struct resource femi_resources[] = {
45d5cb9783SPaul Mundt 	[0] = {
46d5cb9783SPaul Mundt 		.start	= PHYS_FEMI_CBLOCK,
47d5cb9783SPaul Mundt 		.end	= PHYS_FEMI_CBLOCK + 0x00100000 - 1,
48d5cb9783SPaul Mundt 		.flags	= IORESOURCE_MEM,
49d5cb9783SPaul Mundt 	},
50d5cb9783SPaul Mundt 	[1] = {
51d5cb9783SPaul Mundt 		.start	= PHYS_FEMI_DBLOCK,
52d5cb9783SPaul Mundt 		.end	= PHYS_FEMI_DBLOCK + 0x08000000 - 1,
53d5cb9783SPaul Mundt 		.flags	= IORESOURCE_MEM,
54d5cb9783SPaul Mundt 	},
55d5cb9783SPaul Mundt };
56d5cb9783SPaul Mundt 
57d5cb9783SPaul Mundt static struct superhyway_device femi_device = {
58d5cb9783SPaul Mundt 	.name		= "femi",
59d5cb9783SPaul Mundt 	.num_resources	= ARRAY_SIZE(femi_resources),
60d5cb9783SPaul Mundt 	.resource	= femi_resources,
61d5cb9783SPaul Mundt };
62d5cb9783SPaul Mundt 
63d5cb9783SPaul Mundt static struct resource epbr_resources[] = {
64d5cb9783SPaul Mundt 	[0] = {
65d5cb9783SPaul Mundt 		.start	= P4SEGADDR(0x1e7ffff8),
66d5cb9783SPaul Mundt 		.end	= P4SEGADDR(0x1e7ffff8 + (sizeof(u32) * 2) - 1),
67d5cb9783SPaul Mundt 		.flags	= IORESOURCE_MEM,
68d5cb9783SPaul Mundt 	},
69d5cb9783SPaul Mundt 	[1] = {
70d5cb9783SPaul Mundt 		.start	= PHYS_EPBR_BLOCK,
71d5cb9783SPaul Mundt 		.end	= PHYS_EPBR_BLOCK + 0x00a00000 - 1,
72d5cb9783SPaul Mundt 		.flags	= IORESOURCE_MEM,
73d5cb9783SPaul Mundt 	},
74d5cb9783SPaul Mundt };
75d5cb9783SPaul Mundt 
76d5cb9783SPaul Mundt static struct superhyway_device epbr_device = {
77d5cb9783SPaul Mundt 	.name		= "epbr",
78d5cb9783SPaul Mundt 	.num_resources	= ARRAY_SIZE(epbr_resources),
79d5cb9783SPaul Mundt 	.resource	= epbr_resources,
80d5cb9783SPaul Mundt };
81d5cb9783SPaul Mundt 
82d5cb9783SPaul Mundt static struct resource dmac_resource = {
83d5cb9783SPaul Mundt 	.start	= PHYS_DMAC_BLOCK,
84d5cb9783SPaul Mundt 	.end	= PHYS_DMAC_BLOCK + 0x00100000 - 1,
85d5cb9783SPaul Mundt 	.flags	= IORESOURCE_MEM,
86d5cb9783SPaul Mundt };
87d5cb9783SPaul Mundt 
88d5cb9783SPaul Mundt static struct superhyway_device dmac_device = {
89d5cb9783SPaul Mundt 	.name		= "dmac",
90d5cb9783SPaul Mundt 	.num_resources	= 1,
91d5cb9783SPaul Mundt 	.resource	= &dmac_resource,
92d5cb9783SPaul Mundt };
93d5cb9783SPaul Mundt 
94d5cb9783SPaul Mundt static struct resource pbr_resources[] = {
95d5cb9783SPaul Mundt 	[0] = {
96d5cb9783SPaul Mundt 		.start	= P4SEGADDR(0x1ffffff8),
97d5cb9783SPaul Mundt 		.end	= P4SEGADDR(0x1ffffff8 + (sizeof(u32) * 2) - 1),
98d5cb9783SPaul Mundt 		.flags	= IORESOURCE_MEM,
99d5cb9783SPaul Mundt 	},
100d5cb9783SPaul Mundt 	[1] = {
101d5cb9783SPaul Mundt 		.start	= PHYS_PBR_BLOCK,
102d5cb9783SPaul Mundt 		.end	= PHYS_PBR_BLOCK + 0x00400000 - (sizeof(u32) * 2) - 1,
103d5cb9783SPaul Mundt 		.flags	= IORESOURCE_MEM,
104d5cb9783SPaul Mundt 	},
105d5cb9783SPaul Mundt };
106d5cb9783SPaul Mundt 
107d5cb9783SPaul Mundt static struct superhyway_device pbr_device = {
108d5cb9783SPaul Mundt 	.name		= "pbr",
109d5cb9783SPaul Mundt 	.num_resources	= ARRAY_SIZE(pbr_resources),
110d5cb9783SPaul Mundt 	.resource	= pbr_resources,
111d5cb9783SPaul Mundt };
112d5cb9783SPaul Mundt 
113d5cb9783SPaul Mundt static struct superhyway_device *sh4202_devices[] __initdata = {
114d5cb9783SPaul Mundt 	&emi_device, &femi_device, &epbr_device, &dmac_device, &pbr_device,
115d5cb9783SPaul Mundt };
116d5cb9783SPaul Mundt 
sh4202_read_vcr(unsigned long base,struct superhyway_vcr_info * vcr)117d5cb9783SPaul Mundt static int sh4202_read_vcr(unsigned long base, struct superhyway_vcr_info *vcr)
118d5cb9783SPaul Mundt {
119d5cb9783SPaul Mundt 	u32 vcrh, vcrl;
120d5cb9783SPaul Mundt 	u64 tmp;
121d5cb9783SPaul Mundt 
122d5cb9783SPaul Mundt 	/*
123d5cb9783SPaul Mundt 	 * XXX: Even though the SH4-202 Evaluation Device documentation
124d5cb9783SPaul Mundt 	 * indicates that VCRL is mapped first with VCRH at a + 0x04
125d5cb9783SPaul Mundt 	 * offset, the opposite seems to be true.
126d5cb9783SPaul Mundt 	 *
127d5cb9783SPaul Mundt 	 * Some modules (PBR and ePBR for instance) also appear to have
128d5cb9783SPaul Mundt 	 * VCRL/VCRH flipped in the documentation, but on the SH4-202
129d5cb9783SPaul Mundt 	 * itself it appears that these are all consistently mapped with
130e868d612SSimon Arlott 	 * VCRH preceding VCRL.
131d5cb9783SPaul Mundt 	 *
132d5cb9783SPaul Mundt 	 * Do not trust the documentation, for it is evil.
133d5cb9783SPaul Mundt 	 */
1349d56dd3bSPaul Mundt 	vcrh = __raw_readl(base);
1359d56dd3bSPaul Mundt 	vcrl = __raw_readl(base + sizeof(u32));
136d5cb9783SPaul Mundt 
137d5cb9783SPaul Mundt 	tmp = ((u64)vcrh << 32) | vcrl;
138d5cb9783SPaul Mundt 	memcpy(vcr, &tmp, sizeof(u64));
139d5cb9783SPaul Mundt 
140d5cb9783SPaul Mundt 	return 0;
141d5cb9783SPaul Mundt }
142d5cb9783SPaul Mundt 
sh4202_write_vcr(unsigned long base,struct superhyway_vcr_info vcr)143d5cb9783SPaul Mundt static int sh4202_write_vcr(unsigned long base, struct superhyway_vcr_info vcr)
144d5cb9783SPaul Mundt {
145d5cb9783SPaul Mundt 	u64 tmp = *(u64 *)&vcr;
146d5cb9783SPaul Mundt 
1479d56dd3bSPaul Mundt 	__raw_writel((tmp >> 32) & 0xffffffff, base);
1489d56dd3bSPaul Mundt 	__raw_writel(tmp & 0xffffffff, base + sizeof(u32));
149d5cb9783SPaul Mundt 
150d5cb9783SPaul Mundt 	return 0;
151d5cb9783SPaul Mundt }
152d5cb9783SPaul Mundt 
153d5cb9783SPaul Mundt static struct superhyway_ops sh4202_superhyway_ops = {
154d5cb9783SPaul Mundt 	.read_vcr	= sh4202_read_vcr,
155d5cb9783SPaul Mundt 	.write_vcr	= sh4202_write_vcr,
156d5cb9783SPaul Mundt };
157d5cb9783SPaul Mundt 
158d5cb9783SPaul Mundt struct superhyway_bus superhyway_channels[] = {
159d5cb9783SPaul Mundt 	{ &sh4202_superhyway_ops, },
160d5cb9783SPaul Mundt 	{ 0, },
161d5cb9783SPaul Mundt };
162d5cb9783SPaul Mundt 
superhyway_scan_bus(struct superhyway_bus * bus)163d5cb9783SPaul Mundt int __init superhyway_scan_bus(struct superhyway_bus *bus)
164d5cb9783SPaul Mundt {
165d5cb9783SPaul Mundt 	return superhyway_add_devices(bus, sh4202_devices,
166d5cb9783SPaul Mundt 				      ARRAY_SIZE(sh4202_devices));
167d5cb9783SPaul Mundt }
168d5cb9783SPaul Mundt 
169