1 /* 2 * New-style PCI core. 3 * 4 * Copyright (c) 2004 - 2009 Paul Mundt 5 * Copyright (c) 2002 M. R. Brown 6 * 7 * Modelled after arch/mips/pci/pci.c: 8 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org) 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file "COPYING" in the main directory of this archive 12 * for more details. 13 */ 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <linux/pci.h> 17 #include <linux/init.h> 18 #include <linux/types.h> 19 #include <linux/dma-debug.h> 20 #include <linux/io.h> 21 #include <linux/mutex.h> 22 23 unsigned long PCIBIOS_MIN_IO = 0x0000; 24 unsigned long PCIBIOS_MIN_MEM = 0; 25 26 /* 27 * The PCI controller list. 28 */ 29 static struct pci_channel *hose_head, **hose_tail = &hose_head; 30 31 static int pci_initialized; 32 33 static void __devinit pcibios_scanbus(struct pci_channel *hose) 34 { 35 static int next_busno; 36 static int need_domain_info; 37 struct pci_bus *bus; 38 39 bus = pci_scan_bus(next_busno, hose->pci_ops, hose); 40 hose->bus = bus; 41 42 need_domain_info = need_domain_info || hose->index; 43 hose->need_domain_info = need_domain_info; 44 if (bus) { 45 next_busno = bus->subordinate + 1; 46 /* Don't allow 8-bit bus number overflow inside the hose - 47 reserve some space for bridges. */ 48 if (next_busno > 224) { 49 next_busno = 0; 50 need_domain_info = 1; 51 } 52 53 pci_bus_size_bridges(bus); 54 pci_bus_assign_resources(bus); 55 pci_enable_bridges(bus); 56 } 57 } 58 59 static DEFINE_MUTEX(pci_scan_mutex); 60 61 int __devinit register_pci_controller(struct pci_channel *hose) 62 { 63 if (request_resource(&iomem_resource, hose->mem_resource) < 0) 64 goto out; 65 if (request_resource(&ioport_resource, hose->io_resource) < 0) { 66 release_resource(hose->mem_resource); 67 goto out; 68 } 69 70 *hose_tail = hose; 71 hose_tail = &hose->next; 72 73 /* 74 * Do not panic here but later - this might hapen before console init. 75 */ 76 if (!hose->io_map_base) { 77 printk(KERN_WARNING 78 "registering PCI controller with io_map_base unset\n"); 79 } 80 81 /* 82 * Setup the ERR/PERR and SERR timers, if available. 83 */ 84 pcibios_enable_timers(hose); 85 86 /* 87 * Scan the bus if it is register after the PCI subsystem 88 * initialization. 89 */ 90 if (pci_initialized) { 91 mutex_lock(&pci_scan_mutex); 92 pcibios_scanbus(hose); 93 mutex_unlock(&pci_scan_mutex); 94 } 95 96 return 0; 97 98 out: 99 printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n"); 100 return -1; 101 } 102 103 static int __init pcibios_init(void) 104 { 105 struct pci_channel *hose; 106 107 /* Scan all of the recorded PCI controllers. */ 108 for (hose = hose_head; hose; hose = hose->next) 109 pcibios_scanbus(hose); 110 111 pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq); 112 113 dma_debug_add_bus(&pci_bus_type); 114 115 pci_initialized = 1; 116 117 return 0; 118 } 119 subsys_initcall(pcibios_init); 120 121 static void pcibios_fixup_device_resources(struct pci_dev *dev, 122 struct pci_bus *bus) 123 { 124 /* Update device resources. */ 125 struct pci_channel *hose = bus->sysdata; 126 unsigned long offset = 0; 127 int i; 128 129 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 130 if (!dev->resource[i].start) 131 continue; 132 if (dev->resource[i].flags & IORESOURCE_PCI_FIXED) 133 continue; 134 if (dev->resource[i].flags & IORESOURCE_IO) 135 offset = hose->io_offset; 136 else if (dev->resource[i].flags & IORESOURCE_MEM) 137 offset = hose->mem_offset; 138 139 dev->resource[i].start += offset; 140 dev->resource[i].end += offset; 141 } 142 } 143 144 /* 145 * Called after each bus is probed, but before its children 146 * are examined. 147 */ 148 void __devinit pcibios_fixup_bus(struct pci_bus *bus) 149 { 150 struct pci_dev *dev = bus->self; 151 struct list_head *ln; 152 struct pci_channel *chan = bus->sysdata; 153 154 if (!dev) { 155 bus->resource[0] = chan->io_resource; 156 bus->resource[1] = chan->mem_resource; 157 } 158 159 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { 160 dev = pci_dev_b(ln); 161 162 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 163 pcibios_fixup_device_resources(dev, bus); 164 } 165 } 166 167 /* 168 * We need to avoid collisions with `mirrored' VGA ports 169 * and other strange ISA hardware, so we always want the 170 * addresses to be allocated in the 0x000-0x0ff region 171 * modulo 0x400. 172 */ 173 void pcibios_align_resource(void *data, struct resource *res, 174 resource_size_t size, resource_size_t align) 175 { 176 struct pci_dev *dev = data; 177 struct pci_channel *chan = dev->sysdata; 178 resource_size_t start = res->start; 179 180 if (res->flags & IORESOURCE_IO) { 181 if (start < PCIBIOS_MIN_IO + chan->io_resource->start) 182 start = PCIBIOS_MIN_IO + chan->io_resource->start; 183 184 /* 185 * Put everything into 0x00-0xff region modulo 0x400. 186 */ 187 if (start & 0x300) 188 start = (start + 0x3ff) & ~0x3ff; 189 } else if (res->flags & IORESOURCE_MEM) { 190 if (start < PCIBIOS_MIN_MEM + chan->mem_resource->start) 191 start = PCIBIOS_MIN_MEM + chan->mem_resource->start; 192 } 193 194 res->start = start; 195 } 196 197 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 198 struct resource *res) 199 { 200 struct pci_channel *hose = dev->sysdata; 201 unsigned long offset = 0; 202 203 if (res->flags & IORESOURCE_IO) 204 offset = hose->io_offset; 205 else if (res->flags & IORESOURCE_MEM) 206 offset = hose->mem_offset; 207 208 region->start = res->start - offset; 209 region->end = res->end - offset; 210 } 211 212 void __devinit 213 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 214 struct pci_bus_region *region) 215 { 216 struct pci_channel *hose = dev->sysdata; 217 unsigned long offset = 0; 218 219 if (res->flags & IORESOURCE_IO) 220 offset = hose->io_offset; 221 else if (res->flags & IORESOURCE_MEM) 222 offset = hose->mem_offset; 223 224 res->start = region->start + offset; 225 res->end = region->end + offset; 226 } 227 228 int pcibios_enable_device(struct pci_dev *dev, int mask) 229 { 230 u16 cmd, old_cmd; 231 int idx; 232 struct resource *r; 233 234 pci_read_config_word(dev, PCI_COMMAND, &cmd); 235 old_cmd = cmd; 236 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) { 237 /* Only set up the requested stuff */ 238 if (!(mask & (1<<idx))) 239 continue; 240 241 r = &dev->resource[idx]; 242 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 243 continue; 244 if ((idx == PCI_ROM_RESOURCE) && 245 (!(r->flags & IORESOURCE_ROM_ENABLE))) 246 continue; 247 if (!r->start && r->end) { 248 printk(KERN_ERR "PCI: Device %s not available " 249 "because of resource collisions\n", 250 pci_name(dev)); 251 return -EINVAL; 252 } 253 if (r->flags & IORESOURCE_IO) 254 cmd |= PCI_COMMAND_IO; 255 if (r->flags & IORESOURCE_MEM) 256 cmd |= PCI_COMMAND_MEMORY; 257 } 258 if (cmd != old_cmd) { 259 printk("PCI: Enabling device %s (%04x -> %04x)\n", 260 pci_name(dev), old_cmd, cmd); 261 pci_write_config_word(dev, PCI_COMMAND, cmd); 262 } 263 return 0; 264 } 265 266 /* 267 * If we set up a device for bus mastering, we need to check and set 268 * the latency timer as it may not be properly set. 269 */ 270 static unsigned int pcibios_max_latency = 255; 271 272 void pcibios_set_master(struct pci_dev *dev) 273 { 274 u8 lat; 275 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 276 if (lat < 16) 277 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 278 else if (lat > pcibios_max_latency) 279 lat = pcibios_max_latency; 280 else 281 return; 282 printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n", 283 pci_name(dev), lat); 284 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 285 } 286 287 void __init pcibios_update_irq(struct pci_dev *dev, int irq) 288 { 289 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 290 } 291 292 char * __devinit pcibios_setup(char *str) 293 { 294 return str; 295 } 296 297 /* 298 * We can't use pci_find_device() here since we are 299 * called from interrupt context. 300 */ 301 static void pcibios_bus_report_status(struct pci_bus *bus, 302 unsigned int status_mask, int warn) 303 { 304 struct pci_dev *dev; 305 306 list_for_each_entry(dev, &bus->devices, bus_list) { 307 u16 status; 308 309 /* 310 * ignore host bridge - we handle 311 * that separately 312 */ 313 if (dev->bus->number == 0 && dev->devfn == 0) 314 continue; 315 316 pci_read_config_word(dev, PCI_STATUS, &status); 317 if (status == 0xffff) 318 continue; 319 320 if ((status & status_mask) == 0) 321 continue; 322 323 /* clear the status errors */ 324 pci_write_config_word(dev, PCI_STATUS, status & status_mask); 325 326 if (warn) 327 printk("(%s: %04X) ", pci_name(dev), status); 328 } 329 330 list_for_each_entry(dev, &bus->devices, bus_list) 331 if (dev->subordinate) 332 pcibios_bus_report_status(dev->subordinate, status_mask, warn); 333 } 334 335 void pcibios_report_status(unsigned int status_mask, int warn) 336 { 337 struct pci_channel *hose; 338 339 for (hose = hose_head; hose; hose = hose->next) 340 pcibios_bus_report_status(hose->bus, status_mask, warn); 341 } 342 343 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 344 enum pci_mmap_state mmap_state, int write_combine) 345 { 346 /* 347 * I/O space can be accessed via normal processor loads and stores on 348 * this platform but for now we elect not to do this and portable 349 * drivers should not do this anyway. 350 */ 351 if (mmap_state == pci_mmap_io) 352 return -EINVAL; 353 354 /* 355 * Ignore write-combine; for now only return uncached mappings. 356 */ 357 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 358 359 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 360 vma->vm_end - vma->vm_start, 361 vma->vm_page_prot); 362 } 363 364 #ifndef CONFIG_GENERIC_IOMAP 365 366 static void __iomem *ioport_map_pci(struct pci_dev *dev, 367 unsigned long port, unsigned int nr) 368 { 369 struct pci_channel *chan = dev->sysdata; 370 371 if (unlikely(!chan->io_map_base)) { 372 chan->io_map_base = generic_io_base; 373 374 if (pci_domains_supported) 375 panic("To avoid data corruption io_map_base MUST be " 376 "set with multiple PCI domains."); 377 } 378 379 380 return (void __iomem *)(chan->io_map_base + port); 381 } 382 383 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) 384 { 385 resource_size_t start = pci_resource_start(dev, bar); 386 resource_size_t len = pci_resource_len(dev, bar); 387 unsigned long flags = pci_resource_flags(dev, bar); 388 389 if (unlikely(!len || !start)) 390 return NULL; 391 if (maxlen && len > maxlen) 392 len = maxlen; 393 394 if (flags & IORESOURCE_IO) 395 return ioport_map_pci(dev, start, len); 396 if (flags & IORESOURCE_MEM) { 397 if (flags & IORESOURCE_CACHEABLE) 398 return ioremap(start, len); 399 return ioremap_nocache(start, len); 400 } 401 402 return NULL; 403 } 404 EXPORT_SYMBOL(pci_iomap); 405 406 void pci_iounmap(struct pci_dev *dev, void __iomem *addr) 407 { 408 iounmap(addr); 409 } 410 EXPORT_SYMBOL(pci_iounmap); 411 412 #endif /* CONFIG_GENERIC_IOMAP */ 413 414 #ifdef CONFIG_HOTPLUG 415 EXPORT_SYMBOL(pcibios_resource_to_bus); 416 EXPORT_SYMBOL(pcibios_bus_to_resource); 417 EXPORT_SYMBOL(PCIBIOS_MIN_IO); 418 EXPORT_SYMBOL(PCIBIOS_MIN_MEM); 419 #endif 420