1 /* 2 * New-style PCI core. 3 * 4 * Copyright (c) 2004 - 2009 Paul Mundt 5 * Copyright (c) 2002 M. R. Brown 6 * 7 * Modelled after arch/mips/pci/pci.c: 8 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org) 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file "COPYING" in the main directory of this archive 12 * for more details. 13 */ 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <linux/pci.h> 17 #include <linux/init.h> 18 #include <linux/types.h> 19 #include <linux/dma-debug.h> 20 #include <linux/io.h> 21 #include <linux/mutex.h> 22 23 unsigned long PCIBIOS_MIN_IO = 0x0000; 24 unsigned long PCIBIOS_MIN_MEM = 0; 25 26 /* 27 * The PCI controller list. 28 */ 29 static struct pci_channel *hose_head, **hose_tail = &hose_head; 30 31 static int pci_initialized; 32 33 static void __devinit pcibios_scanbus(struct pci_channel *hose) 34 { 35 static int next_busno; 36 static int need_domain_info; 37 struct pci_bus *bus; 38 39 bus = pci_scan_bus(next_busno, hose->pci_ops, hose); 40 hose->bus = bus; 41 42 need_domain_info = need_domain_info || hose->index; 43 hose->need_domain_info = need_domain_info; 44 if (bus) { 45 next_busno = bus->subordinate + 1; 46 /* Don't allow 8-bit bus number overflow inside the hose - 47 reserve some space for bridges. */ 48 if (next_busno > 224) { 49 next_busno = 0; 50 need_domain_info = 1; 51 } 52 53 pci_bus_size_bridges(bus); 54 pci_bus_assign_resources(bus); 55 pci_enable_bridges(bus); 56 } 57 } 58 59 static DEFINE_MUTEX(pci_scan_mutex); 60 61 int __devinit register_pci_controller(struct pci_channel *hose) 62 { 63 if (request_resource(&iomem_resource, hose->mem_resource) < 0) 64 goto out; 65 if (request_resource(&ioport_resource, hose->io_resource) < 0) { 66 release_resource(hose->mem_resource); 67 goto out; 68 } 69 70 *hose_tail = hose; 71 hose_tail = &hose->next; 72 73 /* 74 * Do not panic here but later - this might hapen before console init. 75 */ 76 if (!hose->io_map_base) { 77 printk(KERN_WARNING 78 "registering PCI controller with io_map_base unset\n"); 79 } 80 81 /* 82 * Scan the bus if it is register after the PCI subsystem 83 * initialization. 84 */ 85 if (pci_initialized) { 86 mutex_lock(&pci_scan_mutex); 87 pcibios_scanbus(hose); 88 mutex_unlock(&pci_scan_mutex); 89 } 90 91 return 0; 92 93 out: 94 printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n"); 95 return -1; 96 } 97 98 static int __init pcibios_init(void) 99 { 100 struct pci_channel *hose; 101 102 /* Scan all of the recorded PCI controllers. */ 103 for (hose = hose_head; hose; hose = hose->next) 104 pcibios_scanbus(hose); 105 106 pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq); 107 108 dma_debug_add_bus(&pci_bus_type); 109 110 pci_initialized = 1; 111 112 return 0; 113 } 114 subsys_initcall(pcibios_init); 115 116 static void pcibios_fixup_device_resources(struct pci_dev *dev, 117 struct pci_bus *bus) 118 { 119 /* Update device resources. */ 120 struct pci_channel *hose = bus->sysdata; 121 unsigned long offset = 0; 122 int i; 123 124 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 125 if (!dev->resource[i].start) 126 continue; 127 if (dev->resource[i].flags & IORESOURCE_PCI_FIXED) 128 continue; 129 if (dev->resource[i].flags & IORESOURCE_IO) 130 offset = hose->io_offset; 131 else if (dev->resource[i].flags & IORESOURCE_MEM) 132 offset = hose->mem_offset; 133 134 dev->resource[i].start += offset; 135 dev->resource[i].end += offset; 136 } 137 } 138 139 /* 140 * Called after each bus is probed, but before its children 141 * are examined. 142 */ 143 void __devinit pcibios_fixup_bus(struct pci_bus *bus) 144 { 145 struct pci_dev *dev = bus->self; 146 struct list_head *ln; 147 struct pci_channel *chan = bus->sysdata; 148 149 if (!dev) { 150 bus->resource[0] = chan->io_resource; 151 bus->resource[1] = chan->mem_resource; 152 } 153 154 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { 155 dev = pci_dev_b(ln); 156 157 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 158 pcibios_fixup_device_resources(dev, bus); 159 } 160 } 161 162 /* 163 * We need to avoid collisions with `mirrored' VGA ports 164 * and other strange ISA hardware, so we always want the 165 * addresses to be allocated in the 0x000-0x0ff region 166 * modulo 0x400. 167 */ 168 void pcibios_align_resource(void *data, struct resource *res, 169 resource_size_t size, resource_size_t align) 170 { 171 struct pci_dev *dev = data; 172 struct pci_channel *chan = dev->sysdata; 173 resource_size_t start = res->start; 174 175 if (res->flags & IORESOURCE_IO) { 176 if (start < PCIBIOS_MIN_IO + chan->io_resource->start) 177 start = PCIBIOS_MIN_IO + chan->io_resource->start; 178 179 /* 180 * Put everything into 0x00-0xff region modulo 0x400. 181 */ 182 if (start & 0x300) 183 start = (start + 0x3ff) & ~0x3ff; 184 } else if (res->flags & IORESOURCE_MEM) { 185 if (start < PCIBIOS_MIN_MEM + chan->mem_resource->start) 186 start = PCIBIOS_MIN_MEM + chan->mem_resource->start; 187 } 188 189 res->start = start; 190 } 191 192 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 193 struct resource *res) 194 { 195 struct pci_channel *hose = dev->sysdata; 196 unsigned long offset = 0; 197 198 if (res->flags & IORESOURCE_IO) 199 offset = hose->io_offset; 200 else if (res->flags & IORESOURCE_MEM) 201 offset = hose->mem_offset; 202 203 region->start = res->start - offset; 204 region->end = res->end - offset; 205 } 206 207 void __devinit 208 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 209 struct pci_bus_region *region) 210 { 211 struct pci_channel *hose = dev->sysdata; 212 unsigned long offset = 0; 213 214 if (res->flags & IORESOURCE_IO) 215 offset = hose->io_offset; 216 else if (res->flags & IORESOURCE_MEM) 217 offset = hose->mem_offset; 218 219 res->start = region->start + offset; 220 res->end = region->end + offset; 221 } 222 223 int pcibios_enable_device(struct pci_dev *dev, int mask) 224 { 225 u16 cmd, old_cmd; 226 int idx; 227 struct resource *r; 228 229 pci_read_config_word(dev, PCI_COMMAND, &cmd); 230 old_cmd = cmd; 231 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) { 232 /* Only set up the requested stuff */ 233 if (!(mask & (1<<idx))) 234 continue; 235 236 r = &dev->resource[idx]; 237 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 238 continue; 239 if ((idx == PCI_ROM_RESOURCE) && 240 (!(r->flags & IORESOURCE_ROM_ENABLE))) 241 continue; 242 if (!r->start && r->end) { 243 printk(KERN_ERR "PCI: Device %s not available " 244 "because of resource collisions\n", 245 pci_name(dev)); 246 return -EINVAL; 247 } 248 if (r->flags & IORESOURCE_IO) 249 cmd |= PCI_COMMAND_IO; 250 if (r->flags & IORESOURCE_MEM) 251 cmd |= PCI_COMMAND_MEMORY; 252 } 253 if (cmd != old_cmd) { 254 printk("PCI: Enabling device %s (%04x -> %04x)\n", 255 pci_name(dev), old_cmd, cmd); 256 pci_write_config_word(dev, PCI_COMMAND, cmd); 257 } 258 return 0; 259 } 260 261 /* 262 * If we set up a device for bus mastering, we need to check and set 263 * the latency timer as it may not be properly set. 264 */ 265 static unsigned int pcibios_max_latency = 255; 266 267 void pcibios_set_master(struct pci_dev *dev) 268 { 269 u8 lat; 270 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 271 if (lat < 16) 272 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 273 else if (lat > pcibios_max_latency) 274 lat = pcibios_max_latency; 275 else 276 return; 277 printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n", 278 pci_name(dev), lat); 279 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 280 } 281 282 void __init pcibios_update_irq(struct pci_dev *dev, int irq) 283 { 284 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 285 } 286 287 char * __devinit pcibios_setup(char *str) 288 { 289 return str; 290 } 291 292 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 293 enum pci_mmap_state mmap_state, int write_combine) 294 { 295 /* 296 * I/O space can be accessed via normal processor loads and stores on 297 * this platform but for now we elect not to do this and portable 298 * drivers should not do this anyway. 299 */ 300 if (mmap_state == pci_mmap_io) 301 return -EINVAL; 302 303 /* 304 * Ignore write-combine; for now only return uncached mappings. 305 */ 306 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 307 308 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 309 vma->vm_end - vma->vm_start, 310 vma->vm_page_prot); 311 } 312 313 #ifndef CONFIG_GENERIC_IOMAP 314 315 static void __iomem *ioport_map_pci(struct pci_dev *dev, 316 unsigned long port, unsigned int nr) 317 { 318 struct pci_channel *chan = dev->sysdata; 319 320 if (unlikely(!chan->io_map_base)) { 321 chan->io_map_base = generic_io_base; 322 323 if (pci_domains_supported) 324 panic("To avoid data corruption io_map_base MUST be " 325 "set with multiple PCI domains."); 326 } 327 328 329 return (void __iomem *)(chan->io_map_base + port); 330 } 331 332 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) 333 { 334 resource_size_t start = pci_resource_start(dev, bar); 335 resource_size_t len = pci_resource_len(dev, bar); 336 unsigned long flags = pci_resource_flags(dev, bar); 337 338 if (unlikely(!len || !start)) 339 return NULL; 340 if (maxlen && len > maxlen) 341 len = maxlen; 342 343 if (flags & IORESOURCE_IO) 344 return ioport_map_pci(dev, start, len); 345 if (flags & IORESOURCE_MEM) { 346 if (flags & IORESOURCE_CACHEABLE) 347 return ioremap(start, len); 348 return ioremap_nocache(start, len); 349 } 350 351 return NULL; 352 } 353 EXPORT_SYMBOL(pci_iomap); 354 355 void pci_iounmap(struct pci_dev *dev, void __iomem *addr) 356 { 357 iounmap(addr); 358 } 359 EXPORT_SYMBOL(pci_iounmap); 360 361 #endif /* CONFIG_GENERIC_IOMAP */ 362 363 #ifdef CONFIG_HOTPLUG 364 EXPORT_SYMBOL(pcibios_resource_to_bus); 365 EXPORT_SYMBOL(pcibios_bus_to_resource); 366 EXPORT_SYMBOL(PCIBIOS_MIN_IO); 367 EXPORT_SYMBOL(PCIBIOS_MIN_MEM); 368 #endif 369